FCH125N60E

FCH125N60E FAIRCHILD | Alldatasheet

Document overview

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• PDF pages: 9

Technical content

Features

• 6 5 0 V @ TJ = 150°C
• T y p . RDS(on) = 102 mΩ
• Ultra Low Gate Charge (Typ. Q g = 75 nC)
• Low Effective Output Capacitance (Typ. C oss(eff) = 258 pF)
• 100% Avalanche Tested
• R o H S C o m p l i a n t

Applications

• Telecom / Sever Power Supplies
• Industrial Power Supplies

Description

SuperFET® II MOSFET is Fairchild Semiconductor’s brand-new high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. This technology is tailored to minimize conduction loss , provide superior switching performance, dv/dt rate and higher avalanche energy. Consequently, SuperFET II MOSFET easy-drive series offers slightly slower rise and fall times compared to the SuperFET II MOSFET series. Noted by the “E” part number suffix, this family helps manage EMI issues and al lows for easier design implementation. For faster switching in applications where switching losses must be at an absolute minimum, please consider the SuperFET II MOSFET series. G S D G D S TO-247

www.fairchildsemi.com2©2015 Fairchild Semiconductor Corporation FCH125N60E Rev. 1.0 FCH125N60E — N-Channel SuperFET® II Easy-Drive MOSFET Package Marking and Ordering Information Electrical Characteristics TC = 25oC unless otherwise noted. Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity FCH125N60E FCH125N60E TO-247 Tube N/A N/A 30 units Symbol Parameter Test Conditions Min. Typ. Max. Unit BVDSS Drain to Source Breakdown Voltage VGS = 0 V, ID = 10 mA, TJ = 25°C 600 - - V VGS = 0 V, ID = 10 mA, TJ = 150°C 650 - - V ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 10 mA, Referenced to 25oC- 0 . 7 - V / oC IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V - - 1 μAVDS = 480 V, VGS = 0 V,TC = 125oC- 2 - IGSS Gate to Body Leakage Current V GS = ±20 V, VDS = 0 V - - ±100 nA VGS(th) Gate Threshold Voltage V GS = VDS, ID = 250 μA2 . 5 - 3 . 5 V RDS(on) Static Drain to Source On Resistance V GS = 10 V, ID = 14.5 A - 102 125 m Ω gFS Forward Transconductance VDS = 20 V, ID = 14.5 A -2 5- S Ciss Input Capacitance VDS = 380 V, VGS = 0 V, f = 1 MHz - 2250 2990 pF Coss Output Capacitance - 60 80 pF Crss Reverse Transfer Capacitance - 17 - pF Coss(eff.) Effective Output Capacitance V DS = 0 V to 480 V, VGS = 0 V - 258 - pF Qg(tot) Total Gate Charge at 10V VDS = 380 V, ID = 14.5 A, VGS = 10 V (Note 4) -7 5 9 5 n C Qgs Gate to Source Gate Charge - 10 - nC Qgd Gate to Drain “Miller” Charge - 33 - nC ESR Equivalent Series Resistance f = 1 MHz - 3.5 - Ω td(on) Turn-On Delay Time VDD = 380 V, ID = 14.5 A, VGS = 10 V, Rg = 4.7 Ω (Note 4) -2 3 5 6 n s tr Turn-On Rise Time - 20 50 ns td(off) Turn-Off Delay Time - 106 222 ns tf Turn-Off Fall Time - 23 56 ns IS Maximum Continuous Drain to Source Diode Forward Current - - 29 A ISM Maximum Pulsed Drain to Source Diode Forward Current - - 87 A VSD Drain to Source Diode Forward Voltage V GS = 0 V, ISD = 14.5 A - - 1.2 V trr Reverse Recovery Time VGS = 0 V, ISD = 14.5 A, dIF/dt = 100 A/μs - 376 - ns Qrr Reverse Recovery Charge - 6.5 - μC Notes: 1. Repetitive rating: pulse width limited by maximum junction temperature. 2. IAS = 6.0 A, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 14.5 A, di/dt ≤ 200 A/μs, VDD ≤ 380 V, Starting TJ = 25°C 4. Essentially independent of operating temperature.

Figure 12. Transient Thermal Response Curve

Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms

• ISD controlled by pulse period VDD L I SD 10V VGS ( Driver ) I SD ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop VSD IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width DUT VDS Driver RG Same Type as DUT VGS • dv/dt controlled by RG
• ISD controlled by pulse period VDD LL I SD 10V VGS ( Driver ) I SD ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop VSD IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width

Figure 17. TO-247, Molded, 3-Lead, Jedec Variation AB ically the warranty therein, which covers Fairchild products.

www.fairchildsemi.com9©2015 Fairchild Semiconductor Corporation FCH125N60E Rev. 1.0 FCH125N60E — N-Channel SuperFET® II Easy-Drive MOSFET PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. 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