FCH110N65F FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

  • 7 0 0 V @ TJ = 150°C
  • T y p . RDS(on) = 96 mΩ (Typ.)
  • Ultra Low Gate Charge (Typ. Q g = 98 nC)
  • Low Effective Output Capacitance (Typ. C oss(eff.) = 464 pF)
  • 100% Avalanche Tested
  • R o H S C o m p l i a n t

Applications

Description

SuperFET® II MOSFET is Fairchild Semiconductor’s brand-new high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. This technology is tailored to minimize conduction loss, provide superior switching perfor- mance, dv/dt rate and higher avalanche energy. Consequently, SuperFET II MOSFET is very suitable for the switching power applications such as PFC, server/telecom power, FPD TV power, ATX power and industrial power applications. SuperFET II FRFET ® MOSFET’s optimized body diode reverse recovery performance can remove additional component and improve system reliability.

  • LCD / LED / PDP TV • Telecom / Server Power Supplies
  • Solar Inverter • AC - DC Power Supply G S D G D S TO-247 long leads

www.fairchildsemi.com©2014 Fairchild Semiconductor Corporation FCH110N65F Rev. C0 FCH110N65F — N-Channel SuperFET® II FRFET® MOSFET Package Marking and Ordering Information Electrical Characteristics TC = 25oC unless otherwise noted. Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity FCH110N65F_F155 FCH110N65F TO-247G03 Tube N/A N/A 30 units Symbol Parameter Test Conditions Min. Typ. Max. Unit BVDSS Drain to Source Breakdown Voltage VGS = 0 V, ID = 10 mA, TJ = 25°C 650 - - VVGS = 0 V, ID = 10 mA, TJ = 150°C 700 - - ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 10 mA, Referenced to 25oC - 0.67 - V/ oC IDSS Zero Gate Voltage Drain Current VDS = 650 V, VGS = 0 V - - 10 μAVDS = 520 V, TC = 125oC- 1 1 0 - IGSS Gate to Body Leakage Current V GS = ±20 V, VDS = 0 V - - ±100 nA VGS(th) Gate Threshold Voltage V GS = VDS, ID = 3.5 mA 3 - 5 V RDS(on) Static Drain to Source On Resistance V GS = 10 V, ID = 17.5 A - 96 110 m Ω gFS Forward Transconductance VDS = 20 V, ID = 17.5 A -3 0- S Ciss Input Capacitance VDS = 100 V, VGS = 0 V, f = 1 MHz - 3680 4895 pF Coss Output Capacitance - 110 145 pF Crss Reverse Transfer Capacitance - 0.65 - pF Coss Output Capacitance V DS = 380 V, VGS = 0 V, f = 1 MHz - 65 - pF Coss(eff.) Effective Output Capacitance V DS = 0 V to 400 V, VGS = 0 V - 464 - pF Qg(tot) Total Gate Charge at 10V VDS = 380 V, ID = 17.5 A, VGS = 10 V (Note 4) - 98 145 nC Qgs Gate to Source Gate Charge - 20 - nC Qgd Gate to Drain “Miller” Charge - 43 - nC ESR Equivalent Series Resistance f = 1 MHz - 0.7 - Ω td(on) Turn-On Delay Time VDD = 380 V, ID = 17.5 A, VGS = 10 V, Rg = 4.7 Ω (Note 4) -3 1 7 2 n s tr Turn-On Rise Time - 21 52 ns td(off) Turn-Off Delay Time - 89 188 ns tf Turn-Off Fall Time - 5.7 21 ns IS Maximum Continuous Drain to Source Diode Forward Current - - 35 A ISM Maximum Pulsed Drain to Source Diode Forward Current - - 105 A VSD Drain to Source Diode Forward Voltage V GS = 0 V, ISD = 17.5 A - - 1.2 V trr Reverse Recovery Time VGS = 0 V, ISD = 17.5 A, dIF/dt = 100 A/μs - 133 - ns Qrr Reverse Recovery Charge - 0.67 - μC Notes: 1. Repetitive rating: pulse width limited by maximum junction temperature. 2. IAS = 8 A, RG = 25 Ω, starting TJ = 25°C. 3. ISD ≤ 17.5 A, di/dt ≤ 200 A/μs, VDD ≤ 380 V, starting TJ = 25°C. 4. Essentially independent of operating temperature typical characteristics.

Figure 12. Transient Thermal Response Curve

Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms

  • ISD controlled by pulse period VDD L I SD 10V VGS ( Driver ) I SD ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop VSD IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width DUT VDS Driver RG Same Type as DUT VGS • dv/dt controlled by RG
  • ISD controlled by pulse period VDD LL I SD 10V VGS ( Driver ) I SD ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop VSD IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width

Figure 17. TO-247, Molded, 3-Lead, Jedec AB Long Leads ically the warranty therein, which covers Fairchild products.

www.fairchildsemi.com9©2014 Fairchild Semiconductor Corporation FCH110N65F Rev. C0 FCH110N65F — N-Channel SuperFET® II FRFET® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WI THOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME AN Y LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERM S OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 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