FC8130 FS | Alldatasheet

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Technical content

Features

 300mA guaranteed output current 75dB typical PSRR at 1kHz  260mV (VOUT=3.3V) typical dropout at 300mA  52µA typical quiescent current  Less than 1µA typical shutdown mode  Fast line and load transient response  1.7V to 5.5V input range  Auto-discharge during chip disable  0.8V to 4.0V output voltage range  Stable with small ceramic output capacitors  Fold-back over current protection  ±1% output voltage tolerance Typical Application IN OUTV N VOUT FC8130 EN GND 1uF Ceramic Capacitor ON/OFF 1uF Ceramic Capacitor

  1. 4. 23 2/16Revision No : 0 FC8130 Connection Diagrams SOT-23-5 OUT 5 4 1 32 NC IN GND EN Thermal pad 1 2 OUT GND ENIN uDFN-4 SC-70-5 VOUT 5 4 1 32 NC VIN GND EN SC-82-4 VIN 1 2 VOUT EN GND Order information FC8130-XXVN05NRR XX Output voltage NRR RoHS & Halogen free package Rating: -40 to 85°C Package in Tape & Reel FC8130-XXFJ04NRR XX Output voltage FJ04 uDFN-4 Package NRR RoHS & Halogen free package Rating:-40 to 85°C Package in Tape & Reel FC8130-XXVI05NRR XX Output voltage NRR RoHS & Halogen free package Rating:-40 to 85°C Package in Tape & Reel FC8130-XXVJ04NRR XX Output voltage NRR RoHS & Halogen free package Rating:-40 to 85°C Package in Tape & Reel
  1. 4. 23 3/16Revision No : 0 FC8130 Order, Marking & Packing Information Package Vout Product ID. Marking Packing SOT-23-5 0.8V FC8130-08VN05NRR 8130 Tracking Code 5 4 1 32 PIN1 DOT Tape & Reel 3Kpcs 1.0V FC8130-10VN05NRR 1.2V FC8130-12VN05NRR 1.3V FC8130-13VN05NRR 1.5V FC8130-15VN05NRR 1.8V FC8130-18VN05NRR 2.5V FC8130-25VN05NRR 2.8V FC8130-28VN05NRR 3.0V FC8130-30VN05NRR 3.3V FC8130-33VN05NRR Package Vout Product ID. Marking Packing uDFN-4 0.8V FC8130-08FJ04NRR X X = tracking code Tape & Reel 8Kpcs 1.0V FC8130-10FJ04NRR X X = tracking code 1.2V FC8130-12FJ04NRR X X = tracking code 1.3V FC8130-13FJ04NRR X X = tracking code 1.5V FC8130-15FJ04NRR X X = tracking code
  1. 4. 23 4/16Revision No : 0 FC8130 1.8V FC8130-18FJ04NRR X X = tracking code 2.5V FC8130-25FJ04NRR X X = tracking code 2.8V FC8130-28FJ04NRR X X = tracking code 3.0V FC8130-30FJ04NRR X X = tracking code 3.3V FC8130-33FJ04NRR X X = tracking code Package Vout Product ID. Marking Packing SC-70-5 0.8V FC8130-08VI05NRR 8130 Tracking Code 5 4 1 32 PIN1 DOT Tape & Reel 3Kpcs 1.0V FC8130-10VI05NRR 1.2V FC8130-12VI05NRR 1.3V FC8130-13VI05NRR 1.5V FC8130-15VI05NRR 1.8V FC8130-18VI05NRR 2.5V FC8130-25VI05NRR 2.8V FC8130-28VI05NRR 3.0V FC8130-30VI05NRR 3.3V FC8130-33VI05NRR
  1. 4. 23 Revision No : 0 FC8130 Package Vout Product ID. Marking Packing SC-82-4 0.8V FC8130-08VJ04NRR 8130 Tracking Code 4 3 1 2 PIN1 DOT Tape & Reel 3Kpcs 1.0V FC8130-10VJ04NRR 1.2V FC8130-12VJ04NRR 1.3V FC8130-13VJ04NRR 1.5V FC8130-15VJ04NRR 1.8V FC8130-18VJ04NRR 2.5V FC8130-25VJ04NRR 2.8V FC8130-28VJ04NRR 3.0V FC8130-30VJ04NRR 3.3V FC8130-33VJ04NRR
  1. 4. 23 6/16Revision No : 0 FC8130 Pin Functions Name SOT-23-5 uDFN-4 SC-70-5 SC-82-4 Function IN 1 4 1 4 Supply Voltage Input. Require a minmum input capacitor of close to 1uF ceramic capacitor to ensure stabi lity and sufficient decoup ling from the ground pin. GND 2 2 2 2 Ground Pin. EN 3 3 3 1 Enable Input. Enable the regulator by pul ling the EN pin High. To keep the regulator on during normal operation, connect the EN pin to V N. The EN pin must not exceed V N under all operating conditions. NC 4 N/A 4 N/A No Connected. OUT 5 1 5 3 Regulated Output Vol tage Pin. A small 1µF ceramic capacitor is needed from this pin to ground to assure stability. Thermal Pad N/A YES N/A N/A The thermal pad with large thermal land area on the PCB will helpful chip power dissipation, to connect it to GND together normally. Functional Block Diagram Vref Fold-back OC IN EN OUT GND FIG.1. Functional Block Diagram of FC8130
  1. 4. 23 7/16Revision No : 0 FC8130 Absolute Maximum Ratings (Notes 1, 2) IN, EN, OUT -0.3V to 6.5V Power Dissipation (Note 6) Storage Temperature Range -65°C to 150°C Junction Temperature (TJ) 150°C Lead Temperature ( Soldering, 10 sec.) 260°C ESD Rating Human Body Mode l 2KV Machine Model 200V Operating Ratings (Note 1, 2) Supply Voltage 1.7V to 5.5V Operating Temperature Range -40°C to 85°C Thermal Resistance: Symbol θJA(Note 3) θJc(Note 4) uDFN-4 110(℃/W) 23(℃/W)

Electrical Characteristics

Unless otherwise specified, all limits guaranteed for VN = VOUT +1V (Note 5), VEN=V N, C N = COUT = 1µF, TA = 25°C. Boldface limits apply for the operating temperature extremes: -40°C and 85°C. Symbol Parameter Conditions Min Typ (Note 7) Max Units VIN Input Voltage 1.7 5.5 V VOUT Output Voltage 0.8 4.0 V ΔVOTL Output Voltage Tolerance Vout> 2.0V, T=25℃ X0.99 X1.01 V Vout< =2.0V, T=25℃ -20 +20 mV Vout>2V, -40~85℃ X0.97 X1.03 V Vout< =2V, -40~85℃ -60 60 mV IOUT Maximum Output Current Average DC Current Rating 300 mA Icl Current Limit Vin=Vout+1V 420 mA ISC Short Current Limit 40 mA IQ Quiescent C urrent IOUT = 0mA 52 75 µA ISD Shutdown Supply Current VOUT = 0V, EN = GND 0.2 1 µA VDO Dropout Voltage (Note 5) IOUT = 300mA, Vout=0.8V 860 mV IOUT = 300mA, Vout=1.2V 580 IOUT = 300mA, Vout=1.5V 440 IOUT = 300mA, Vout=1.8V 380 IOUT = 300mA, Vout=2.8V 290 IOUT = 300mA, Vout=3.3V 260 ΔVOUT Line Regulation IOUT = 1mA, (VOUT + 1V) ≤ V N ≤ 5.5V 0.02 0.1 %/V Load Regulation 1mA ≤ IOUT ≤ 300mA 10 30 mV PSRR Power supply rejection ratio f = 1kHz, Ripple 0.2 Vp-p, Vin=Set Vout +1V, Iout = 30mA 75 dB en Output Voltage Noise VOUT=0.8V, IOUT=30mA, 10Hz ≤ f ≤ 100kHz 40 µVRMS VEN EN Input Threshold 1.0 V 0.4

  1. 4. 23 8/16Revision No : 0 FC8130 IEN EN Input Bias Current EN=GND or VIN 0.1 1 µA Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: All voltages are with respect to the potential at the ground pin. Note 3: θ JA is measured in the natural convection at TA=25℃ on a high effective thermal conductivity test board (2 layers, 2S0P). Note 4: θJC represents the resistance t o the heat flows th e chip to package top case Note 5: Dropout voltage is measured by reducing VIN until VOUT drops 100mV from its nominal value at VN -VOUT = 1V. Note 6: Maximum Power dissipation for the device is calculated using the following equations: JAθ AT - J(MAX)T DP = Where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction -to-ambient thermal resistance. E.g. for the SOT-23-5 packageθJA = 152°C/W, TJ (MAX) = 150°C and using TA= 25°C, the maximum power dissipation is found to be 0.82W. The derating factor (-1/ θJA) = -6.6mW/°C, thus below 25°C the power dissipation figure can be increased by 6.6mW per degr ee, and similarity decreased by this factor for temperatures above 25°C. N ote 7: Typical values represent the most likely parametric norm.
  1. 4. 23 9/16Revision No : 0 FC8130 Typical Performance Characteristics Unless otherwise specified, VIN = VOUT (NOM) + 1V, VEN=VIN, CIN = COUT = 1µF, TA = 25°C PSRR vs. Frequency (VOUT=0.8V) PSRR vs. Frequency (VOUT=3.3V) Cround Current vs. VIN (VOUT=0.8V) Ground Current vs. IOUT (VOUT=0.8V) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 Vin r un urr n (u 100 120 140 160 0 40 80 120 160 200 240 280 320 360 ut m r u urr n u Output Voltage Noise Output Current Limit (Fold-back)
  1. 4. 23 10/16Revision No : 0 FC8130 Typical Performance Characteristics (cont.) Unless otherwise specified, VN= VOUT (NOM) + 1V, VEN=V N, C N = COUT = 1µF, TA = 25°C Enable Response (VOUT=0.8V) Disable Response (VOUT=0.8V) Load transient (VOUT=0.8V, IOUT=50mA to 100mA) Load transient (VOUT=0.8V, IOUT=1mA to 300mA)
  1. 4. 23 11/16Revision No : 0 FC8130

Application Information

Referring to Fig.1 as shown in the Functional Block Diagram section, the FC8130 adopts the classical regulator topology in which negative feedback control is used to perform the desired voltage regulating function . The sub Vout-select form the feedback circuit which s amples the output voltage for the e rror amplifier’s non-inverting input. The inverting input is set to the bandgap reference voltage. Du e to its high open-loop gain, the error amplifier ensures that the sampled output feedback voltage at its non-inverting input is virtually equal to the preset voltage reference voltage. The error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage to the P-channel MOS pa ss transistor, which controls the amount of current reaching the output. If there are changes in the output voltag e du e to load changes, the feedback resistors register these changes to the non-inverting input of the error amplifier. The error amplifier then adjusts its driving voltage to maintain virtual short betw een its two input nodes under a ll loading conditions. The regulation of the output voltage is achieved as a direct result of the error amplifier keeping its input voltages equal. This negative feedback control topo logy is further augmented by the shutdown, the temperature and current protection circuitry. Output Capacitor The FC8130 is specially designed for use with ceramic output capacitors of as low as 1μF to take advantage of the savings in cost and space, as well as the superior filtering of high frequency noise. Capacitors of higher value or other types may be used, but it is im portant to make sure its equivalent series re sistance (ESR) be restricted to less than 0. 5Ω. The use of larger capacitors with s maller ESR values is desirable for applications involving large and fast input or output transients, as well as situations where the a pplication systems are not physically located immediately adjacent to the battery power source. Typical ceramic capacitors suitable for use with the FC8130 are X5R and X7R. The X5R and the X7R capacitors are ab le to maintain their capacitance values to within ±20% and ±10%, respectively, as the temperature increases. No-Load Stability The FC8130 is capable of stable operation during no-load conditions, a mandatory feature for some applications such as CMOS RAM keep -alive operations. Input Capacitor A minimum input capacitance of 1µF is required for FC8130. The capacitor value may be increased without limit. Improper workbench set-ups may have adve rse effects on the normal operation of the regulator. A case in point is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. This will establish a pseudo LCR network, and is likely to happen under high current conditions or near dropout. A 10µF tantalum input capacitor will dampen the parasitic LCR action thanks to its high ESR. H owe ver, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions.

  1. 4. 23 12/16Revision No : 0 FC8130 Power Dissipation Thermal overload results from excessive power dissipation that causes the IC junction temperature to increase beyond a safe operating level. The concept of ther mal resistance θJA (°C/W) is often used to describe an IC junction’s relative readiness in allowing its thermal energy to dissipate to its ambient air. An IC junction with a low thermal resistance is preferred because it is relativ ely effective in di ssipating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. The relationship between θJA and TJ is as follows: TJ = θJA x (PD) + TA T A is the ambient temperature, and PD is the power generated by the IC and can be written as: PD = IOUT (VIN - VOUT) As the above equations show, it is desirable to work with ICs whose θJA values are small suc h that T J does not increase strongly with P D. To avoid ther mally overloading the EMP8130, refrain from exceeding the absolute maximum junction temperature rating of 150°C under continuous operating condition s. Overstressing the regulator with high loading currents and elevated input-to-output differential voltages can increase the IC die temperature significantly. Shutdown The FC8130 enters sleep mode when the EN pin is low. When this occurs, the pass transistor, the error amplifier, and the biasing circuits, including the bandgap reference, are turned off, thus reducing the supply current to typically < 1uA. The low supply current makes the FC8130 best suited for battery-powered applications. The maximum guaranteed voltage at the EN pin to enter sleep mode is 0.4V. A minimum guaranteed voltage of 1.0V at the EN pin will activate the FC8130. To const antly keep the regulator on, direct co nnection of the EN pin to the VIN pin is allowed.
  1. 4. 23 13/16Revision No : 0 FC8130 Package Outline Drawing SOT-23-5 TOP VIEW SIDE VIEW PIN#1 MARK 1 3 5 4 DETAIL E E1 e A A1 L 1 3 DET AIL c D b Min. Max. A 0.90 1.45 A1 0.00 0.15 b 0.30 0.50 c 0.08 0.25 D 2.70 3.10 E 1.40 1.80 E1 2.60 3.00 e L 0.30 0.60

0.95 BSC

  1. 4. 23 14/16Revision No : 0 FC8130 Package Outline Drawing uDFN-4L (1mmx1 mm) L b 1 2 3 4 K D2 D E e A TOP VIEW BOTTOM VIEW SIDE VIEW Min Max A 0.5 0.6 Min Max A1 0 0.05 D2 0.4 0.6 A3 E2 0.4 0.6 b 0. 175 0. 275 D E e L 0.2 0.5 K 0.2 - 0.150 REF.

1.00 BSC

0.625 BSC

Dimension in mmSymbol Dimension in mm Exposed pad

  1. 4. 23 15/16Revision No : 0 FC8130 Package Outline Drawing SC-70-5 TOP VIEW 1 3 6 4 D E E1 b DETAIL A L C DET AIL A SIDE VIEW b e A D Min. Max. A 0.80 1.10 A1 0.00 0.10 b 0.15 0.30 c 0.08 0.22 D 1.85 2.15 E 1.10 1.40 E1 1.80 2.40 e L 0.26 0.46 Dimension in mmSymbol

0.65 BSC

＊ This drawing includes SC70 5&6 lead. For 5 lead packages, the No.5 was removed.

  1. 4. 23 16/16Revision No : 0 FC8130 Package Outline Drawing SC-82-4 TOP VIEW 1 2 4 3 D e E E1 b DETAIL A L C DET AIL A SIDE VIEWBOTTOM VIEW A D Min. Max. A 0.80 1.10 A1 0.00 0.10 b 0.15 0.30 b1 0.30 0.60 c 0.08 0.22 D 1.85 2.15 E 1.10 1.40 E1 1.80 2.40 e L 0.26 0.46

1.1875 BSC

1.30 BSC