FC74VHC1G02 FS | Alldatasheet

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Technical content

The FC74VHC1G02 is an advanced high speed CMOS 2–input NOR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. FC74VHC1G02 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the FC74VHC1G02 to be used to interface 5 V circuits to 3 V circuits.

  • High Speed: t PD = 3.0 ns (Typ) at V CC = 5 V
  • Low Power Dissipation: I CC = 2 uA (Max) at T A = 25°C
  • Power Down Protection Provided on Inputs
  • Balanced Propagation Delays
  • Pin and Function Compatible with Other Standard Logic Families
  • Chip Complexity: FETs = 56; Equivalent Gates = 14 V3d SC–88A / SOT–353/SC–70 DF SUFFIX MARKING DIAGRAMS Pin 1 d = Date Code

Figure 1. Pinout (Top View) Figure 2. Logic Symbol

1 IN B

2 IN A

3 GND

4 OUT Y

5 V CC

  1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

not implied. Functional operation should be restricted to the Recommended Operating Conditions.

  1. Tested to EIA/JESD22–A114–A
  2. Tested to EIA/JESD22–A115–A

Figure 3. Failure Rate vs. Time

  1. 09. 23 3/4Revision No : 0 FC74VHC1G02 DC ELECTRICAL CHARACTERISTICS V CC T A = 25°C T A < 85°C –55°C<TA<125°C Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max U nit V IH V5 . 15 . 15 . 1 0 . 2l e v e L – h g i H m u m i n i M 1 . 21 . 21 . 2 0 . 3e g a t l o V t u p n I 4.5 3.15 3.15 3.15 5.5 3.85 3.85 3.85 V L V 5 . 05 . 05 . 00 . 2l e v e L – w o L m u m i x a M 9 . 09 . 09 . 00 . 3e g a t l o V t u p n I 4.5 1.35 1.35 1.35 5.5 1.65 1.65 1.65 V N = V H or V L I OH = –4 mA 3.0 2.58 2.48 2.34 I OH = –8 mA 4.5 3.94 3.80 3.66 V N = V H or V L I OL = 4 mA 3.0 0.36 0.44 0.52 I OL = 8 mA 4.5 0.36 0.44 0.52 Leakage Current I CC Maximum Quiescent V IN = V CC or GND 5.5 2.0 20 40 µA Supply Current 6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD • V CC •f in + I CC . C PD is used to determine the no– load dynamic power consumption; P D = C PD • V CC 2 • f in + I CC • V CC . AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns TA = 25°C TA < 85°C Symbol Parameter T est Conditions Min Typ Max Min Max Min Max Unit t PHL Propagation Delay, C L = 50 pF 5.4 1 1.4 13.0 15.5 Input A or B to Y C L = 50 pF 3.8 7.5 8.5 10.0 C N Maximum Input 5.5 10 10 10 pF Capacitance Typical @ 25°C, V CC = 5.0 V C PD Power Dissipation Capacitance (Note 6) 11 pF –55°C<TA<125°C