FC51J16SJTS1A ESMT | Alldatasheet

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Features

 Compatible to JEDEC Embedded Multi Media Card (eMMC) Electrical Standard (5.1)  Data bus width: 1bit (default), 4bit and 8bit  Not support large sector size (4KB)  Temperature: Operation (-25°C~85°C), storage (-40°C~85°C)  User Density: Density LBA (Hex) LBA (Dec) Capacity (Bytes)

16 GB 0x1D7A000 30,908,416 15,825,108,992

Table 1. Read/Write Performance

  1. Values given for an 8-bit bus width, running HS400 mode from ESMT proprietary tool
  2. Performance numbers might be subject to changes without notice.

Table 2. Capacity according to partition

16 GB 4096 KB 4096 KB 4096 KB

Table 3. Ordering Information

Figure 1. Ball Configuration (Top View)

Table 4. Ball Descriptions

  1. I: input; O: Output; PP: push-pull; OD: open-drain; NC: Not connected (or logical high); S: power supply.

Table 5. OCR Register Table 6. CID Register

Table 7. CSD Register

Table 8. Extended CSD Register

4 R [305:302] 0h

Table 8. Extended CSD Register - Continued

Note：Reserved bits should be read as “0”.

Figure 2. Bus Signal Levels Table 9. Bus Signal Levels

Figure 3. Bus Timing in Single Data Rate Mode

Table 10. High-Speed Device Interface Timing

  1. CLK timing is measured at 50% of VCCQ.
  2. A e•MMC shall support the full frequency range from 0 Mhz - 26 Mhz, or 0 MHz - 52 MHz
  3. Device can operate as high-speed Device interface timing at 26 MHz clock frequency.
  4. CLK rise and fall times are measured by min (VIH) and max (VIL).
  5. Inputs CMD, DAT rise and fall times are measured by min (V IH) and max (V IL), and outputs CMD, DAT rise an d fall times

are measured by min (VOH) and max (VOL).

Table 11. Backward Compatible Device Interface Timing

  1. The Device must always start with the backward -compatible interface timing. The timing mode can be switched to high -
  2. CLK timing is measured at 50% of VCCQ.
  3. For compatibility with Devices that support the v4.2 standard or earlier, host should not use > 26 MHz before switching to

high-speed interface timing.

  1. CLK rise and fall times are measured by min (VIH) and max (VIL).
  2. tOSU and tOH are defined as values from clock rising edge. However, there may be Devices or devices which utilize clock

Figure 4. Bus Timing in Dual Data Rate Mode

Table 12. High-speed Dual Data Rate Interface Timing

  1. CLK timing is measured at 50% of VCCQ.
  2. Inputs DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs DAT rise and fall times are measured

Figure 5. HS200 Device Clock Timing Note1: VIH denote VIH(min.) and VIL denotes VIL(max.). reference point for timing measurements. Table 13. HS200 Device Clock Timing

Figure 6. HS200 Device Input Timing Note1: tISU and tIH are measured at VIL(max.) and VIH(min.). Note2: VIH denote VIH(min.) and VIL denotes VIL(max.). Table 14. HS200 Device Input Timing

Figure 7. HS200 Device Output Timing Note: VOH denotes VOH(min.) and VOL denotes VOL(max.). Table 15. HS200 Device Output Timing Does not include a long term temperature drift. Delay variation due to temperature change after tuning. ∆TPH is 2600ps for ΔT from -25 deg.C to 125 deg.C during operation. Host path may add Signal Integrity induced noise, skews, etc. Expected TVW at Host input is larger than 0.475UI. Note: Unit Interval (UI) is one bit nominal time. For example, UI=5ns at 200MHz.

Figure 8. tPH Consideration

The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode. Figure 9. HS400 Device Input Timing Note: VT = 50% of VCCQ, indicates clock reference point for timing measurements. Table 16. HS400 Device Input Timing Slew rate SR 1.125 - V/ns With respect to VIH/VIL. Allowable deviation from an ideal 50% duty cycle. Minimum pulse width tCKMPW 2.2 - ns With respect to VT. Slew rate SR 1.125 - V/ns With respect to VIH/VIL.

The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC status response. Figure 10. HS400 Device Output Timing Note: VT = 50% of VCCQ, indicates clock reference point for timing measurements. Table 17. HS400 Device Output Timing Minimum pulse width tDSMPW 2.0 - ns With respect to VT. Read pre-amble tRPRE 0.4 - tPERIOD Max value is specified by manufacturer. Read post-amble tRPST 0.4 - tPERIOD Max value is specified by manufacturer.

Table 18. Bus Signal Line Load Table 19. HS400 Capacitance and Resistors Note: Recommended maximum value is 50 KOhm for 1.8V interface supply voltages.

Table 20. Supply Voltage Table 21. Power Consumption

  1. Test condition: Bus width x8, 200 MHz DDR, 512KB data transfer, measured on internal board, 25°C.
  2. The measurement for max RMS current is the average RMS current consumption over a period of 100ms.
  3. Power measurement conditions: Bus configuration = x8, No CLK.
  4. Bus configuration = x8, No CLK. In sleep state, triggered by CMD5. Flash VCC power supply is switched off.

Table 22. Push-pull signal level - high-voltage Table 23. Push-pull signal level - 1.70V-1.95V VCCQ voltage range

  1. 0.7 * VDD for MMC4.3 and older revisions.
  2. 0.3 * VDD for MMC4.3 and older revisions.

Figure 11. 153-BALL (11.5x13 mm) Controlling dimension: Millimeter.

ESMT FC51J16SJTS1A (2AF) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Jul. 2023 Revision: 1.0 30/31

Revision History

0.1 2023/02/02 Original 0.2 2023/03/14 1. Add the specification of Power Consumption 2. Modify the description of Extended CSD Register [184] 0.3 2023/05/18 Modify CSD and Extended CSD Register table 1.0 2023/07/12 Delete Preliminary

ESMT FC51J16SJTS1A (2AF) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Jul. 2023 Revision: 1.0 31/31 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ES MT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human live s or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.