FC4057A420QD16

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 INTRODUCTION  FEATURES The FC4057 is a highly integrated st andalone switch mode single-cell Li-Ion battery charger. It utilizes a 1.5MHz synchronous buck converter topology to reduce power dissipation during charging. Low power dissipation, an internal integrated MOSFET and current sense resistor allow a physically small charger that can be embedded in a wide range of space-limited portable applications with high capacity batteries. The single ce ll charger has a single input that operates from either a USB port o r AC wa ll adapter for a versatile solution. The battery is charged in three phases: trickle- charge, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and shutdown the charge if the internal temperature threshold is exceeded. The FC4057 includes com plete charge termination circuitry, automatic recharge and a ±1% float voltage. Battery charge current, charge timeout and end-of-charge indication parameters are set with external components. Additional fea tures include defective battery detection, battery overvoltage protection and a voltage-based battery pack thermistor monitoring input (NTC) that monitors battery temperature for safe charging.  APPLICATIONS  Battery Back-Up Systems  Tablets and Portable Mobile Internet Devices  Netbook, Smartbook  Portable Media Players  IPod, iPhone, iPad Docking  Bluetooth speaker & 2.4G Wireless speaker  Smart Phones  Portable Data Capture Terminals  Personal Medical Products  Portable Instruments  3G/4G Wireless Routers  1.5MHz High-Efficiency Switch Mode Charger  Single Input Mini-USB/Adapter Charger –7V Maximum Input Voltage Rating –5.5 V Maximum Operating Input Voltage –Compatible with Current Limited Adapters  High Integration for Reduced BOM Count and Board Space Savings –Low RDS(ON) Integrated Power FETs for Up to 2A Charge Rate –Integrated Charge Current Sense Resistor –Integrated Reverse Current Blocking Element  Low Power Dissipation  Accurate Battery Management Functions – 1% Battery Regulation Accu racy – 10% Charge Current Accuracy  Remote Sensing at Battery Terminals  IDET Blanking  Programmable Charge Current Detection/Termination  Automatic Recharge  Complete System Level Protection –Input UVLO, Sleep Mode, VIN_DPM, Battery Over-voltage Protection(Battery OVP) –Reverse Leakage Protection Prevents Battery Drainage –Hard Short On The Battery Terminals Protection –High Rate Charge Current Limit –Cycle By Cycle Current Limit –Thermal Shutdown –Voltage Based, NTC Monito ring Input For Temperature Qualified Charging –Programmable Charge Safety Timer –Defective Battery Detection –Soft-Start Feature to Reduce Inrush Current  Status Output for Charging and Faults 2A Synchronous Buck Single Cell Li-Ion USB/Adapter Charger FC4057 Series SEMICONDUCTOR TECH NIC AL DATA FC4057A420QD16 2020. 06. 12 1/40Revision No : 0

 ORDER INFORMATION(1) Battery Float Voltage Package 4.20V QFN4X4-16 4.35V QFN4X4-16 (1)Contact Chipower to check availability of other battery float voltage versions.  PIN CONFIGURATION: PIN FUNCTIONS PIN TYPE(1) DESCRIPTIONNO. NAME

1 BAT I/O

Battery Charger Output Terminal. Connect to the positive terminal of the battery. Connect a 10μF ceramic chip capacitor between BAT and PGND to keep the ripple voltage small. 2 SENSE I Internal Sense Resistor. Connect to external inductor.

3 PGND P

Power Ground. Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the internal n-channel low-side FET. On PCB layou t, connected directly to ground connection of input and output capacitors of the charger and should be connected to the ground plane to return current through the internal low-side FET.

4 GND SENS I

Ground Sense. Connect this pin to the negative battery terminal. GNDSENS provides a Kelvin connection for PGND and must be connected to PGND schematically.

5 SW O

Switch Node Connection. This pin connects to the drains of the internal main and synchronous power MOSFET switches. Connect to external inductor. Keep these PCB trace lengths as short and wide as possible to reduce EMI and voltage overshoot. (1)I = input; O = output; P = power TOP VIEW 5 6 7 13146 1 5 1 BAT SENSE PGND GNDSENS BATSENS TIMER IDET SS PROG NTC FAULT VINSENSE SW EN PVIN CHRG

Electrical Characteristics

Device No. FC4057A420QD16 FC4057A435QD16 FC4057A420QD16 2020. 06. 12 2/40Revision No : 0

PIN FUNCTIONS (continued) PIN TYPE(1) DESCRIPTIONNO. NAME

6 EN I

Chip Enable Input Pin. Pulling the EN pin high places the FC4057 into a low power state where the BAT drain current drops to less than 3μA and the supply current is reduced to less than 50µA. For normal free running operation, pull the EN pin low.

7 C HRG I

Open-Drain Charge Status Output. When the battery is being charged, CHRG is pulled low by an internal N-channel MOSFET. When the charge current drops below the IDET threshold (set by the RIDET programming resistor) for more than 5 milliseconds, the N-channel MOSFET turns off and a 30µA weak current source is connected from CHRG to ground. (This signal is latched and is reset by initiating a new charge cycle.) When the timer runs out or the input supply is removed, the current source will be disconnected and the CHRG pin is fo rced to a high impedance state. A battery pack temperature fault causes this pin to blink.

8 PV IN I

Positive Supply Voltage Input. This pin connects to the power devices inside the chip. VIN ranges from 4.5V to 5.5V for normal operation. Operation down to the VIN_DPM is allowed with current limited wall adapters. Decouple with a 10μF or larger surface mounted ceramic capacitor.

9 V INSENSE I

Positive Supply Sense Input. This pin connects to the inputs of all input comparators (UVL, VINSENSE to VBATSENS, VIN_DPM). It also supplies power to the controller portion of this chip. When the BATSENS pin rises to within 130mV of VINSENSE, the FC4057 enters sleep mode, dropping IIN to 50µA. Tie this pin to the terminal of the PVIN by a R&C decoupling circuit.

10 FAULT I

Battery Fault. This pin is a logic high if a shorted battery is detected or if a battery pack temperature fault is detected. A battery pack temperature fault occurs with the NTC temperature monitor circuit enabled and the thermistor temperature is either below 0°C or above 50°C (typical). (1) I = input; O = output; P = power FC4057A420QD16 2020. 06. 12 3/40Revision No : 0

PIN FUNCTIONS (continued)

11 NTC I

Input to the NTC (Negative Temperature Coefficient) Thermistor Temperature Monitoring Circuit. Under normal operation, tie a thermistor from the NTC pin to the GNDSENS pin and a resistor of equal value from NTC to VINSENSE. When the voltage on this pin is above 0.74VINSENSE (Cold, 0°C) or below 0.29VINSENSE (Hot, 50°C), charging is disabled and the CHRG pin blinks. When the voltage on NTC comes back between 0.74VINSENSE and 0.29VINSENSE, the timer continues where it left off and charging resumes. There is approximately 3°C of temperature hysteresis associated with each of the input comparators. If the NTC function is not used, connects the NTC pin to GNDSENS. This will disable all of the NTC functions. NTC should never be pulled above VINSENSE.

12 PROG O

Charge Current Program. The RPROG resistor connects from this pin to GNDSENS, setting the current: RPROG = 1.130K IBAT (AMPS) where IBAT is the high rate battery charging current.

13 IDET O

Charge Rate Detection Threshold. Connecting a resistor, RIDET to GNDSENS programs the charge rate detection threshold. If RIDET = RPROG, CHRG provides an IBAT/10 indication. For other thresholds see the Applications Information section.

14 SS O

Soft-Start/Compensation. Provides soft-start function and compensation for the float voltage control loop and compensation for the charge current control loop. Tie a soft-start/compensation capacitor between this pin and GNDSENS.

15 T IMER O

Timer Capacitor. The timer period is set by placing a capacitor, CT MER, to GNDSENS. Set CTIMER to: CTIMER = Time (Hrs) • 0.09(µF) where time is the desired taper timer charging time. Connect this pin to IDET to disable the timer. Connect this pin to GNDSENS to end battery charging when IBAT drops below the IDET charge rate threshold.

16 BAT SENS I

Battery Sense Input. An internal resistor divider sets the final float voltage at this pin. The resistor divider is disconnected in sleep mode or when EN = H to reduce the battery drain current. Connect this pin to the positive battery terminal.

17 Exposed

Pad(bottom) P Ground. This pin must be soldered to the PCB ground for electrical contact and rated thermal performance. There is an internal electrical connection between the exposed pad and the PGND pin of the device. Do not use the Exposed Pad as the primary ground input for the device. PGND pin must be connected to ground at all times. (1)I = input; O = output; P = power FC4057A420QD16 2020. 06. 12 4/40Revision No : 0

 ABSOLUTE MAXIMUM RATINGS(1) (unless otherwise specified, TA=25°C) PARAMETER SYMBOL RATINGS UNITS Input Voltage(2) t<1ms，DC<1% PVIN,VINSENSE -0.3~7 V Steady State -0.3~ 6 SW, SENSE, BAT, BATSENS, SS, FAULT, CHRG, EN, NTC, PROG, IDET, TIMER Voltage(2) -0.3~6 V Output sink current ICHRG 10 mA Power Dissipation QFN4x4-16 PD 2000 mW Operating free air temperature range(3) TA -40~85 °C Operating Junction Temperature(4) Tj -40~125 °C Storage Temperature Range Tstg -65~+125 °C Lead Temperature (Soldering, 10s) Tsolder 260 °C ESD rating(5) Human Body Model - (HBM) 2 kV Machine Model- (MM) 200 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages are with respect to network ground terminal. (3) The FC4057 is guaranteed to meet performance specifications from 0°C to 85°C. Specification s over the –40°C to 85° C operating temperature range are assured by design, characterization and correlation with statistical process controls. (4) This IC includes overtemperature protection that is intended to protect the device during momentary overload. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. (5) ESD testing is performed according to the respective JESD22 JEDEC standard. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin.  RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNITS Supply voltage at PVIN, VINSENSE 4.5(1) 5.5 (2) V Charge current, IBAT 2 A Operating free air temperature range, TA 0 85 °C Operating junction temperature range, Tj 0 125 °C (1) If PVIN and VINSENSE is between UVLO and 4.5V, and above the battery voltage, then the IC is active (can deliver some charge to the battery), but the IC will have limited or degraded performance (some functions may not meet data sheet specifications). The battery may be undercharged (VFLOAT less than in the specification), but will not be overcharged (VFLOAT will not exceed specification). (2) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on the SW pin. A tight layout minimizes switching noise.

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VIN=5V, VEN=0V, RPROG=560Ω, RIDET=560Ω, TA =25 , unless otherwise specified PARAMETER SYMBOL CO NDITIONS MIN TYP MAX UNITS POWER SUPPLIES Supply Voltage VIN Note1 4.5 5.5 V Supply Current IIN PVIN Connected to VINSENSE, PROG and IDET Pins Open, Charger On 2 mA Shutdown, EN= VIN 50 µA ENABLE EN Low-level Voltage VENL VEN Falling, Device ON 0.3 V EN High-level Voltage VENH VEN Rising, Device Off 1.5 VIN V EN Input Bias Current I(EN) EN=GNDSENS or EN=VIN ±0.01 ±1 µA BATTERY CHARGER Trickle Charge Threshold V TRIKL VBAT Rising Measured from BATSENS to GNDSENS 2.8 2.9 3.0 V VBAT Falling Measured from BATSENS to GNDSENS 2.55 2.65 2.75 V Trickle Charge Current ITRIKL VBAT = 2V 35 50 65 mA Deglitch Time For Trickle Charge To Current Mode Charge Transition t DGL(TRIKL) 5 mS Current Mode Charge Current I BAT RPROG = 560Ω, VBAT =3.5V 1.8 2 2.2 A RPROG = 1.13k, VBAT =3.5V 0.9 1 1.1 A Shutdown, EN= VIN ±5 µA PROG Pin Voltage VPROG RPROG = 560Ω,Current Mode 1.200 V VBAT Regulated Float Voltage V FLOAT Measured from BATSENS to GNDSENS -1 1 % IDET Pin Voltage VIDET RIDET = 560Ω 1.200 V IDET Threshold IIDET RIDET = 560Ω 150 200 250 mA Deglitch Time For IDET tDGL(IDET) Both rising and falling, 2-mV over-drive, tRISE, tFALL=100ns 5 mS Recharge Battery Threshold Voltage VRECHRG VFLOAT – VRECHRG.VBAT Falling Measured from BATSENS to GNDSENS 50 100 150 mV Deglitch Time For Recharge t DGL(RECHRG) VBAT Falling Below VRECHRG, Measured from BATSENS to GNDSENS 4 mS Recharge Time tRECHRG Percent of Desired Taper Timer Charge Time 50 %

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(continued) VIN=5V, VEN=0V, RPROG=560Ω, RIDET=560Ω, TA =25 , unless otherwise specified STATUS OUTPUT CHRG Pin Weak Pull-Down Current IWPD-CHRG VCHRG=1V 15 30 50 µA CHRG Pin Low-level Output Voltage VOL-CHRG ICHRG=5mA(sink current) 0.1 0.4 V CHRG Pin Leakage Current I CHRG-LEAK When output FET is off, VCHRG=5V 1 µA CHRG Pin Pulse Frequency f CHRG-FLASH Battery Temperature Fault, CTIMER=0.1μF 1.5 Hz CHRG Pin Pulse Width tCHRG-PULSE Battery Temperature Fault, CTIMER=0.1μF 333 mS FAULT Pin Low-level Output Voltage VOL-FAULT 1mA Load 0.4 V FAULT Pin High-level Output Voltage VOH-FAULT 1mA Load 4.6 V INPUT PROTECTION VIN Undervoltage Lockout Voltage VUVL VIN Rising, Measured from VINSENSE to GNDSENS 2.9 3.1 V VIN Undervoltage Lockout Hysteresis ΔVUVL Measured from VINSENSE to GNDSENS 200 mV Sleep-mode Entry Threshold V SLP VINSENSE – VBATSENS Falling (Turn-Off), VBATSENS=4V 250 300 350 mV Sleep-mode Exit Hysteresis V (SLP_EXIT) VINSENSE – VBATSENS Rising (Turn-On), VBATSENS=4V 300 350 400 mV Deglitch time for VINSENSE rising above VBATSENS + V(SLP_EXIT) Rising voltage, 2-mV over drive, tRISE=100nS 5 mS Input DPM Threshold VIN_DPM Note2 4.3 4.5 4.7 V Battery OVP Threshold Voltage V (BOVP) VBATSENS threshold over VFLOAT to turn off charger during charge 102 105 108 %V of VFLOAT VBOVP Hysteresis V(BOVP-HYS) Lower limit for VBATSENS falling from above V(BOVP) 5 %V of VFLOAT Battery Short Circuit Threshold Voltage V(BATSHRT) VBATSENS rising, 100 mV hysteresis 1.8 V Battery Short Circuit Current I (BATSHRT) 35 50 65 mA Safety Timer Accuracy tTIMER CTIMER = 0.1μF ±10 % Low-Battery Trickle Charge Time tTRIKL Percent of Desired Taper Timer Charge Time, VBAT< 3.1V, Measured Using BATSENS and GNDSENS Pins 25 %

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VIN=5V, VEN=0V, RPROG=560Ω, RIDET=560Ω, TA =25 , unless otherwise specified Soft-Start Ramp Current ISS VBAT< VFLOAT – 100mV, VBAT Across BATSENS and GNDSENS Pins 6 12.8 16 µA THERMAL SHUTDOWN PROTECTION Thermal Shutdown TTSD 160 °C Thermal Shutdown Hysteresis THYS 20 °C OSCILLATOR Oscillator Frequency fosc 1.2 1.5 1.8 MHz Maximum Duty Cycle DMAX 100 % Minimum Duty Cycle DMIN 0 % POWER SWITCH P-CH MOSFET On Resistance RPFET Measured from PVIN to SW 115 mΩ N-CH MOSFET On Resistance RNFET Measured from SW to PGND 110 mΩ P- CHMOSFET Leakage Current ILKG VEN=VIN=5V, VSW=0V ±0.01 ±1 µA N- CHMOSFET Leakage Current VEN=VIN=VSW=5V ±3 ±10 µA Cycle by Cycle Current Limit I CL 3.5 A Reverse Leakage Current (Measured from SW to PVIN) IREV-LEAK EN=H or L, PVIN=0V, VSW=5V 1 µA BATTERY-PACK NTC MONITOR NTC Pin Hot Temperature Fault Threshold VHOT From NTC to GNDSENS Pin Falling Threshold 0.29 VINSENSE From NTC to GNDSENS Pin Rising Threshold 0.30 VINSENSE NTC Pin Cold Temperature Fault Threshold VCOLD From NTC to GNDSENS Pin Rising Threshold 0.74 VINSENSE From NTC to GNDSENS Pin Falling Threshold 0.72 VINSENSE NTC Disable Threshold V (NTCDIS) From NTC to GNDSENS Pin Falling Threshold 0.015 VINSENSE 0.020 VINSENSE 0.025 VINSENSE NTC Disable Hysteresis ΔV(NTCDIS-HYS) From NTC to GNDSENS Pin 0.010 VINSENSE Deglitch time for NTC change 5 mS Note 1: Operation with current limited wall adapters is allowed down to the VIN_DPM threshold. Note 2: In order to prevent the input power supply from drooping too low and either crash the rest of the system and/or disable the charger, the charger’s V IN_DPM feature may reduce the charge current to prevent the input from dropping below the VIN_DPM threshold. Electrical Characteristics (continued) FC4057A420QD16 2020. 06. 12 8/40Revision No : 0

 TYPICAL APPLICATION CIRCUITS Figure1 Typical Application Circuit SW SENSE VINSENSE PVIN PGND CHRG NTC FAULT EN PROG IDET TIMER SS GNDSENS BATSENS BAT 1.5 μH 280Ω 10μF 0.1μF0.22μF 10μF 4.2V Li-lon VIN 1μF 200Ω4.5V TO 5.5V 4.7μF S RD Q DRIVER 8 3 5 + - OVER CURRENT CPMPARATOR 1.2V 1.1V PROG SHORT COMPARATOR LOW CURRENT VIN GOOD RECHARGE PROG ERROR AMP CHARGE CURRENT ERRON AMP 150mV UNDER VOLTAGE COMPARATOR VOLTAGE REFERENCE + - SHUTDOWN COMPARATOR LOW-BATTERY COMPARATOR RECHARGER COMPARATOR FLOAT VOLTAGE ERROR AMP BATTERY OVERVOLTAGE COMPARATOR 1.2V LOGIC DISCHARGE SS PROG SHORTED SS LOW OVERVOLTAGE CONNECT CHIP OVER TEMP TFAULT TIMER CHRG FAULT SS PWM COMPARATOR OSCILLATOR CURRENT REVERSAL COMPARATOR 50mA IDET COMPARATOR SOFT-START COPMPARATOR TRICKLE ON OVERCURRENT SHUTDOWN LOW BATTERY NTC COMPARATOR CHIP OVERTEMP COMPARATOR 2 1 9 16 4121317 BATSENSVINSENSEBATSENSESWPGNDSENSE SS EN CHRG FAULT TIMER NTC GND IDET PROG GNDSENS Figure 2 Functional Block Diagram  Block Diagram FC4057A420QD16 2020. 06. 12 9/40Revision No : 0

 OPERATION The FC4057 is a constant current, constant voltage Li-Ion battery charger based on a synchronous buck architecture. Low power dissipation makes continuous high rate (2A) battery charging practical. The battery DC charge current is programmed by a resistor R PROG (or a DAC output current) at the PROG pin. Linear vs. Switching Battery Charging The FC4057 performs ba ttery charging using the benefits of the step-down or "buck" architecture to m ultiply the input current when stepping down the output voltage. This property is expressed mathematic ally in the comparison belo w, and pro vides the ability to maximize battery charging from current limited devices, as well as greatly decrease power and heat related dissipation. Linear Charging Linear charge current relationship(1): IBATL≈ IIN Note(1): Equation does not take into account thermal foldback. Efficiency of linear charger: ηL = VBA T VIN Switch-Mode Charging Switch-mode current relationship: IBATS = ηS •VIN •IIN VBA T Where ηS is estimated with 90%. Example: Power Savings Conventional Linear Charger IC: PDL= (VIN-VBAT)•IBAT=(5V-3.5V)•1A=1.5W Switch-Mode Charger IC: PDS = VBA T •IBAT ηS −VBA T •IBA T = 3.5V •1A Battery Charging Charging begins when the VIN voltage rises above the UVLO level (approximately 3.0V), VIN is 250mV greater than the battery voltage and EN is low. At the beginning of the charge cycle, if the battery voltage is less than the trickle charge threshold, 2.65V, the charger goes into trickle charge mode and delivers approximately 50mA to the battery using a linear charger. If the battery voltage stays low for more than one quarter of the taper timer time, the battery is considered faulty , the charge cycle is terminated and the FAULT pin produces a logic high output. When the battery voltage exceeds the trickle charge threshold, the low rate linear charger is turned off and the high rate PWM charger ramps up (based on the SS pin capacitance) reaching its full-scale constant current (set via the PROG pin). When the battery approaches the float voltage, the charge current will start to decrease. When the charge current drops below the charge rate detection threshold (set via the IDET pin) for more than 5ms, an internal c omparator turns off the internal pull-down N-channel MOSFET at the CHRG pin, and connects a weak current source (30μA typical) to ground to indicate a near end-of-charge condition. Taper timer charging time is set by an external capacitor connected to the timer pin. After time out occurs, the charge cycle is terminated and the CHRG pin is forced to a high impedance state. To restart the charge cycle, remove and reapply the input voltage, or momentarily shut the charger down via the EN pin. Also, a ne w charge cycle will begin if the battery voltage drops below the recharge threshold voltage(100mV below the float voltage). The taper timer charging time of a recharge cycle lasts only one-half of the normal taper timer charging time.

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A negative temperature coefficient (NTC) thermistor located close to the battery pack can be used to monitor battery temperature and suspend charging when battery temperature is out of the 0°C to 50°C window. A temperature fault drives the FAULT pin high and makes the CHRG pin blink. When the input voltage (VIN) is present, the charger can be shut down by pulling the EN pin up. IDET Blanking The IDET comparator provides an end-of-charge indication by sensing when battery charge current is less than the IDET threshold. To prevent a false end-of-charge indication from occurring during soft-star t, this comparator is blanked until the battery voltage approaches the float voltage. Automatic Battery Recharge After the charge cycle is completed and if both the battery and the input power supply (wall adapter) are still connected, a new charge cycle will begin if the battery voltage drops below VRECHRG due to self- discharge or external loading. This will keep the battery near maximum capacity at all times without manually restarting the charge cycle. In some applications such as battery charging in GPRS cell phones, large load current transients may cause battery voltage to momentarily drop below the recharge threshold. To prevent these transients from initiating are charge cycle when it is not needed, the output of the recharge comparator is digitally qualified. Only if the battery voltage stays below the recharge threshold for at least 4ms will battery recharging occur. (GPRS qualification is available even if time out is disabled.) Battery Charging Profile There are four loops that influence the charge current:

• Constant current loop (CC)
• Constant voltage loop (CV)
• Input-voltage dynamic power management loop (VIN-DPM)
• Cycle by Cycle current limit During the charging process, all the four loops are enabled and the one that is dominant takes control. The FC4057 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. Figure 3 illustrates the entire battery charging profile, which consists of three phases: 1. Preconditioning-Current Mode (Trickle) Charge - Linear Mode. 2. Constant-Current Mode(Fast) Charge - Switching Mode. 3. Constant-Voltage Mode (Taper) Charge - Switching Mode. Figure 3: Charging Current and Battery Voltage vs Time

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APPLICATION INFORMATION

Because of the high integration in the FC4057 IC, the application circuit based on this Synchronous Buck Li-Ion Charger IC is rather simple. Only low prof ile external components need to be selected for the targeted application specifications. Soft-Start and Compensation Capacitor Selection The FC4057 has a low current trickle charger and a PWM-based high current charger. Soft-start is used whenever the high rate charger is initially turned on, preventing high start-up current. Soft-start ramp rate is set by the internal 12.8μA pull-up current and an external capacitor from SS to GNDSENS. The control r ange on the SS pin is approximately 0.3V to1.6V. With a 0.1µF capacitor, the time to ramp up to maximum duty cycle is approximately 10ms. The external capacitor on the SS pin also sets the compensation for the current control loop and the float voltage control loop. A minimum capacitance of 10nF is required. Trickle Charge And Defective Battery Detection While monitoring the charge cycle, the FC4057 utilizes a charge safety timer to help identifydefective cells and to ensure that the battery is charged safely. Operation is as follow s: At the beginning of a charge cycle, if the battery voltage is low (below 2.65V), the charger goes into trickle charge reducing the charge current to 50mA. If the low battery voltage persists for one quarter of the taper timer charging time, the battery is assumed to be defective, the charge cycle is terminated, the CHRG pin output assumes a high impedance state, and the FAULT pin pulls high. The fault can be cleared by toggling VCC, temporarily forcing the EN pin to high, or temporarily forcing the BAT pin voltage above .9V. If the battery voltage exceeds the trickle charge threshold of 2.9V(typ.) prior to the expiration of the timer, the charge cycle proceeds into fast charge. Two time out periods of 37.5 minutes for Trickle Charge mode and 2.5 hours for Constant Voltage Taper mode. Mode Time Trickle Charge (TC) Time Out 37.5 minutes Constant Voltage (CV) Mode Taper Time Out, IBAT<IIDET 2.5 hours Table 1. Summary for a 0.22 F Ceramic Capacitor Used for the Timer Capacitor from PROG to GNDSENS, but it may also be set with a current output DAC connected to the PROG pin. The voltage on the PROG pin is nominally 1.2V. issues with the RPROG short test when using the maximum charge current setting.

1.13kΩ programs approximately 100mA and 280Ω approximately 400mA. single resistor, R1,can program both (Figure 16). Figure 16. Programming Charge Current and IDET Threshold with a Single Resistor IDET and PROG pins must flow through a single resistor R1 when a single programming resistor is used. where time is the desired taper timer charging time. the time-out periods would be doubled.

The timer starts when an input voltage greater than the undervoltage lockout threshold level is applied and the EN pin is lower than the chip enable threshold voltage level. After a time-out occurs, the charge current stops, and the CHRG output assumes a high impedance state to indicate that the charging has stopped. Connecting the TIMER pin to IDET disables the timer function. Connect this pin to GNDSENS to end battery charging when IBAT drops below the IDET charge rate threshold. Hardware Chip Enable Input (EN) The FC4057 con tains a EN input. Drive EN low to enable charge and enter normal operation. At any point in the charge cycle, the FC4057 can be put into shutdown mode by driving the EN pin high. This reduces the battery drain current to less than 3μA and the supply current to less than 50μA. When in shutdown mode, the CHRG pin is in the high impedance state. Driving EN high during DEFAULT mode resets the safety timer. A new charge cycle can be initiated by driving the EN pin low. A resistor pull-down on this pin forces the FC4057 to be enabled if the pin is allowed to float. Input Voltag e Protection in Charge Mode Undervoltage Lockout Internal undervoltage lockout circuits monitor VIN and keep the charger circuits shut down until VIN rises above the undervoltage lockout threshold. The UVLO has a built-in hysteresis of 200mV. Sleep Mode The FC4057 enters the low-power sleep mode if the voltage on V INSENSE falls below sleep-mode entry threshold, V BATSENS+VSLP, and V INSENSE is higher than the undervoltage lockout threshold, V UVL. This feature prevents reverse current draining from t he battery during the absence of V INSE NSE. W hen VINSENSE< V BATSENS+VSLP, the FC4057 turns off the PWM converter. Once V INSENSE > V BATSENS + V(SLP_EXIT), the device initiates a new c harge cycle . Input Voltage Based DPM During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage will decease. Once the supply drops to VIN_DPM (typically 4.5V), the input current limit is reduced down to prevent further supply droop. When the IC enters this mode, the charge current is lower than the set value . Th is feature ensures IC compatibility with adapters with different current capabilities without a hardware change. Battery Protection in Charge Mode Output Overvoltage Protection The FC4057 provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage goes too high. A comparator turns off both chargers (high rate and trickle) if battery voltage exceeds the float voltage V FLOAT by approximately 5%. This may occur in situations where the battery is accidentally disconnected while battery charging is underway. Once V BATSENSE drops to the battery overvoltage exit threshold, the fault is cleared and charge process ba ck to normal. Battery Short Protection During the normal charging process, if the battery voltage is lower than the short-circuit threshold, V(BATSHRT), the charger operates in linear charge mode with a lower charge rate of I (BATSHRT)= ITRIKL as shown in Figure 2. Short-Circuit Current Protection Short-circuit protection is provided in several different ways. First, a hard short on the battery terminals will cause the charge to enter trickle charge mode, limiting charge current to the trickle charge current (typically 50mA). Se cond, PWM charging is prevented if the high rate charge current is programmed far above the 2A maximum recommended charge current (via the PROG pin). Third, an overcurrent comparator monitors the peak inductor current. APPLICATION INFORMATION(continued) FC4057A420QD16 2020. 06. 12 17/40Revision No : 0

and a new charging cycle resumes . or sink current. Table 2 describes the status of the charge cycle based on the CHRG and FAULT outputs. charging is proceeding normally. out-of-temperature condition. Low 30µA pull down IDET has been reached and charging is proceeding normally. to an NTC out-of-temperature condition. Low High Normal time out (charging has stopped). out-of-temperature condition. Table 2. CHRG and FAULT Status Indicator These status pins can be used to communicate to the host processor or drive LEDs.

Note: Red LED forward voltage (VF) is typically 2.0V@ 2mA. Figure 17. Microprocessor Interface resistor will then pull the pin high to indicate charging has stopped. IDET. In this case, an external device can terminate charging by pulling the EN pin high. 50kHz, alternating between a high and low duty factor at an approximate rate of 1.5Hz (Figure 18).

Figure 18. CHRG Temperature Fault Waveform interrupt line. Serrations within this pulse are typically 500ns wide. cold comparators each have approximately 3°C of hysteresis to prevent oscillation about the trip point. Grounding the NTC pin disables the NTC function. also work (Vishay Dale R-T Curve 2 shows a ratio of RCOLD to RHOT of 2.815/0.4086 = 6 .89). Power conscious designs may want to use thermistors whose room temperature value is greater than 10k. value of RNOM with respect to RNTC. where RHOT is the resistance ratio of RNTC at the desired hot temperature trip point.

trip points a resistor, R1, can be added in series with RNTC (see Figure 19).

0.74 VINSENSE

0.29 VINSENSE

0.02 VINSENSE

Figure 19. Extending the Delta Temperature The final solution is as shown if Figure 19 where RNOM =121k, R1 = 13.3k and RNTC = 100k at 25°C.

When a 1% resistor is used for RNOM, the major error in the 50°C trip point is determined by the tolerance of the NTC thermistor. A typical 10k NTC thermistor has a ±10% tolerance. By looking up the temperature coefficient of the thermistor at 50°C, the tolerance error can be calculated in degrees centigrade.Consider the Vishay NTHS0603N02N1002J thermistor which has a temperature coefficient of –3.3%/°C at 50°C. Dividing the tolerance by the temperature coefficient, ±10 % /(3.3%/°C) = ±3°C, gives the temperature error of the hot trip point. The cold trip point is a little more complicated because its error depends on the tolerance of the NTC thermistor and the degree to which the ratio of its value at 0°C and its value at 50°C varies from 7 to 1. Therefore, the cold trip point error can be calculated using the tolerance, TOL, the temperature coefficient of the thermistor at 0°C, TC (in %/°C), the value of the thermistor at 0°C, RCOLD, and the value of the the rmistor at 50°C, RHOT. The formula is: Temperature Error(℃)= ( 1+TOL 7 •RCOLD RHOT −1 •100 TC For example, the Vishay NTHS0603N02N1002J thermistor with a tolerance of ±10%, TC of –4.5%/°C, and RCOLD/RHOT of 6.89, has a cold trip point error of: Temperature Error(℃)= (1±0.10 7 •6.89 −1) •100 -4.5 = −1.8℃, +2.5℃ If a thermistor with a tolerance less than ±10% is used, the trip point errors begin to depend on errors other than thermistor tolerance including the input offset voltage of the internal comparators of the FC4057 and the effects of internal voltage drops due to high charging currents. Selecting Input Bypass Capacitor The FC4057 uses a synchronous buck regulator to provide high battery charging current. In most applications, all that is needed is a bypass capacitor, typically a 10 µF capacitor placed in close proximity to PV IN and PGND pins, works well. The FC4057 is designed to work with both regulated and unregulated e xternal dc supplies. If a non-regulated supply is chosen, the supply unit should have enough capacitance to hold up the supply voltage to the minimum required input voltage at maximum load. If not, more capacitance has to be added to the input of the charger. A 10µF chip ceramic capacitor is recommended for the input bypass capacitor, because it provides low ESR and ESL and can handle the high RMS ripple currents. However, some high Q capacitors may produce high transients due to self-resonance under some start-up conditions, such as connecting the charger inpu t to a hot power source. Adding a 1.5 Ω resistor in series with an X5R ceramic capacitor wi ll minimize start-up voltage transients. Protecting the PVIN Pin from Overvoltage Transients Many types of capacitors can be used for input bypassing, however, caution must be exercised when using multilayer ceramic capacitors to bypass the PV IN pin, which powered by USB bus or Wall Adapter Input. High voltage transients can be generated under some start-up conditions, depending on the power supply characteristics and cable length, such as when the USB or wall adapter is hot plugged. When power is supplied via the USB bus or wall adapter, the cable inductance along with the self resonant and high Q characteristics of some types of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage pin ratings and damage the FC4057 The long cable lengths of most wall adapters and USB cables makes them especially susceptible to this problem. To bypass the PVIN pin, add a 1Ω resistor in series with an X5R ceramic capacitor to lower the effective Q of the network and greatly reduce the ringin g. A tantalum, OS-CON, or electrolytic capacitor can be used in place of the ceramic and resistor, as their higher ESR reduces the Q, thus reducing the voltage ringing. The oscilloscope photograph in Figure 20 shows how serious the overvoltage transient can be for the USB and wall adapter inputs. For both traces, a 5V supply is hot-plugged using a three foot long cable. For the top trace, only a 4.7µF capacitor (without the recommended 1Ω series resistor) is used to locally APPLICATION INFORMATION(continued) FC4057A420QD16 2020. 06. 12 22/40Revision No : 0

Figure 20. Waveforms Resulting from Hot-Plugging a 5V Input Supply adapter hot-plug events to ensure that overvoltage transients have been adequately removed. 200μFof local capacitance. The capacitance on the BAT rail can be higher if distributed amongst the rail. local bypass to BAT. A 47μF bypass capacitor is recommended for optimal transient response. impedance is raised to 2Ω with a bead or inductor, only 5% of the ripple current will flow in the battery. Similar techniques may also be applied to minimize EMI from the input leads. When selecting an inductor, several attributes must be examined to find the right part for the application.

chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some efficiency gain is reached using the 2.2μH inductor, however, due to the physical size of the inductor, this may not be a viable option. The 1.5μH inductor provides a good tradeoff between size and efficiency. A good choice is the IHLP-2525AH-01from Vishay Dale. To calculate the inductor ripple current: ΔIL = VBA T L •fOSC

• (1 −VBA T VIN ) = VBA T− VBAT VIN L •fOSC where VBAT is the battery voltage, VIN is the input voltage, L is the inductance and f is the PWM oscillator frequency (typically 1.5MHz). Maximum inductor ripple current occurs at maximum VIN and VBAT = VIN/2. Peak inductor current will be: IPK = IBAT + 0.5 •∆IL where IBAT is the maximum battery charging current. When sizing the inductor make sure that the peak current will not exceed the saturation current of the inductors. Also, ΔIL should never exceed 0.4(IBAT) as this may interfere with proper operation of the output short-circuit p rotection comparator . 1.5μH provides reasonable inductor ripple current in a typical application. With 1.5μH and 2A charge current: ΔIL = 2.85V − (2.85V)2 VIN 1.5µH •1.5MHz = 0.61AP−P and IPK = 2.31A Due to the high currents possible with the FC4057 a thermal analysis must also be done for the inductor. Many inductors have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty cycle of the load transients. For example, if the application requires a 2A DC load with peaks at 2.31A 20% of the time, a Δ40°C temperature rise current must be greater than 2.62A: ITEMPRISE=IBAT+D•( IPK - IBAT)=2A+0.2•(2.31-2A)=2.62A Remote Sensing-Kelvin Sensing the Battery The internal P-channel MOSF ET drain is connected to the BAT pin, while the BATSENS pin connects through an internal precision resistor divider to the input of the constant-voltage amplifier. This architecture allows the BATSENS pin to Kelvin sense the positive battery terminal. This is especially useful when the copper trace from the BAT pin to the Li-Ion battery is long and has a high resistance. High charge currents can cause a significant volt age d rop between the positive battery terminal and the BAT pin. In this situation, a separate trace from the BATSENS pin to the battery terminals will eliminate this voltage error and result in more accurate battery voltage sensing. The BATSENS pin MU ST be electrically connected to the BAT pin. For highest float voltage accuracy, tie G NDSENS and BATSENS directly to the battery terminals. In a similar fashion, tie B AT and PGND directly to the battery terminals. This eliminates IR dro ps in the GNDSENS and BATSENS lines by preventing charge current from flowing in them. USB Charge Reduction In many instances, product system designers do not know the real properties of a potential port to be used to supply power to the battery charger. Typical powered USB ports commonly found on desktop and notebook PCs should supply up to 500mA(USB2.0) or 900mA(USB3.0). In the event a port being used to supply the charger is unable to provide the programmed fast charge current, or if the sy stem under charge must also share supply current with other fun ctions, the FC4057 will automatically reduce USB fast charge current to maintain port integrity and protect the host system. The input voltage based DPM system becomes active when the voltage on the input falls below the input voltage DPM regulation threshold (VIN_DPM), which is typically 4.5V. The input voltage based DPM system will reduce the fast charge current level in a linear fashion until the voltage sensed on the i nput recovers above the charge reduction threshold voltage. APPLICATION INFORMATION(continued) FC4057A420QD16 2020. 06. 12 24/40Revision No : 0

Figure 22. Charging Characteristic the soft-start cycle causing a corresponding increase in wall adap ter load current. the VIN jumps back up to VADAPTER. voltage drop in the FC4057 is very low when charge current is highest, power dissipation is also very low. where IIN is VIN current consumed by the IC.

IBAT = Charge current at Constant-Current Mode (Fast) Charge & Constant-Voltage Mode (Taper) Charge ηS = Synchronous Buck Converter efficiency PL_winding = winding loss of the output inductor, it normally can be estimated as: PL_win ding = ≈IL_RM S 2 •RL_DCR Where: IL_RMS= RMS ripple current of the output inductor, calculated as IL_RMS = ²IBAT 2 + 1 12 ΔIL RL_DCR= DCR of the output inductor, which is temperature-dependent. It normally can be estimated as: RL_DCR(T) = RL_DCR(25°C) •(1+K•ΔT) where K is the temperature coefficient and K ≈ 0.0039/°C. So the IC power dissipation in switching mode, PDS can be calculated from the following equations PDS = ( VBAT •IBAT ηS −VBA T •IBAT ) − IL_RMS 2 •RL_DC R (T) PDS = ( VBA T •IBA T ηS −VBA T •IBAT ) − ( ²IBAT 2 + 1 12 ΔIL 2 )

• RL_DC R(25°C) •(1 + K •ΔT) PDS = ( VBA T •IBA T ηS −VBAT •IBAT ) − (IBA T 2 + 1 12 ΔIL 2) •RL_DCR (25°C) •(1 + K •ΔT) PDS = ( VBA T •IBAT ηS −VBA T •IBA T) −{ IBA T 2 + 1 12 •[ VBA T L •fOSC
• (1 −VBA T VIN } R L_DC R(25°C) •(1 + K •ΔT) Due to the charge profile of Li-Ion batteries the maximum power dissipation is typica lly seen at the beginning of the charge cycle when the battery voltage is at VTRIKL. See the charging profile, Figure 3. Power dissipation in buck battery charger mode may be estimated from the dissipation curves given in the Typical Performance Characteristics section of the data sheet. This will slightly overestimate chip power dissipation, because it assumes all loss, including loss from external components, occurs within the chip. FC4057 power dissipation is very low if a current limited wall adapter is used and allowed to enter current limit. Insert the highest power dissipation figure into the following equation to determine maximum junction temperature: TJ= TA + (PD •40°C/W) The FC4057 includes chip overtemperature protection. If junction temperature exceeds 160°C (typical), the chip will stop battery charging until chip temperature drops below 140°C. Thermal Considerations The thermal path for the heat generated by the IC is from the die to the copper lead frame, through t he package leads (especially the ground lead) and the Exposed Thermal Die Pad to th e PC board copper. The PC board copper is the heat sink. The FC4057 is housed in a thermally-enhancedExposed Thermal Die Pad package that has an exposed metal pad on the backside of the package. The most common measure of package thermal performance is thermal impedance ( θJA ) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mat hematical expression for θJA is: θJA=(TJ – TA) /PD Where: APPLICATION INFORMATION(continued) FC4057A420QD16 2020. 06. 12 27/40Revision No : 0

Figure 24. Recommended Land Pattern for 16-Pin QFN4x4 Exposed Thermal Die Pad plane available, and the Exposed Thermal Die Pad should be connected to the largest area available. and dissipate the heat to the surrounding ambient.

Figure 27. Battery Isolation and Power Path Bypass, Powering the Load Directly closing the battery isolation switch and connecting the battery to the load. the use of an optional Schottky diode in parallel with QISO, as shown.

Figure 29. QISO is On When the Gate is Low and Current Flows from the Battery Cell A diode, D BYPASS in Figure 29 is required to prevent reverse current from flowing to the power source. source to the system load. A schottky diode, which has lower forward voltage drop, is recommended. MOSFET is used for demonstration in this section. to high rate (PWM) charge mode but initially delivers zero current (because the soft-start pin is at zero). and V BAT rapidly rises until the f loat voltage is reached.

series with the soft-start capacitor. Figure 30. Battery-Less Start-Up

reduce power dissipation in the charging circuit while charging at high current. Specification compliant Dedicated Charger, rega rdless of its current limit. capacitor in a smaller 0805 case. from building up in the cable too fast thus dampening out any resonant overshoot. Figure 33. USB Soft Connect Circuit

ssipation. The other paths contain only DC and/or 1.5MHz tri-wave ripplecurrent and are less critical. components that return to ground should be connected to GNDSENS. in the return path which reduce the regulated battery voltage.

1 PACK+

Figure 34. Lithium-Ion Cell Connections The circled location 1 in Figure 34 indicates the Kelvin connection of the most positive battery node. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. PGND pins as possible to minimize the ground difference between the input and VINSENSE. parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.

5.The local output bypass capacitor from BAT to PGND should be connected between the BAT pin and PGND of the IC. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. 6.Minimize the amount of inductance between BAT and the postive connection of the battery terminal. If a large parasitic board inductance on BAT is expected, increase the bypass capacitance on BAT. 7.Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths. 8.The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-si gn al components). It is also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue, and having the components segregated minimizes coupling between signals. 9.The high-cu rrent charge paths into PV IN, BAT, SENSE and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pin is power ground connection for high-current power converter node. Internally, PGND is connect ed to the source of the internal n-channel low-side FET. On PCB layout, connected directly to ground connection of input and output capacitors of the charger and should be connected to the ground plane to return curren t through the internal low-side FET. 10.GNDSENS provides a Kelvin connection for PGND and must be connected to PGND schematically. 11.Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground. 12.Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 13.It is critical that the exposed power pad on the backside of the IC package must be soldered to the PCB ground plane for proper power dissipation and should be connected to as much copper in the PCB as possible. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. This allows better thermal performance as the board pulls heat away from the IC. 14.The via s ize and number should be enough for a given current path. 15. The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery pack. It is important that the NTC thermistor not be in close thermal contact with the FC4057 Furthermore, it is essential that the PV IN connection to R NOM is made according to standard Kelvin sense techniques. Since PV IN is a high current path into the FC4057 it is essential to minimize voltage drops between the PVIN input pin and the top of RNOM. 16.The constant current provided to ch arge the timer capacitor is very small, and the TIMER pin is susceptible to noise and changes in capacitance value. Therefore, the timer capacitor should be physically located on the printed circuit board layout as close as possible to the TIMER pin. Figure35. High Frequency Current Path APPLICATION INFORMATION(continued) FC4057A420QD16 2020. 06. 12 38/40Revision No : 0

For a list of recommend component manufacturers, contact the Chipower application department. Figure 36. 2A Li-Ion Battery Charger with 2.5Hr Timer, Temperature

QFN4×4-16 PACKAGING INFORMATION Dimensions In Millimeters Symbol Min NOM Max A 0.70 0.75 0.80 A1 0.0 0.02 0.05 A3 0.20REF b 0.25 0.30 0.35 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 2.20 2.30 2.40 E2 2.20 2.30 2.40 e 0.55 0.65 0.75 K 0.20 - - L 0.50 0.55 0.60 R 0.09 - - FC4057A420QD16 2020. 06. 12 40/40Revision No : 0