FBL2031

FBL2031 PHILIPS | Alldatasheet

Document overview

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 FBL2031 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver Product specification Supersedes data of 1998 Sep 04

2000 Apr 18

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

22000 Apr 18 853-2118 23499

FEATURES

• Latched, registered or straight through in either A to B or B to A path
• Drives heavily loaded backplanes with equivalent load impedances down to 10Ω .
• High drive 100mA BTL open collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces power consumption
• Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Each BTL driver has a dedicated Bus GND for a signal return
• Controlled output ramp and multiple GND pins minimize ground bounce
• Glitch-free power up/power down operation
• Low ICC current
• Tight output skew
• Supports live insertion
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
• 5V compatible I/O on A-port

DESCRIPTION

The FBL2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FBL2031 is intended to provide the electrical interface to a high performance wired-OR bus. QUICK REFERENCE DATA SYMBOL PARAMETER TYPICAL UNIT tPLH tPHL Propagation delay An to Bn 2.7 ns tPLH tPHL Propagation delay Bn to An 4.4 4.2 ns C O Output capacitance (B0 – Bn only) 6 pF IOL Output current (B0 – Bn only) 100 mA AIn to Bn (outputs Low or High) 11 ICC Supply current Bn to AOn (outputs Low) 22 mA Bn to AOn (outputs High) 18

ORDERING INFORMATION

PACKAGE VCC = 3.3V±10%; Tamb = –40°C to +85°C DWG No. 52-pin Plastic Quad Flat Pack (PQFP) FBL2031BB SOT379-1

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 3

52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 BUS GND BUS GND BUS GND BUS GND BUS GND BUS GND BUS GND LOGIC GND LOGIC GND LOGIC GND BG GND BG VCC OEA BIAS V VCC VCC 9-Bit latched/registered transceiver FBL2031 52-lead PQFP LOGIC GND BUS GND SEL0 OEB0 OEB1 TCK (option) TMS (option) BUS GND VCC TDO (option) TDI (option) SEL1 LCBA LCAB LOGIC GND LOGIC GND LOGIC GND LOGIC GND SG00087 PIN DESCRIPTION SYMBOL PIN NUMBER TYPE NAME AND FUNCTION A0 – A8 50, 52, 2, 4, 6, 8, 10, 12, 14I/O BiCMOS data inputs/3-State outputs (TTL) B0 – B8 40, 38, 36, 34, 32, 30, 28, 26, 24 I/O Data inputs/Open Collector outputs, High current drive (BTL) OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low OEA 47 Input Enables the A outputs when High BUS GND 25, 27, 29, 31, 33, 35, 37, 39, 41 GND Bus ground (0V) LOGIC GND 51, 1, 3, 5, 7, 9, 11, 13 GND Logic ground (0V) VCC 23, 43, 49 Power Positive supply voltage BIAS V 48 Power Live insertion pre-bias pin BG V CC 17 Power Band Gap threshold voltage reference BG GND 19 GND Band Gap threshold voltage reference ground SEL0 20 Input Mode select SEL1 15 Input Mode select LCAB 18 Input A to B clock/latch enable (transparent latch when Low) LCBA 16 Input B to A clock/latch enable (transparent latch when Low) TMS 42 Input Test Mode Select (optional, if not implemented then no connect) TCK 44 Input Test Clock (optional, if not implemented then no connect) TDI 22 Input Test Data In (optional, if not implemented then no connect) TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 4

The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A “00” configures latches in both directions. A “10” configures thru mode in both directions. A “01” configures register mode in both directions. A “11” configures register mode in the A-to-B direction and latch mode in the B-to-A direction. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1 . Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The “V OH ” clamp reduces inductive ringing effects during a Low-to-High transition. The “VOH ” clamp is always active. The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while V CC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a V CC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature. PACKAGE THERMAL CHARACTERISTICS PARAMETER CONDITION 52-PIN PLASTIC QFP θja Still air 80°C/W θja 300 Linear feet per minute air flow 58°C/W θjc Thermally mounted on one side to heat sink 20°C/W

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 5

An Bn * OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An Bn An to Bnthru mode L — H L L X X H L input H An to Bn thru mode H — H L L X X H L input L An to Bntransparent latch L — H L L L X L L input H An to Bn transparent latch H — H L L L X L L input L An to Bnlatch and read l — H L L ↑ X L L input H An to Bn latch and read h — H L L ↑ X L L input L Bn outputs latched and read (preconditioned latch) X — H L X H X L L X latched data An to Bnregister l — H L L ↑ X X H input H An to Bn register h — H L L ↑ X X H input L Bn to An thru mode — L Disable H X X H L H input Bn to An thru mode — H Disable H X X H L L input — L Disable H X L L L H input Bn to An transparent latch — H Disable H X L L L L input Bn to An transparent latch — L Disable H X L H H H input — H Disable H X L H H L input — l Disable H X ↑ L L H input Bn to An latch and read — h Disable H X ↑ L L L input Bn to An latch and read — l Disable H X ↑ H H H input — h Disable H X ↑ H H L input An outputs latched and read — X X X H X H L L latched data X (preconditioned latch) — X X X H X H H H latched data X Bn to An register — l Disable H X ↑ L H H input Bn to An register — h Disable H X ↑ L H L input Disable Bnoutputs X X L X X X X X X X H Disable Bn outputs X X X H X X X X X X H Disable An outputs X X X X L X X X X Z X FUNCTION SELECT TABLE MODE SELECTED SEL0 SEL1 Thru mode H L Register mode (An to Bn) X H Latch mode (An to Bn) L L Register mode (Bn to An) L H Latch mode (Bn to An) L L Latch mode (Bn to An) H H NOTES: H = High voltage level L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High LCXX transition h = High voltage level one set-up time prior to the Low-to-High LCXX transition X = Don’t care Z = High-impedance (OFF) state — = Input not externally driven ↑ = Low-to-High transition H** = Goes to level of pull-up voltage Bn * = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Disable = OEB0 is Low or OEB1 is High.

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 6

(JTAG Boundary Scan pins) LOGIC GND = 1, 3, 5, 7, 9, 11, 13, 51 BUS GND = 25, 27, 29, 31, 33, 35, 37, 39, 41 BIAS V = 48 V CC = 23, 43, 49 BG V CC =1 7 BG GND = 19 DQ E MUX A ⇒ B QD MUX A ⇒ B 26 B7 12A7 MUX A ⇐ B TTL MUX A ⇒ B MUX A ⇐ B MUX A ⇒ B MUX A ⇐ B DQ Clk DQ E DQ Clk DQ E DQ Clk DQ E DQ Clk DQ E DQ E DQ E DQ Clk DQ Clk DQ E 15SEL1 16LCBA DQ Clk MUX A ⇐ B SG00061

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 7

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +4.6 V V Input voltage AI0 – AI6, OEB0, OEBn, OEAn –0.5 to +7.0 V VIN Input voltage B0 – B8 –0.5 to +3.5 IIN Input current VIN /C0116 0 –50 VOUT Voltage applied to output in High output state –0.5 to +7.0 V IO Current applied to output in AO0 – AO8 64, –64 mA IOUT Low output state/High output state B0 – B8 200 TSTG Storage temperature –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER COMMERCIAL LIMITS VCC = 3.3V±10%; Tamb = –40 to +85°C UNIT MIN TYP MAX VCC Supply voltage 3.0 3.3 3.6 V V High level input voltage Except B0–B8 2.0 V VIH High-level input voltage B0 – B8 1.62 1.55 V Low level input voltage Except B0–B8 0.8 V VIL Low-level input voltage B0 – B8 1.47 IIK Input clamp current –18 mA IOH High-level output current AO0 – AO8 –32 mA IO Low level output current AO0 – AO8 +32 mA IOL Low-level output current B0 – B8 100 C OB Output capacitance on B port 6 7 pF Tamb Operating free-air temperature range 0 +70 °C LIVE INSERTION SPECIFICATIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN TYP MAX UNIT VBIASV Bias pin voltage Voltage difference between the Bias voltage and VCC after the PCB is plugged in. – – 0.5 V I S Bias pin (IBIASV) input VCC = 0 V, Bias V = 3.6V 1.2 mA IBIASV (BIASV ) DC current VCC = 3.3V, Bias V = 3.6V 10 µA VBn Bus voltage during prebias B0 – B8 = 0V, Bias V = 3.3V 1.62 2.1 V ILM Fall current during prebiasB0 – B8 = 2V, Bias V = 1.3 to 2.5V 1 µA IHM Rise current during prebiasB0 – B8 = 1V, Bias V = 3 to 3.6V –1 µA IBnPEAK Peak bus current during insertion VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V, Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns 10 mA IO OFF Power up current VCC = 0 to 3.3V, OEB0 = 0.8V 100 µAIOL OFF Pow er up current VCC = 0 to 1.2V, OEB0 = 0 to 5V 100 µA tGR Input glitch rejection VCC = 3.3V 1.0 1.35 ns

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 8

DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT IOH High level output currentB0 – B8 VCC = MAX, VIL = MAX, VOH = 1.9V 100 µA IO Power off output currentB0 B8 VCC = 0V, VIL = MAX, VOH = 1.9V 100 µAIOFF Pow er-off output current B0 – B8 VCC = 0V, VIL = MAX, VOH = 1.9V @ 85°C 300 µA Hi h l l t t 3 VCC = MIN to MAX VCC –0.2 V VOH High-level output voltage AO0 – AO83 VCC = MIN; IOH = -8mA 2.4 Vvoltage VCC = MIN; IOH = -32mA 2.0 V AO0 AO8 3 VCC = MIN; IOL = 16mA 0.4 V VO Low level output voltage AO0 – AO8 3 VCC = MIN; IOL = 32mA 0.5 V VOL Low-level output voltage B0 – B8 VCC = MIN, IOL = 4mA 0.5 V VCC = MIN, IOL = 100mA 0.75 1.0 1.20 V VIK Input clamp voltage VCC = MIN, II = IIK = –18mA –0.85 –1.2 V Control pins VCC = 3.6V; VI = VCC or GND ±1.0 II Input leakage current Control/ AI0 – AI8 VCC = 0V or 3.6V; VI = 5.5V 10 µAI g AI0 – AI8 VCC = 3.6V; VI = VCC 1 µ Note 4 VCC = 3.6V; VI = 0V –5 VCC = MAX, VI = 1.9V 100 µA IIH High-level input currentB0 – B8 VCC = MAX, VI = 3.5V, note 5 100 mA VCC = MAX, VI = 3.75V @ –40°C 100 mA IIL Low-level input currentB0 – B8 VCC = MAX, VI = 0.75V –100 µA IOZH Off-state output currentAO0 – AO8 VCC = MAX, VO =3V 5 µA IOZL Off-state output currentAO0 – AO8 VCC = MAX, VO = 0.5V –5 µA ICCH B to A VCC = MAX, outputs High 18 32 mA ICCL B to A VCC = MAX, outputs Low 22 37 mA ICC Supply current (total)ICCH A to B VCC = MAX, outputs High 11 16 mA ICCL A to B VCC = MAX, outputs Low 11 16 mA ICCZ VCC = MAX 18 32 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 3.3V, TA = 25°C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Unused pins are at VCC or GND. 5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit is active). This is not a tested condition.

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 9

AC ELECTRICAL CHARACTERISTICS B TO A SPECIFICATIONS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 3.3V, Tamb = –40 to +85°C, VCC = 3.3V±10%, UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency Waveform 4 120 150 MHz tPLH tPHL Propagation delay (thru mode) Bn to An Waveform 1, 2 2.8 3.0 4.3 4.5 5.9 6.0 2.2 2.6 6.8 7.3 ns tPLH tPHL Propagation delay (transparent latch) Bn to An Waveform 1, 2 2.8 3.4 4.9 5.0 7.0 6.6 1.8 2.8 8.4 7.8 ns tPLH tPHL Propagation delay LCBA to An (latch) Waveform 1, 2 7.7 7.5 10.2 10.1 13.0 12.9 6.1 6.1 15.6 15.4 ns tPLH tPHL Propagation delay LCBA to An (register) Waveform 1, 2 2.7 3.0 4.2 4.5 5.7 6.1 2.1 2.4 6.7 6.9 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An (inverting) Waveform 1, 2 2.9 1.9 5.8 5.8 9.1 10.4 2.2 1.2 10.5 11.6 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An (non-inverting) Waveform 1, 2 2.0 2.8 5.9 5.6 10.3 8.8 1.4 2.2 12.3 10.0 ns tPZH tPHZ Output enable time from High or Low OEA to An Waveform 5, 6 3.0 4.0 4.4 5.6 5.7 7.3 2.6 3.2 6.6 8.3 ns tPZL tPLZ Output disable time to High or Low OEA to An Waveform 5, 6 2.6 1.4 4.0 2.6 5.4 3.7 2.1 1.0 6.0 4.4 ns tTLH tTHL Output transition time, An Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 0.2 0.1 2.0 1.2 ns tSK (o) Output to output skew for multiple channels 1 Waveform 3 0.5 1.0 1.5 ns tSK (p) Pulse skew2  tPHL – tPLH  MAX Waveform 2 0.5 1.0 1.5 ns NOTES: 1.  tPN actual – tPM actual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC , loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 10

AC ELECTRICAL CHARACTERISTICS A TO B 9 Ω LOAD SPECIFICATIONS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 3.3V, Tamb = –40 to +85°C, VCC = 3.3V±10%, UNIT MIN TYP MAX MIN MAX tPLH tPHL Propagation delay (thru latch) An to Bn Waveform 1, 2 1.4 1.3 2.6 2.5 3.8 3.8 1.0 1.0 4.9 4.2 ns tPLH tPHL Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.7 2.0 2.9 3.5 4.2 5.0 1.0 1.5 5.4 5.7 ns tPLH tPHL Propagation delay LCAB to Bn (latch) Waveform 1, 2 8.8 8.4 11.6 11.0 14.5 13.7 6.7 6.7 17.9 16.6 ns tPLH tPHL Propagation delay LCAB to Bn (register) Waveform 1, 2 2.3 2.5 3.6 4.0 5.0 5.4 1.4 1.9 6.2 6.4 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (inverting) Waveform 1, 2 2.3 1.3 3.8 4.8 5.5 8.8 1.2 1.0 7.0 9.6 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (non-inverting) Waveform 1, 2 2.0 2.6 4.4 4.3 7.2 6.1 1.1 1.7 8.5 7.6 ns tPLH tPHL OEBn to Bn Waveform 1, 2 1.2 1.9 2.9 3.3 4.8 4.7 1.0 1.2 5.8 6.4 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.2 0.4 3.0 1.5 ns tSK (o) Output to output skew for multiple channels 1 Waveform 3 0.4 1.0 2.0 ns tSK (p) Pulse skew2  tPHL – tPLH  MAX Waveform 2 0.3 1.0 1.5 ns NOTES: 1.  tPN actual – tPM actual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC , loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 11

AC ELECTRICAL CHARACTERISTICS A TO B 16.5 Ω LOAD SPECIFICATIONS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 3.3V, Tamb = –40 to +85°C, VCC = 3.3V±10%, UNIT MIN TYP MAX MIN MAX tPLH tPHL Propagation delay (thru latch) An to Bn Waveform 1, 2 1.4 1.2 2.7 2.4 3.9 3.6 1.0 1.0 5.0 4.0 ns tPLH tPHL Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.8 2.0 3.0 3.2 4.2 4.7 1.0 1.4 5.6 5.5 ns tPLH tPHL Propagation delay LCAB to Bn (latch) Waveform 1, 2 8.6 8.0 11.4 10.6 14.2 13.3 6.5 6.4 17.5 16.1 ns tPLH tPHL Propagation delay LCAB to Bn (register) Waveform 1, 2 2.2 2.3 3.5 3.7 4.8 5.1 1.2 1.7 6.1 5.9 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (inverting) Waveform 1, 2 2.6 1.4 4.5 4.4 6.7 7.7 1.5 1.1 8.1 8.4 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (non-inverting) Waveform 1, 2 2.2 2.3 4.5 4.0 6.9 5.8 1.4 1.5 8.2 6.9 ns tPLH tPHL OEB0 to Bn Waveform 1, 2 1.8 1.7 3.1 2.9 4.4 4.2 1.0 1.0 5.8 6.0 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.2 0.4 3.0 1.5 ns tSK (o) Output to output skew for multiple channels 1 Waveform 3 0.5 1.0 2.0 ns tSK (p) Pulse skew2  tPHL – tPLH  MAX Waveform 2 0.5 1.0 1.5 ns NOTES: 1.  tPN actual – tPM actual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC , loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 12

AC SETUP REQUIREMENTS (Commercial) LIMITS SYMBOL PARAMETER TEST Tamb = +25°C, VCC = 3.3V, Tamb = –40 to +85°C, VCC = 3.3V±10%, UNITSYMBOL PARAMETER CONDITION C L = 50pF (A side) / CD = 30pF (B side) R L = 500Ω (A side) / RU = 16.5Ω (B side) UNIT MIN TYP MIN ts(H) ts(L) Setup time An to LCAB Waveform 4 1.3 1.3 1.5 1.5 ns th(H) th(L) Hold time An to LCAB Waveform 4 1.0 1.0 1.0 1.0 ns ts(H) ts(L) Setup time Bn to LCBA Waveform 4 5.0 4.0 6.0 4.5 ns th(H) th(L) Hold time Bn to LCBA Waveform 4 0.0 0.0 0.0 0.0 ns tw (H) tw (L) Pulse width, High or Low LCAB or LCBA Waveform 4 3.0 3.0 3.0 3.0 ns AC WAVEFORMS ÍÍ ÍÍ VM ts tPZL Input Output VMVM VMVM tPLH tPHL VMVM VM VM tPHL tPLH Output An, Bn An, Bn VM VM tSK (o) An OEA VMVM tPLZ VM VOL +0.3V An OEA VM VM VM VOH -0.3V OV tPHZtPZH NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. Input ÍÍ ÍÍ ÍÍÍÍ ÍÍÍÍ An, Bn LCAB, LCBA VM VM 1/fMAX th ts th tw (L) tw (H) The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Propagation Delay for Data or Output Enable to Output Waveform 2. Propagation Delay for Data or Output Enable to Output Waveform 3. Output to Output Skew Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level tw (input) tw (output) SG00062

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 13

TEST CIRCUIT AND WAVEFORMS 2.5ns 2.0ns500ns 500ns INPUT PULSE REQUIREMENTS Rep. RateAmplitude tTLH tTHL 1MHz3.0V 2.5ns Input Pulse Definitions VM = 1.55V for Bn, VM = 1.5V for all others. VCC Family FB+ D.U.T.PULSE GENERATOR 7.0V R L R LC LR T VIN VOUT Test Circuit for 3-State Outputs on A Port TEST SWITCH SWITCH POSITION tPLZ, tPZL All other closed open DEFINITIONS: R L = Load Resistor; see AC CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. C D = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R U = Pull up resistor; see AC CHARACTERISTICS for value. tW 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE AMP (V) LOW V LOW V tTHL (tf) tTLH (tr) tW tWLow V 0.0V tTLH (tr) tTHL (tf) AMP (V) A Port 1MHz2.0V 2.0ns1.0VB Port VCC D.U.T.PULSE GENERATOR R U C DR T VIN VOUT Test Circuit for Outputs on B Port BIAS V 2.0V (for RU = 9 Ω ) 2.1V (for RU = 16.5 Ω ) SG00063

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 14

QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 15

Philips Semiconductors Product specification FBL20319-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

2000 Apr 18 16

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 04-00 Document order number: 9397 750 07089 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.