SN74FB2033K TI | Alldatasheet
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8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Compatible With IEEE Std 1194.1-1991 (BTL) /C0068 TTL A Port, Backplane Transceiver Logic (BTL) B Port /C0068 Open-Collector B-Port Outputs Sink 100 mA /C0068 BIAS VCC Pin Minimizes Signal Distortion During Live Insertion/Withdrawal /C0068 High-Impedance State During Power Up and Power Down /C0068 B -Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage /C0068 TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination AI2 AO1 AI1 CLKAB/LEAB IMODE1 IMODE0 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 AI8 AO8 GND CLKBA/LEBA OMODE0 OMODE1 OEB GND AO7 BG GND V GND CC VCC RC PACKAGE (TOP VIEW)VCC OEA CC OEB CCBG V GND AO2 AI3 AO3 AI4 AO4 LOOPBACK AI5 AO5 AI6 AO6 AI7 GND GND GND GND GND GND GND GND BIAS V
description
The SN74FB2033K is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port. The common I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels. The SN74FB2033K is specifically designed to be compatible with IEEE Std 1194.1-1991. The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock inputs serve as active-high transparent latch enables. Copyright 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
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description (continued) Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the output of the selected A-to-B logic element (before inversion) is the B-to-A input. The AO port-enable/-disable control is provided by OEA. When OEA is low or when VCC is less than 2.5 V, the AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels). The B port is controlled by OEB and OEB. If OEB is low, or OEB is high, or when VCC is less than 2.5 V, the B port is inactive. If OEB is high and OEB is low, the B port is active. BG V CC and BG GND are the bias-generator reference inputs. The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated outputs are in the high-impedance (AO port) or inactive (B port) states. Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing effects on VOH during a low-to-high transition. The other clamps out ringing below the BTL VOL voltage of 0.75 V. Both of these clamps are active only during ac switching and do not affect the BTL outputs during steady-state conditions. BIAS V CC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C QFP – RC Tube SN74FB2033KRC FB2033K † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables FUNCTION INPUTS FUNCTION/MODE OEA OEB OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK FUNCTION/MODE L L X X X X X X Isolation L XH X X X X X Isolation X H L L L X X X AI to B, buffer mode X H L L H X X X AI to B, flip-flop mode X H L H X X X X AI to B, latch mode H L X X X L L L B tA O b f f dH XH X X L L L B to AO , buffer mode H L X X X L H L B t AO fli fl dH XH X X L H L B to AO , flip-flop mode H L X X X H X L B tA O l t h dH XH X X H X L B to AO , latch mode H L X X X L L H AI to AO buffer mode H XH X X L L H AI to AO , buffer mode H L X X X L H H AI to AO flip flop mode H XH X X L H H AI to AO , flip-flop mode H L X X X H X H AI to AO latch mode H XH X X H X H AI to AO , latch mode H H L X X X X L AI to B, B to AO ENABLE/DISABLE INPUTS OUTPUTS OEA OEB OEB AO B L X X Hi Z H X X Active X LL Inactive (H) X LH Inactive (H) X HL Active X H H Inactive (H) BUFFER INPUT OUTPUT L H H L LATCH INPUTS OUTPUT CLK/LE DATA OUTPUT H L H H HL L X Q 0
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
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Function Tables (Continued) LOOPBACK LOOPBACK Q † L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram). SELECT INPUTS SELECTED-LOGIC MODE1 MODE0 ELEMENT L L Buffer L H Flip-flop H X Latch FLIP-FLOP INPUTS OUTPUT CLK/LE DATA OUTPUT L X Q 0 ↑ LH ↑ H L
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram CLKBA/LEBA OEB OEB OMODE1 OMODE0 CLKAB/LEAB AI1 IMODE1 IMODE0 AO1 OEA LOOPBACK One of Eight Channels Transceiver P Q
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) MIN NOM MAX UNIT VCC , BG VCC Supply voltage 4.75 5 5.25 V BIAS VCC Supply voltage 4.5 5 5.5 V VIH High level input voltage B port 1.62 2.3 VVIH High-level input voltage Except B port 2 V VIL Low level input voltage B port 0.75 1.47 VVIL Low -level input voltage Except B port 0.8 V IOH High-level output current AO port –3 mA IOL Low level output current AO port 24 mAIOL Low -level output current B port 100 mA ∆t/∆v Input transition rise or fall rate Except B port 10 ns/V TA Operating free-air temperature 0 70 °C NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: A and control inputs to VCC (5 V) or GND, and B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK B port VCC = 4.75 V, II = –18 mA –1.2 VVIK Except B port VCC = 4.75 V, II = –40 mA –0.5 V VCC = 4.75 V to 5.25 V,IOH = –10 µA VCC –1.1 VOH AO port VCC = 4 75 V IOH = –3 mA 2.5 2.85 3.4 V VCC = 4.75 V IOH = –32 mA 2 AO port VCC = 4 75 V IOL = 20 mA 0.33 0.5 VOL AO port VCC = 4.75 V IOL = 55 mA 0.8 VVOL B t VCC = 4 75 V IOL = 100 mA 0.75 1.1 V B port VCC = 4.75 V IOL = 4 mA 0.5 II Except B port VCC = 0, VI = 5.25 V 100 µA IIH Except B port VCC = 5.25 V, VI = 2.7 V 50 µAIIH B port‡ VCC = 0 to 5.25 V, VI = 2.1 V 100 µA IIL Except B port VCC = 5.25 V, VI = 0.5 V –50 µAIIL B port‡ VCC = 5.25 V, VI = 0.75 V –100 µA IOH B port VCC = 0 to 5.25 V, VO = 2.1 V 100 µA IOZH AO port VCC = 2.1 V to 5.25 V, VO = 2.7 V 50 µA IOZL AO port VCC = 2.1 V to 5.25 V, VO = 0.5 V –50 µA IOZPU A port VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V 50 µA IOZPD A port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA IOS § AO port VCC = 5.25 V, VO = 0 –40 –80 –150 mA ICC All outputs on VCC = 5.25 V, IO = 0 45 70 mA C i AI port and control inputsVI = 0.5 V or 2.5 V 5 pF C o AO port VO = 0.5 V or 2.5 V 5 pF C i B port VCC = 0 to 4.75 V 6 pFC io per IEEE Std 1194.1-1991VCC = 4.75 V to 5.25 V 6 pF † All typical values are at VCC = 5 V, TA = 25°C ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. live-insertion characteristics over recommended operating free-air temperature range (see Note 3) PARAMETER TEST CONDITIONS MIN MAX UNIT ICC (BIAS VCC ) VCC = 0 to 4.75 V, VB = 0 to 2 V, BIAS VCC = 4.5 V to 5.5 V 1.2 mA ICC (BIAS VCC ) VCC = 4.75 V to 5.25 V,VB = 0 to 2 V, BIAS VCC = 4.5 V to 5.5 V 10 µA VO B port VCC = 0, BIAS VCC = 5 V 1.62 2.1 V VCC = 0, VB = 1 V, VI (BIAS VCC ) = 4.75 V to 5.25 V –1 IO B port VCC = 0 to 5.25 V, OEB = 0 to 0.8 V 100 µA VCC = 0 to 2.2 V, OEB = 0 to 5 V 100 NOTE 3: Power-up sequence is GND, BIAS VCC , VCC .
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
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timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25°C MIN MAX UNIT MIN MAX fclock Clock frequency 0 150 0 150 MHz tw Pulse duration, CLKAB/LEAB or CLKBA/LEBA 3.3 3.3 ns tsu Setup time, data before CLKAB/LEAB or CLKBA/LEBA↑ 2.7 2.7 ns th Hold time, data after CLKAB/LEAB or CLKBA/LEBA↑ 0.7 0.7 ns
8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN MAX UNIT(INPUT) (OUTPUT) MIN TYP MAX fmax 150 150 MHz tPLH AI (through mode) B ns tPHL ns tPLH B (th h d ) AO ns tPHL B (through mode) AO 3.1 4.2 5.1 2.6 6 ns tPLH AI (transparent) B ns tPHL ns tPLH B (t t) AO 2.2 4.3 6 2.2 6.6 ns tPHL B (transparent) AO 2.5 4.2 5.6 2.5 6 ns tPLH OEB B ns tPHL ns tPLH OEB B ns tPHL ns tPZH OEA AO ns tPZL OEA AO 2.3 4.3 5.7 2.3 6 ns tPHZ OEA AO 1.7 4 5.5 1.7 5.9 ns tPLZ OEA AO ns tPLH CLKAB/LEAB B ns tPHL ns tPLH CLKBA/LEBA AO ns tPHL CLKBA/LEBA AO ns tPLH OMODE B 2.9 6.6 8.4 2.9 10 ns tPHL OMODE B 3 5.7 7.5 3 8.3 ns tPLH IMODE AO ns tPHL IMODE AO ns tPLH LOOPBACK AO 2 5.2 7.3 2 8.2 ns tPHL LOOPBACK AO ns tPLH AI AO ns tPHL AI AO ns ns ns tr Rise time, 10% to 90%, AO 2.5 3.4 4.8 2 5 ns tf Fall time, 90% to 10%, AO 1.5 2.5 3.8 1 5 ns B-port input pulse rejection 1 ns output-voltage characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT VOHP Peak output voltage during turnoff of 100 mA into 40 nHB port See Figure 1 3 V VOHV Minimum output voltage during turnoff of 100 mA into 40 nHB port See Figure 1 1.62 V VOLV Minimum output voltage during high-to-low switch B port IOL = –50 mA 0.3 V
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Figure 1. Load Circuit for VOHP and VOHV
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74FB2033KRC ACTIVE QFP RC 52 96 TBD CU SNPB Level-2-240C-1YR SN74FB2033KRCR ACTIVE QFP RC 52 500 TBD CU SNPB Level-2-240C-1YR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1
MQFP003 – OCTOBER 1994 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RC (S-PQFP-G52) PLASTIC QUAD FLATPACK 4040151/ B 03/95 0,16 NOM 0,25 1,03 0,73 0,05 MIN Gage Plane 0,22 7,80 TYP 0,38 SQ SQ 9,80 2,20 1,80 10,20 12,95 13,45 2,45 MAX 0,65 M0,13 Seating Plane 0,10 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022
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