FB2033 PHILIPS | Alldatasheet

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Technical content

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

11995 May 25 853-1717 15279

FEATURES

  • 8-bit transceivers
  • Latched, registered or straight through in either A to B or B to A path
  • Drives heavily loaded backplanes with equivalent load impedances down to 10Ω .
  • High drive 100mA BTL Open Collector drivers on B-port
  • Allows incident wave switching in heavily loaded backplane buses
  • Reduced BTL voltage swing produces less noise and reduces power consumption
  • Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity
  • Compatible with IEEE Futurebus+ or proprietary BTL backplanes
  • Each BTL driver has a dedicated Bus GND for a signal return
  • Controlled output ramp and multiple GND pins minimize ground bounce
  • Glitch-free power up/power down operation
  • Low ICC current
  • Tight output skew
  • Supports live insertion QUICK REFERENCE DA TA SYMBOL PARAMETER TYPICAL UNIT tPLH tPHL Propagation delay AIn to Bn 3.0 3.0 ns tPLH tPHL Propagation delay Bn to AOn 4.3 4.1 ns C OB Output capacitance (B0 – Bn only) 6 pF IOL Output current (B0 – Bn only) 100 mA ICC Supply current AIn to Bn (outputs Low or High) 24 mAICC Supply current Bn to AOn (outputs Low) 45 mA Bn to AOn (outputs High) 22

ORDERING INFORMATION

VCC = 5V±10%; Tamb = 0°C to +70°C DRAWING NUMBER 52-pin Plastic Quad Flat Pack (QFP) FB2033BB SOT379-1 NOTE: Thermal mounting or forced air is recommended PIN CONFIGURA TION OEB0 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 BUS GND BUS GND BUS GND BUS GND BUS GND BUS GND BUS GND LOGIC GND AO1 AO2 AO3 LOOPBACK AI4 AI5 AO6 AO7 AI1 AO0 OEA LCBA BIAS V LGOIC GND LCAB 8-Bit Universal Transceiver FB2033 52-lead PQFP BG GNDOEB1 LOGIC GND VCC AI2 AI3 AO4 AI6 LOGIC GND AI7 SAB0 SAB1 VCC BUS GND VCC AO5 AI0 SBA1 SBA0 BG VCC SG00068

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 2

DESCRIPTION

The FB2033 is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level side. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A, SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a register, or a D-type latch. When configured in the buffer mode, the inverse of the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-High latch enables. Regardless of the mode, data is inverted from input to output. Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the Loopback input. When the Loopback input is High the output of the selected A-to-B logic element (not inverted) becomes the B-to-A input. The 3-State AO port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-State (AO port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The “VOH ” clamp reduces inductive ringing effects during a Low-to-High transition. The “VOH ” clamp is always active. The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. To support live insertion, OEB0 is held Low during power on/off cycles to ensure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot. As with any high power device thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature. PIN DESCRIPTION SYMBOL PIN NUMBER TYPE NAME AND FUNCTION AI0 – AI7 50, 52, 3, 5, 8, 10, 12, 15 Input Data inputs (TTL) AO0 – AO7 51, 2, 4, 6, 9, 11, 14, 16 Output 3-State outputs (TTL) B0 – B7 40, 38, 36, 34, 32, 30, 28, 26 I/O Data inputs/Open Collector outputs, High current drive (BTL) OEB0 23 Input Enables the B outputs when High OEB1 24 Input Enables the B outputs when Low OEA 43 Input Enables the AO outputs when High BUS GND 39, 37, 35, 33, 31, 29, 27, 25 GND Bus ground (0V) LOGIC GND 1, 13, 17, 49 GND Logic ground (0V) VCC 18, 22, 48 Power Positive supply voltage BIAS V 41 Power Live insertion pre-bias pin BG V CC 44 Power Band Gap threshold voltage reference BG GND 42 GND Band Gap threshold voltage reference ground SABn 20, 21 Input Mode select from AI to B SBAn 45, 46 Input Mode select from B to AO LCAB 47 Input A-to-B clock/latch enable (transparent latch when High) LCBA 19 Input B-to-A clock/latch enable (transparent latch when High) Loopback 7 Input Enables loopback function when High (from AIn to AOn)

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 3

AIn Bn * OEB0 OEB1 OEA LCAB LCBA SAB 1 SBA 1 AOn Bn AIn to Bn thru mode L — H L L X X LL XX Z H AIn to Bn thru mode H — H L L X X LL XX Z L AIn to Bn transparent latch L — H L L H X HX XX Z H AIn to Bn transparent latch H — H L L H X HX XX Z L AIn to Bn latch and read l — H L L ↓ X HX XX Z H AIn to Bn latch and read h — H L L ↓ X HX XX Z L AIn to Bn register L — H L L ↑ X LH XX Z H AIn to Bn register H — H L L ↑ X LH XX Z L Bn outputs latched and read (preconditioned latch) X — H L L L X HX XX Z latched data Bn to AOn thru mode X L L H H X X XX LL H input Bn to AOn thru mode X H L H H X X XX LL L input Bn to AOn transparent latch X L L H H X H XX HX H input Bn to AOn transparent latch X H L H H X H XX HX L input Bn to AOn latch and read X l L H H X ↓ XX HX H input Bn to AOn latch and read X h L H H X ↓ XX HX L input Bn to AOn register X L L H H X ↑ XX LH H input Bn to AOn register X H L H H X ↑ XX LH L input AOn outputs latched and read (preconditioned latch) X X L H H X L XX HX latched data X Disable Bn outputs X X L X X X X XX XX X H Disable Bn outputs X X X H X X X XX XX X H Disable AOn outputs X X X X L X X XX XX Z X FUNCTION SELECT TABLE MODE SELECTED SXX1 SXX0 Thru mode L L Register mode L H Latch mode H X NOTES: H = High voltage level L = Low voltage level h = High voltage level one set-up time prior to the High-to-Low LCXX transition l = Low voltage level one set-up time prior to the High-to-Low LCXX transition X = Don’t care Z = High-impedance (OFF) state — = Input not externally driven ↑ = Low-to-High transition ↓ = High-to-Low transition H** = Goes to level of pull-up voltage Bn* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. NOTE: In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn inputs are blocked out.

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 4

D En D Clk 50AIn 40 Bn 1 of 8 cells D En D Clk LCBA SBA0 SBA1 OEA AOn 1 of 8 cells 42BGGnd BGref 52, 2, 5, 8, 10, 12, 15 2, 4, 6, 9, 11, 14, 16 38, 36, 34, 32, 30, 28, 26 7Loopback SG00069

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 5

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL PARAMETER RATING UNIT VCC Supply voltage -0.5 to +7.0 V VIN Input voltage All inputs except B0 – Bn -1.2 to +7.0 VVIN Input voltage B0 – Bn -1.2 to +3.5 V IIN Input current -40 to +5.0 mA VOUT Voltage applied to output in High output state -0.5 to +VCC V IOUT Current applied to output in Low output state AO0 – AOn 48 mAIOUT Current applied to output in Low output state B0 – Bn 200 mA TSTG Storage temperature -65 to +150 °C RECOMMENDED OPERA TING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage Except B0 – Bn 2.0 VVIH High-level input voltage B0 – Bn 1.62 1.55 V VIL Low-level input voltage Except B0 – Bn 0.8 VVIL Low-level input voltage B0 – Bn 1.47 V IIK Input clamp current Except B0 – Bn -40 mAIIK Input clamp current B0 – Bn -50 mA IOH High-level output current AO0 – AOn -3 mA IOL Low-level output current AO0 – AOn 24 mAIOL Low-level output current B0 – Bn 100 mA IIA Off device input current Except B0 – Bn, VI = 0 to 5.5V, VCC = 0V 100 µA C OB Output capacitance of B port 6 7 pF Tamb Operating free-air temperature range 0 +70 °C

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 6

DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT IOH High level output currentB0 – Bn VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA IOFF Power-off output currentB0 – Bn VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA VOH High-level output voltageAO0 – AOn 4 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85 V VOL Low-level output voltage AO0 – AOn 4 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA 0.5 VVOL Low-level output voltage B0 – Bn VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA .75 1.0 1.15 VOL B0 – Bn VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA 0.5 VIK Input clamp voltage Except B0–Bn VCC = MIN, II = IIK -0.5 VVIK Input clamp voltage B0 – Bn VCC = MIN, II = IIK 6 0.3 V B0 – Bn VCC = MIN, II = -18mA -1.2 II Input current at maximum input voltage Except B0–Bn VCC = MAX, VI = 0.0V or 5.5V ±50 µA IIH High-level input current Except B0–Bn VCC = MAX, VI = 2.7V, Bn = AIn = 0V 20 µA IIH High-level input current B0 – Bn VCC = MAX, VI = 1.9V 100 µA B0 – Bn VCC = MAX, VI = 3.5V 5 100 mA IIL Low-level input current Except B0–Bn VCC = MAX, VI = 0.5V -20 µAIIL Low-level input current B0 – Bn VCC = MAX, VI = 0.75V -100 µA IOZH Off-state output currentAO0 – AOn VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output currentAO0 – AOn VCC = MAX, VO = 0.5V -50 µA IOS Short-circuit output current 3 AO0 – AOn only VCC = MAX, VO = 0.0V -45 -150 mA ICC Supply current (total) AIn to Bn VCC = MAX, outputs Low or High 24 50 mAICC Supply current (total) Bn to AOn VCC = MAX, outputs Low 45 75 mACC Bn to AOn VCC = MAX, outputs High 22 44 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally. 6. B0 – B7 clamps remain active for a minimum of 80ns following a High-to-Low transition.

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 7

LIVE INSERTION SPECIFICATIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VBIASV Bias pin voltage VCC = 0 to 5.25V, Bn = 0 to 2.0V 4.5 5.5 V IBIASV Bias pin DC current VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 1 mA IBIASV Bias pin DC current VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 10 µA VBn Bus voltage during pre-biasB0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V ILM Fall current during pre-biasB0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA IHM Rise current during pre-biasB0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA IBn Peak bus current during insertion VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns 10 mA IOL Power up current VCC = 0 to 5.25V, OEB0 = 0.8V 100 µAIOL Power up current VCC = 0 to 2.2V, OEB0 = 0 to 5V 100 µA tGR Input glitch rejection VCC = 5.0V 1.0 1.35 ns AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITION A PORT LIMITS UNITSYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, C L = 50pF, RL = 500Ω Tamb = 0 to 70°C, VCC = 5V±10%, C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency W aveform 4 100 150 100 MHz tPLH tPHL Propagation delay (thru mode) Bn to AOn W aveform 1, 2 2.2 2.0 4.3 4.1 6.0 6.0 2.0 1.8 7.0 7.0 ns tPLH tPHL Propagation delay (transparent latch) Bn to AOn W aveform 1, 2 1.5 2.4 4.5 4.4 6.5 6.5 1.0 2.0 7.5 7.5 ns tPLH tPHL Propagation delay LCBA to AOn W aveform 1, 2 2.0 2.2 3.8 4.3 5.5 6.0 1.8 1.7 6.0 6.5 ns tPLH tPHL Propagation delay SBAn to AOn W aveform 1, 2 1.4 1.4 2.9 3.1 5.0 5.5 1.0 1.0 6.0 6.5 ns tPLH tPHL Propagation delay (Loopback mode) AIn to AOn W aveform 1, 2 2.0 2.0 3.8 3.9 6.0 6.0 2.8 2.3 7.0 7.0 ns tPLH tPHL Propagation delay (Loopback mode) Loopback to AOn W aveform 1, 2 1.2 1.2 3.4 3.2 5.0 5.5 1.0 1.0 6.0 6.5 ns tPZH tPZL Output enable time from High or Low OEA to AOn W aveform 5, 6 1.0 2.6 3.1 4.0 5.1 5.5 1.0 2.4 5.5 5.8 ns tPHZ tPLZ Output disable time to High or Low OEA to AOn W aveform 5, 6 1.0 1.0 3.5 3.3 5.0 4.6 1.7 1.7 5.6 5.2 ns tTLH tTHL Output transition time, AOn Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 2.0 2.0 5.0 5.0 ns tSK (o) Output to output skew, A port 1 W aveform 3 0.5 1.0 1.5 ns tSK (p) Pulse skew 2  tPHL – tPLH  MAX W aveform 2 0.3 1.0 1.5 ns NOTES: 1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts. 2.  tPN actual – tPM actual/n636861720000000000000000for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC , loading, etc.). 3. tSK (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 8

AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER TEST CONDITION B PORT LIMITS UNITSYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, C D = 30pF, RU = 9Ω Tamb = 0 to 70°C, VCC = 5V±10%, C D = 30pF, RU = 9Ω UNIT MIN TYP MAX MIN MAX tPLH tPHL Propagation delay (thru mode) AIn to Bn W aveform 1, 2 1.2 1.0 2.9 2.9 4.3 4.4 1.0 1.0 4.8 4.6 ns tPLH tPHL Propagation delay (transparent latch) AIn to Bn W aveform 1, 2 1.4 1.0 3.1 3.3 4.5 4.8 1.0 1.0 5.1 5.1 ns tPLH tPHL Propagation delay LCAB to Bn W aveform 1, 2 2.7 2.2 4.4 5.1 5.7 6.6 2.4 2.0 6.4 7.1 ns tPLH tPHL Propagation delay SABn to Bn W aveform 1, 2 1.8 1.0 3.6 3.3 5.0 4.9 1.4 1.0 5.7 5.2 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn W aveform 1, 2 1.4 1.0 3.0 3.1 4.5 5.0 1.0 1.0 5.0 5.6 ns ΔV/Δt Output transition rate, Bn Port 20% to 80%, 80% to 20% Test Circuit and Waveforms 0.4 1.2 V/ns tSK (o) Output to output skew, B port 1 W aveform 3 0.8 1.5 2.0 ns tSK (p) Pulse skew 2  tPHL – tPLH  MAX W aveform 2 0.3 1.5 ns SYMBOL PARAMETER TEST CONDITION R U = 16.5Ω R U = 16.5Ω UNIT tPLH tPHL Propagation delay (thru mode) AIn to Bn W aveform 1, 2 1.2 1.0 3.0 3.0 4.4 4.5 1.0 1.0 4.9 4.7 ns tPLH tPHL Propagation delay (transparent latch) AIn to Bn W aveform 1, 2 1.4 1.0 3.2 3.4 4.6 4.9 1.0 1.0 5.2 5.2 ns tPLH tPHL Propagation delay LCAB to Bn W aveform 1, 2 2.7 2.2 4.5 5.2 5.8 6.7 2.4 2.0 6.5 7.2 ns tPLH tPHL Propagation delay SABn to Bn W aveform 1, 2 1.8 1.0 3.7 3.4 5.1 5.0 1.4 1.0 5.8 5.3 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn W aveform 1, 2 1.4 1.0 3.1 3.2 4.6 5.1 1.0 1.0 5.1 5.7 ns ΔV/Δt Output transition rate, Bn Port 20% to 80%, 80% to 20% Test Circuit and Waveforms 0.2 0.6 V/ns tSK (o) Output to output skew, B port 1 W aveform 3 0.5 1.0 1.5 ns tSK (p) Pulse skew 2  tPHL – tPLH  MAX W aveform 2 0.3 1.0 1.5 ns NOTES: 1.  tPN actual – tPM actual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC , loading, etc.). 2. tSK (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 9

Tamb = +25°C, VCC = 5V Tamb = 0 to 70°C, VCC = 5V±10% UNITSYMBOL PARAMETER TEST CONDITION C L = 50pF (A side) / CD = 30pF (B side) R L = 500Ω (A side) / RU = 9Ω (B side) UNIT MIN TYP MAX MIN MAX ts(H) ts(L) Setup time AIn to LCAB or Bn to LCBA W aveform 4 3.0 3.0 4.0 4.0 ns th(H) th(L) Hold time AIn to LCAB or Bn to LCBA W aveform 4 1.0 1.0 1.3 1.3 ns tw (H) tw (L) Pulse width, High or Low LCAB or LCBA W aveform 4 3.0 3.0 4.0 4.0 ns SYMBOL PARAMETER TEST CONDITION C L = 50pF (A side) / CD = 30pF (B side) R L = 500Ω (A side) / RU = 16.5Ω (B side) UNIT ts(H) ts(L) Setup time AIn to LCAB or Bn to LCBA W aveform 4 3.0 3.0 4.0 4.0 ns th(H) th(L) Hold time AIn to LCAB or Bn to LCBA W aveform 4 1.0 1.0 1.3 1.3 ns tw (H) tw (L) Pulse width, High or Low LCAB or LCBA W aveform 4 3.0 3.0 4.0 4.0 ns AC WAVEFORMS ÍÍ ÍÍ ÍÍ ÍÍ VM ts tPZL Input Output VMVM VMVM tPLH tPHL VMVM VM VM tPHL tPLH Output AIn, Bn AOn, Bn VM VM tSK (o) AOn OEA VMVM tPLZ VM VOL +0.3V AOn OEA VM VM VM VOH -0.3V OV tPHZtPZH Input ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ AIn, Bn LCAB, LCBA VM VM 1/fMAX th ts th tw (L) tw (H) NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Propagation Delay for Data or Output Enable to Output W aveform 2. Propagation Delay for Data or Output Enable to Output W aveform 3. Output to Output Skew W aveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency W aveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level W aveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level SG00070

Philips Semiconductors Product specification FB20338-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

1995 May 25 10

TEST CIRCUIT AND W AVEFORMS 2.5ns 2.0ns500ns 500ns INPUT PULSE REQUIREMENTS Rep. RateAmplitude tTLH tTHL 1MHz3.0V 2.5ns Input Pulse Definitions VM = 1.55V for Bn, VM = 1.5V for all others. VCC Family FB+ D.U.T.PULSE GENERATOR 7.0V R L R LC LR T VIN VOUT Test Circuit for 3-State Outputs on A Port TEST SWITCH SWITCH POSITION tPLZ, tPZL All other closed open DEFINITIONS: R L = Load Resistor; see AC CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R T = T ermination resistance should be equal to ZOUT of pulse generators. C D = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R U = Pull up resistor; see AC CHARACTERISTICS for value. tW 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE AMP (V) LOW V LOW V tTHL (tf) tTLH (tr) tW tWLow V 0.0V tTLH (tr) tTHL (tf) AMP (V) A Port 1MHz2.0V 2.0ns1.0VB Port VCC D.U.T.PULSE GENERATOR R U C DR T VIN VOUT Test Circuit for Outputs on B Port BIAS V 2.0V (for RU = 9 Ω ) 2.1V (for RU = 16.5 Ω ) SG00063