FAN9672 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Continuous Conduction Mode Control
- Two−Channel PFC Control (Maximum)
- Average Current−Mode Control
- PFC Slave Channel Management Function
- Programmable Operation Frequency Range: 18 kHz ∼ 40 kHz or 55 kHz ∼ 75 kHz
- Programmable PFC Output V oltage
- Dual Current Limit Functions
- TriFault Detect Protects Against Feedback Loop Failure
- Sag Protection
- Programmable Soft−Start
- Under−V oltage Lockout (UVLO)
- Differential Current Sensing
- Available in 32−Pin LQFP Package Typical Applications
- High Power AC−DC Power Supply
- DC Motor Power Supply
- White Goods; e.g. Air Conditioner Power Supply
- Server and Telecom Power Supply
- UPS
- Industrial Welding and Power Supply www.onsemi.com MARKING DIAGRAM See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
LQFP−32 FT SUFFIX CASE 561AB Z = Assembly Plant Code X = Year Code Y = Work Code TT = Die Run Code T = Package Type (Q:LQFP) M = Manufacture Flow Code 32 31 30 29 28 27 26 25 10 11 12 13 14 15 169 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 BIBO PVO ILIMIT GC RI RLPK ILIMIT2 LPK GND CS1+ CS1− CS2+ CS2− NC NC LS RDY IEA1 IEA2 NC CM1 CM2 NC VIR IAC SS VEA FBPFC VDD OPFC1 OPFC2 NC ZXYTT F A N 9 6 7 2 TM ON
www.onsemi.com Temperature Range Package Packing Method FAN9672Q −40°C to 105°C 32−Lead, Low Quad Flat Package (LQFP), JEDEC MS−026, Variation BBA, 7 mm Square Tray TYPICAL APPLICATION Figure 1. Typical Application Diagram for Two−Channel PFC Converter
Figure 2. Functional Block Diagram
27 OPFC1
26 OPFC2
55 A5 5 A
Figure 3. Pin Layout (Top View)
Table 1. PIN DEFINITIONS 1 BIBO Brown−In/Out Level Setting: This pin is used for brown in/out setting. value of the current command. GND is recommended for noise filtering. mined by the tolerance of RRLPK at this pin. current threshold for cycle−by−cycle current limit. RDY signal to inform the MCU the downstream power stage can start normal operation. If AC brownout is detected, the VRDY signal is LOW to signal the MCU the PFC is not ready. nal to determine the pulse width for PFC gate drive 1. nal to determine the pulse width for PFC gate drive 2.
13 CM1 Channel 1 Management Setting: This pin is used to configure the characteristics of PFC enable/
crease loading of channel 2 when VVEA, proportional to power level, meets the setting level on VCM2. 16 VIR Input Voltage Range Setting: A capacitor and a resistor are connected in parallel from this pin to GND. range (90 VAC ∼264 VAC) and RIAC must be 6 M/C0087. Voltage between 1.5 V and 3.5 V is not allowed. recommended for noise filtering.
20 CS2− Channel 2 Negative PFC Current Sense Input
21 CS2+ Channel 2 Positive PFC Current Sense Input
22 CS1− Channel 1 Negative PFC Current Sense Input
23 CS1+ Channel 1 Positive PFC Current Sense Input
24 GND Ground Reference and Return
internal 15 V clamp to protect the external power switch.
Table 1. PIN DEFINITIONS (continued) internal 15 V clamp to protect the external power switch. PFC output through a resistor−divider network. 30 VEA Output of PFC Voltage−Loop Amplifier: An error−amplifier output for the PFC voltage feedback loop. A compensation network is connected between this pin and ground. able the gate drive outputs OPFC1 and OPFC2. modulator. The recommended maximum current on IAC is 65 /C0109A. should not be assumed, damage may occur and reliability may be affected. the Recommended Operating Ranges limits may affect device reliability.
- All voltage values, except differential voltage, are given with respect to GND pin.
- Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
www.onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C) Symbol Parameter Condition Min Typ Max Unit VDD SECTION IDD ST Startup Current VDD = VTH−ON - 0.1 V 30 80 /C0109A IDD−OP Operating Current VDD = 14 V, Output Not Switching, RRI = 25 k/C0087 4 6 7 mA VTH−ON Turn−On Threshold Voltage VDD Rising 11.7 12.8 13.9 V ΔVTH UVLO Hysteresis 2 3 V VDD−OVP VDD OVP Threshold OPFC1~2 Disabled, IEA1~2 and SS Pull Low 23 24 25 V ΔVDD−OVP VDD OVP Hysteresis 1 V tD−OVP VDD OVP Debounce Time 80 /C0109s OSCILLATOR (Note 3) VRI Sourcing Voltage on RI RRI = 25 k/C0087 1.15 1.20 1.25 V fOSC1 PFC Frequency Test Case 1 RRI = 25 k/C0087 30 32 34 kHz fOSC2 PFC Frequency Test Case 2 RRI = 12.5 k/C0087 58 62 66 kHz fDV Voltage Stability 13 V ≤ VDD ≤ 22 V 2 % fDT Temperature Stability 2 % ΔVIEA−SAW32 VIEA−SAW of PFC Frequency 32 kHz RRI = 25 k/C0087 5 V ΔVIEA−SAW64 VIEA−SAW of PFC Frequency 64 kHz RRI = 12.5 k/C0087 5.15 V DPFC−MAX Maximum Duty Cycle VIEA > 7 V 94 97 % DPFC−MIN Minimum Duty Cycle VIEA < 1 V 0 % fRANGE1 Frequency Range 1 (Notes 3, 4) 18 40 kHz fRANGE2 Frequency Range 2 (Notes 3, 4) 55 75 kHz tDEAD−MIN Minimum Dead Time RRI = 10.7 k/C0087 600 ns INPUT−RANGE SETTING (VIR) VVIR−H HIGH Setting Level for High Voltage In- put Range RVIR = 500 k/C0087 (VVIR = 5 V) 3.5 V VVIR−L LOW Setting Level for Low Voltage Input Range or Full Voltage Input Range VVIR = 0 V 1.5 V IVIR Sourcing Current of VIR Pin 7 10 13 /C0109A PFC Soft−Start ISS Constant Current Output for Soft−Start System Brown−in 22 /C0109A VSS Maximum Voltage on SS 6.8 V ISS−Discharge Discharge Current of SS Pin Brownout, SAG, VCM1>4 V, RRI Open / Short, OTP 60 /C0109A VOLTAGE ERROR AMPLIFIER VREF Reference Voltage PVO = GND, TJ = 25°C 2.45 2.50 2.55 V AV Open-Loop Gain (Note 3) 42 65 dB Gmv Transconductance VNONINV − VINV = 0.5 V, TJ = 25°C 100 /C0109S IFBPFC−L Maximum Source Current VFBPFC = 2 V, VVEA = 3 V 40 50 /C0109A IFBPFC−H Maximum Sink Current VFBPFC = 3 V, VVEA = 3 V −50 −40 /C0109A IBS Input Bias Current Range −1 1 /C0109A IFBPFC−FL Pull High Current for FBPFC FBPFC Floating 500 nA VVEA-H Output High Voltage on VVEA VFBPFC = 2 V 5.7 6.0 V VVEA-L Output Low Voltage on VVEA VFBPFC = 3 V 0 0.15 V
www.onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C) Symbol UnitMaxTypMinConditionParameter VOLTAGE ERROR AMPLIFIER IVEA−DIS Discharge Current Brownout, RRI Open /Short, OTP, SAG 10 /C0109A VVEA-OFF Threshold Voltage for Low−Power De- tection When VVEA < VVEA−OFF, VOPFC1~2 are Off & VIEA1~2 are Pulled Low 0.3 V CURRENT ERROR AMPLIFIERS Gmi Transconductance VNONINV = VINV, VIEA = 4 V, VILIMIT > 0.6 V, TJ = 25°C 88 /C0109S VOFFSET Input Offset Voltage VVEA = 0.45 V, RIAC=12 M/C0087, VIAC = 311 V, VFBPFC = 2 V, VVIR = 5 V, TJ = 25°C 0 mV VIEA−H Output High Voltage 6.8 7.0 V VIEA−L Output Low Voltage 0 0.4 V IL Sourcing Current VNONINV − VINV, = +0.6 V, VIEA = 1 V, VILIMIT >0.6 V 35 50 /C0109A IH Sinking Current VNONINV − VINV, = -0.6 V, VIEA = 6.5 V, VILIMIT > 0.6 V −50 −35 /C0109A AI Open−Loop Gain (Note 3) 40 50 dB IIEA−LOW IEA Pin Pull−Low Capability VIEA /C0119 5 V 500 /C0109A GAIN MODULATOR (Current Command Generator) IAC Input for AC Current (Notes 3, 5) Multiplier Linear Range 0 65 /C0109A BW Bandwidth (Notes 3, 5) IAC = 40 /C0109A 2 kHz VRM Gain Modulator Output (IMO* RM) Test Cases VIAC = 106.07 V, RIAC = 6 M/C0087, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2 > 4.5 V, TJ = 25°C 0.490 V VIAC = 120.21 V, RIAC = 6 M/C0087, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2 > 4.5 V, TJ = 25°C 0.430 VIAC = 155.56 V, RIAC = 6 M/C0087, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2 > 4.5 V, TJ = 25°C 0.327 VIAC = 311.13 V, RIAC = 12 M/C0087, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2 > 4.5 V, VVIR > 3.5 V, TJ = 25°C 0.320 VIAC = 373.35 V, RIAC = 12 M/C0087, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2 > 4.5 V, VVIR > 3.5 V, TJ = 25°C 0.260 RM Resistor of Gain Modulator Output RM = VRM /IMO 7.5 k/C0087 ILIMIT (Current Command Limit) VRM−R Range of Peak Value in Current Command (VILIMIT/4) 0.2 0.8 V VRM−ILIMIT Current Command Limit Test Case RILIMIT = 42 k/C0087, RRI = 25 k/C0087, VRM−LIMIT = RILIMIT * IILIMIT/4 0.504 V IILIMIT Sourcing Current of ILIMIT Pin RRI = 25 k/C0087 49 /C0109A ILIMIT2 (CS1/CS2, Pulse−by−Pulse Current Limit) VILIMIT2−CS1 Peak Current Limit Voltage Test Case RILIMIT2 = 30 k/C0087, RRI = 25 k/C0087, CS1~2 > VILIMIT2 OPFC1 Disables, VIEA1~2 Pull Low 1.48 V VILIMIT2−CS2 1.48 V IILIMIT2 Sourcing Current for ILIMIT2 Pin RRI = 25 k/C0087, TJ = 25°C 49.5 /C0109A tPFC−BNK1 Leading−Edge Blanking Time of ILIMIT of Each Channel VDD = 15 V, OPFC Drops to 9 V 250 ns tPFC−BNK2 250 ns
www.onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C) Symbol UnitMaxTypMinConditionParameter ILIMIT2 (CS1/CS2, Pulse−by−Pulse Current Limit) tPD1 Propagation Delay to Output of Each Channel 200 400 ns tPD2 200 400 ns VILIMIT2−OPEN Threshold of ILIMIT2 Open−Circuit Pro- tection OPFC1~2 Disabled and VIEA1~3 Pull Low 3.8 4.0 4.2 V TriFault Detect™ VPFC−UVP FBPFC Under−Voltage Protection 0.4 0.5 0.6 V VPFC−OVP FBPFC Over−Voltage Protection (OVP) 2.70 2.75 2.80 V ΔVPFC−OVP FBPFC OVP 200 250 300 mV tFBPFC-OPEN FBPFC Open Delay (Note 3) VFBPFC = VPFC−UVP to FBPFC Open, 470 pF from FBPFC to GND 2 ms tFBPFC−UVP Under−Voltage Protection Debounce Time 50 /C0109s PVO VPVO Programmable Output Setting Range on PVO Pin 0.3 3.5 V VPVO_DIS PVO Disable Voltage PVO< VPVO_DIS 0.2 V VPVO−CLAMPH Low−clamp of FBPFC based on PVO FBPFC Connected to VEA, VPVO = 4 V 1.6 V VFBPFC1 FBPFC Voltage Test Cases FBPFC Connected to VEA, V PVO = 0.3 V 2.425 V VFBPFC2 FBPFC Connected to VEA, V PVO = 3.5 V 1.625 V IPVO−Discharge PVO Discharge Current PVO Open 1 /C0109A GAIN COMPENSATION (GC) SECTION (Note 6) IGC−L1 Test Cases of Mirror Current of IAC on GC Pin VVIR = 0 V, VIAC = 127.28 V, RIAC = 6 M/C0087, 20.71 /C0109A IGC−L2 VVIR = 0 V, VIAC = 311.13 V, RIAC = 6 M/C0087, 51.86 /C0109A IGC−HV VVIR = 5 V, VIAC = 311.13 V, RIAC = 12 M/C0087. 51.86 /C0109A IGC−OPEN Pull High Current for GC−Pin Open 100 nA VGC−OPEN GC−Pin Open Voltage VGC > VGC−OPEN VIEA, OPFC1&2 Blanking 2.85 3.00 3.15 V INDUCTANCE SETTING (LS) Section (Note 6) RLS Acceptable Range of Inductance Setting 12 87 k/C0087 VLS−MIN Voltage Difference between VFBPFC and VGC on LS Pin VFBPFC – VGC ≥ 0 V 50 mV BROWN IN /OUT VBIBO−FL Threshold of Brown−out at VIR = LOW Setting (Full AC−Input Range) VVIR < 1.5 V, RIAC = 6 M/C0087 1.00 1.05 1.10 V ΔVBIBO−F Hysteresis VBIBO > VBIBO−FL + △VBIBO−F, Brown−in, Start SS 850 mV VBIBO−HL Threshold of BO at VIR=HIGH Setting (High AC−Input Range) VVIR > 3.5 V, RIAC = 12 M/C0087 1.00 1.05 1.10 V ΔVBIBO−H Hysteresis VBIBO > VBIBO−HL + △VBIBO−H, Brown−in, Start SS 700 mV tUVP Under−Voltage Protection Delay Time 450 ms
www.onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C) Symbol UnitMaxTypMinConditionParameter SAG PROTECTION SECTION VSAG SAG Voltage of BIBO 1. VBIBO < VSAG & VRDY High for 33 ms, or 2. VBIBO < VSAG & VRDY Low, Brownout, 0.85 V tSAG−DT SAG Debounce Time VBIBO < VSAG & VRDY High 33 ms RLPK, VOLTAGE−SETTING RESISTANCE FOR PEAK DETECTOR IRLPK−OPEN Pull High Current for RLPK Open 100 nA VRLPK−OPEN RLPK Open Voltage RLPK Open 2.28 2.40 2.52 V LPK, PEAK−DETECTOR OUTPUT (Note 7) VLPK−H1 VLPK Output Test Cases VIAC = 311 V, RIAC = 1 2M/C0087, VVIR > 3.5 V, RLPK = 12.4 k/C0087, TJ = 25°C 3.168 V VLPK−H2 VIAC = 373 V, RIAC = 12 M/C0087, VVIR > 3.5 V, RLPK = 12.4 k/C0087, TJ = 25°C 3.80 V VLPK−L1 VIAC = 127 V, RIAC = 6 M/C0087, VVIR < 1.5 V, RLPK = 12.4 k/C0087, TJ = 25°C 1.29 V VLPK−L2 VIAC = 373 V, RIAC = 6 M/C0087, VVIR < 1.5 V, RLPK = 12.4 k/C0087, TJ = 25°C 3.80 V VAC−OFF AC OFF Threshold Voltage Test Case VIAC = 373 V, RIAC = 12 M/C0087, VVIR > 3.5V After tAC−OFF VIEA Pull Low 32 V VAC−ON AC ON Threshold Voltage Test Case VIAC = 373 V, RIAC = 12 M/C0087, VVIR > 3.5 V VAC−OFF +26 V CM1 SECTION ICM1 CM1 Sourcing Current 55 /C0109A VCM1−disable PFC Disable Voltage ICM1 * RCM1 > 4 V OPFC1~2 Disabled and IEA1~2 Pull Low and SS Pull Low 4 V /C01131 Phase of OPFC1 When ICM1 * RCM1 < 4 V or Short 0 ° /C01132 Phase of OPFC2 (Note 8) 170 180 190 ° CM2 SECTION ICM2 CM2 Sourcing Current 55 /C0109A VCM2−disable Channel−2 Disable Voltage ICM2 * RCM2 > 4 V or CM2 Floating OPFC2 Disables and IEA2 PulIs Low 4 V VCM2−range Set VEA Unload Voltage 0 3.8 V RDY SECTION VFB−RD Level of VFBPFC to Pull RDY High VPVO = 0 V, Brown−in, VFBPFC > VFB−RD 2.3 2.4 2.5 V ΔVFB−RD−L Hysteresis VPVO = 0 V, VIR < 1.5 V 1.15 V ΔVFB−RD−H Hysteresis VPVO = 0 V, VIR > 3.5 V 0.85 V ZRDY Pull High Input Impedance TJ = 25°C 100 k/C0087 VRDY−High High Voltage of RDY 4.8 5.0 V VRDY−Low Low Voltage of RDY Pull High Current = 1 mA 0.5 V PFC OUTPUT DRIVER 1~2 VGATE−CLAMP Gate Output Clamping Voltage VDD = 22 V 13 15 17 V
www.onsemi.com Table 5. TYPICAL APPLICATION CIRCUIT
- 180 VAC ~264 V , Two−Channel PFC Using FAN9672
- Switch−Charge Technique of Gain Modulator for Better PF and Lower THD
- 40 kHz Low Switching Frequency Operation with IGBT
- Over−V oltage Protection (OVP), Under −V oltage Protection (UVP), Over −Current Protection (I LIMIT), Inductor Saturation Protection (ILIMIT2)
Figure 52. Schematic of Design Example
1 M/C0087
6 M/C0087
2.2 M/C0087
1.5 M/C0087
- VDD Maximum Rating: 20 V
- VDD OVP: 24 V
- VCC UVLO: 10.3 V/12.8 V
- PVO: 0 V ∼ 1 V
- PFC Soft−Start: CSS = 0.47 /C0109F
- Brown−In/Out: 170 V/160 V
- Switching Frequency: 40 kHz
- VFBPFC for RDY: 2.4 V/1.55 V (96% / 62%)
- RIAC: 12 M/C0087 Inductor Schematic Diagram
- Switching Frequency: 40 kHz
- Bobbin: 7 Pins
Figure 53. Inductor Schematic Diagram Table 6. WINDING SPECIFICATION Table 7. MOSFET AND DIODE REFERENCE SPECIFICATION
600 V (IGBT) FGH40N60SMDF
600 V FFH30S60STU
Table 8. EFFICIENCY Table 9. POWER FACTOR
Table 10. TOTAL HARMONIC DISTORTION
- Pay attention to the inrush current when AC input is first connected to the boost PFC convertor. It is recommended to use NTC and a parallel connected relay circuit to reduce inrush current.
- Add bypass diode to provide a path for inrush current when PFC start up.
- The PFC stage is normally used to provide power to a downstream DC −DC or inverter. It’s recommend that downstream power stage is enabled to operate at full load once the PFC output voltage has reaches a level close to the specified steady−state value.
- The PVO function is used to change the output voltage of PFC, VPFC. The VPFC should be kept at least 25 V higher than VIN.
LQFP−32, 7x7 CASE 561AB−01 ISSUE O DATE 19 JUN 2008 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON30893EDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 132 LEAD LQFP , 7X7 © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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