FAN9611

FAN9611 ONSEMI | Alldatasheet

Document overview

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• PDF pages: 36

Technical content

Features

• Sync−Lock Interleaving Technology for 180° Out−of−Phase Synchronization Under All Conditions
• Automatic Phase Disable at Light Load
• Dead−Phase Detect Protection
• 2.0 A Sink, 1.0 A Source, High−Current Gate Drivers
• High Power Factor, Low Total Harmonic Distortion
• V oltage−Mode Control with (VIN)2 Feedforward
• Closed−Loop Soft−Start with User−Programmable Soft−Start Time for Reduced Overshoot
• Minimum Restart Frequency to Avoid Audible Noise
• Maximum Switching Frequency Clamp
• Brownout Protection with Soft Recovery
• Non−Latching OVP on FB Pin and Latching Second−Level Protection on OVP Pin
• Open−Feedback Protection
• Power−Limit and Current Protection for Each Phase
• Low Startup Current of 80 /C0109A Typical
• Works with DC and 50 Hz to 400 Hz AC Inputs MARKING DIAGRAM $Y = Logo &Z = Assembly Plant Code &2 = 2−Digit Date Code &K = 2−Digits Lot Run Traceability Code FAN9611 = Device Code $Y&Z&2&K FAN9611 Device Package Shipping †

ORDERING INFORMATION

FAN9611MX 16−Lead, Small Outline Integrated Circuit (SOIC) (Pb−Free) 2,500 / Tape & Reel SOIC−16, 150 mils CASE 751BG−01 †For information on tape and reel specifications , including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. This device passed wa ve soldering test by JESD22A−111.

Applications

• 100 − 1000 W AC−DC Power Supplies
• Large Screen LCD−TV , PDP−TV , RP−TV Power
• High−Efficiency Desktop and Server Power Supplies
• Networking and Telecom Power Supplies
• Solar Micro Inverters Related Resources
• Evaluation Board: FEBFAN9611_S01U300A

Figure 3. Typical Application Diagram

3 VREF

5 V VDD

Figure 4. Block Diagram

Figure 5. Pin Layout (Top−View) 1 ZCD1 Zero Current Detector for Phase 1 of the interleaved boost power stage. 2 ZCD2 Zero Current Detector for Phase 2 of the interleaved boost power stage. 3 5VB 5 V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC. 4 MOT Maximum On−Time adjust for the individual power stages. 5 AGND Analog Ground. Reference potential for all setup signals. 6 SS Soft−Start Capacitor. Connected to the non−inverting input of the error amplifier.

7 COMP Compensation Network connection to the output of the gM error amplifier

8 FB Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier. 9 OVP Output Voltage monitor for the independent, second−level, latched OVP protection. 10 VIN Input Voltage monitor for brownout protection and input−voltage feedforward. 11 PGND Power Ground connection. 12 DRV2 Gate Drive Output for Phase 2 of the interleaved boost power stage. 13 DRV1 Gate Drive Output for Phase 1 of the interleaved boost power stage. 14 VDD External Bias Supply for the IC. 15 CS2 Current Sense Input for Phase 2 of the interleaved boost power stage. 16 CS1 Current Sense Input for Phase 1 of the interleaved boost power stage.

www.onsemi.com ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VDD Supply Voltage to AGND & PGND −0.3 20.0 V VBIAS 5VB Voltage to AGND & PGND −0.3 5.5 V Voltage On Input Pins to AGND (Except FB Pin) −0.3 VBIAS + 0.3 V Voltage On FB Pin (Current Limited) −0.3 VDD + 0.8 V Voltage On Output Pins to PGND (DRV1, DRV2) −0.3 VDD + 0.3 V IOH, IOL Gate Drive Peak Output Current (Transient) − 2.5 A Gate Drive Output Current (DC) − 0.05 A TL Lead Soldering Temperature (10 Seconds) − +260 °C TJ Junction Temperature −40 +150 °C TSTG Storage Temperature −65 +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit VDD Supply Voltage Range 9 12 18 V VINS Signal Input Voltage 0 − 5 V ISNK Output Current Sinking (DRV1, DRV2) 1.5 2.0 − A ISRC Output Current Sourcing (DRV1, DRV2) 0.8 1.0 − A LMISMATCH Boost Inductor Mismatch (Note 5) − ±5% ±10% TA Operating Ambient Temperature −40 − +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. While the recommended maximum inductor mismatch is ±10% for optimal current sharing and ripple−current cancellation, there is no absolute maximum limit. If the mismatch is greater than ±10%, current sharing is proportionately worse, requiring over−design of the power supply. However, the accurate 180 ° out−of−phase synchronization is still maintained, providing current cancellation, although its effectiveness is reduced.

www.onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the device.) Symbol Parameter Conditions Min Typ Max Unit SUPPLY ISTARTUP Startup Supply Current VDD = VON – 0.2 V − 80 110 /C0109A IDD Operating Current Output Not Switching − 3.7 5.2 mA IDD_DYM Dynamic Operating Current (Note 6) fSW = 50 kHz; CLOAD = 2 nF − 4 6 mA VON UVLO Start Threshold VDD Increasing 9.5 10.0 10.5 V VOFF UVLO Stop Threshold Voltage VDD Decreasing 7.0 7.5 8.0 V VHYS UVLO Hysteresis VON – VOFF − 2.5 − V BIAS REGULATOR (C5VB = 0.1 /C0109F) V5VB 5VB Output Voltage TA = 25°C; ILOAD = 1 mA − 5.0 − V Total Variation Over Line, Load, and Temperature 4.8 − 5.2 IOUT_MAX Maximum Output Current 5.0 − − mA ERROR AMPLIFIER VEA Voltage Reference TA = 25°C 2.95 3.00 3.05 V Total Variation Over Line, Load, and Temperature 2.91 − 3.075 IBIAS Input Bias Current VFB = 1 V to 3 V; |VSS – VFB| ≤ 0.1 V −0.2 − 0.2 /C0109A IOUT_SRC Output Source Current VSS = 3 V; VFB = 2.9 V −13.7 −8 −4 /C0109A IOUT_SINK Output Sink Current VSS = 3 V; VFB = 3.1 V 4 8 12 /C0109A VOH Output High Voltage 4.5 4.7 V5VB V VOL Output Low Voltage ISINK < 100 /C0109A 0.0 0.1 0.2 V gM Transconductance 50 78 115 /C0109mho PWM VRAMP,OFST PWM Ramp Offset TA = 25°C 120 195 270 mV tON,MIN Minimum On−Time VFB > VSS − − 0 /C0109s MAXIMUM ON−TIME VMOT Maximum On−Time Voltage R = 125 k/C0087 1.16 1.25 1.30 V tON,MAX Maximum On−Time R = 125 k/C0087; VVIN = 2.5 V; VCOMP > 4.5 V; TA = 25°C 3.4 5.0 6.6 /C0109s RESTART TIMER (Each Channel) fSW,MIN Minimum Switching Frequency VFB > VPWM_OFFSET 12.5 16.5 20.0 kHz FREQUENCY CLAMP (Each Channel) fSW,MAX Maximum Switching Frequency (Note 6) 400 525 630 kHz CURRENT SENSE VCS CS Input Threshold Voltage Limit 0.19 0.21 0.23 V ICS CS Input Current VCSX = 0 V to 1 V −0.2 − 0.2 /C0109A tCS_DELAY CS to Output Delay CS Stepped from 0 V to 5 V − 85 100 ns ZERO CURRENT DETECTION VZCD_IN Input Voltage Threshold (Note 6) VZCD is Falling −0.1 0 0.1 V VZCD_H Input High Clamp Voltage IZCD = 0.5 mA 0.8 1.0 1.2 V VZCD_L Input Low Clamp Voltage IZCD = –0.5 mA −0.7 −0.5 −0.3 V IZCD_SRC Source Current Capability (Note 6) − − 1 mA

www.onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the device.) (continued) Symbol UnitMaxTypMinConditionsParameter ZERO CURRENT DETECTION IZCD_SNK Sink Current Capability (Note 6) − − 10 mA tZCD_DLY Turn−On Delay (Note 6) ZCDx to OUTx − 180 − ns OUTPUT ISINK OUTx Sink Current (Note 6) VOUTx = VDD/2; CLOAD = 0.1 /C0109F − 2.0 − A ISOURCE OUTx Source Current (Note 6) VOUTx = VDD/2; CLOAD = 0.1 /C0109F − 1.0 − A tRISE Rise Time CLOAD = 1 nF, 10% to 90% − 10 25 ns tFALL Fall Time CLOAD = 1 nF, 90% to 10% − 5 20 ns VO_UVLO Output Voltage During UVLO VDD = 5 V; IOUT = 100 /C0109A − − 1 V IRVS Reverse Current Withstand (Note 6) − 500 − mA SOFT−START (CSS = 0.1 /C0109F) ISS_MAX Maximum Soft−Start Current VCOMP < 3.0 V −7 −5 −3 /C0109A ISS_MIN Minimum Soft−Start Current (Note 6) VCOMP > 4.5 V −0.40 −0.25 −0.10 /C0109A INPUT BROWNOUT PROTECTION VIN_BO Input Brownout Threshold 0.76 0.925 1.10 V IVINSNK VIN Sink Current VVIN > 1.1 V −0.2 − 0.2 /C0109A VVIN < 0.8 V 1.4 2 2.5 /C0109A INPUT−VOLTAGE FEEDFORWARD RANGE VFF_UL VIN Feedforward Upper Limit (Note 6) 3.1 3.7 4.3 V VFF_RATIO VFF_UL / VIN_BO (Note 6) 3.6 4.0 4.3 PHASE MANAGEMENT VPH,DROP Phase Dropping Threshold VCOMP Decreasing, Transition from 2 to

1 Phase, TA = 25°C

0.66 0.73 0.80 V VPH,ADD Phase Adding Threshold VCOMP Increasing, Transition from 1 to

2 Phase, TA = 25°C

0.86 0.93 1.00 V OVER−VOLTAGE PROTECTION USING FB PIN – CYCLE−BY−CYCLE (Input) VOVPNL Non−Latching OVP Threshold (+8% above VOUT_NOMINAL) TA = 25°C DRV1 = DRV2 = 0 V 3.15 3.25 3.35 V VOVPNL_HYS OVP Hysteresis FB Decreasing − 0.24 − V OVER−VOLTAGE PROTECTION USING OVP PIN – LATCHING (Input) VOVPLCH Latching OVP Threshold (+15%) DRV1 = DRV2 = 0 V 3.36 3.50 3.65 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Not tested in production.

www.onsemi.com unavoidable in converters utilizing the open−loop soft− start scheme. This method is especially dangerous in power−factor− corrector applications because the error amplifier’s bandwidth is typically limited to a very low crossover frequency. The slow response of the amplifier can cause considerable overshoot at the output. FAN9611 employs closed−loop soft−start where the reference voltage of the error amplifier is slowly increased to its final value. When the current and power limits of the converter are properly taken into consideration, the output voltage of the converter follows the reference voltage. This ensures that the error amplifier stays in regulation during soft start and the output voltage overshoot can be eliminated.

Each ZCD pin is internally clamped close to 0 V (GND). conduction time of the rectifier diode. Figure 16. Zero−Current Detect Circuit

5 V Bias Rail (5VB)

5 V rail is turned on, providing a sharp edge that can be used

Figure 17. 5 V Bias Figure 18. Maximum On−Time Control (MOT) the PCB (right under the IC).

pins to filter the high peak currents of the gate driver circuits. 4.7 /C0109F to ensure proper operation. as low as 0.5 /C0109A minimum. from the FB pin and defeating the closed−loop soft−start. the SS voltage to the FB pin, this problem can be mitigated. soft−start capacitor remains 0.5 V above the FB voltage. Figure 19. Soft−Start Programming

4.3 V , the maximum on−time limit terminates the

conduction of the boost switches.

0.73 V and returns to two−phase operation when the error

Figure 20. Error Amplifier Compensation Circuitry

3 V , which is the reference used at the non−inverting input

when the FB voltage returns to its nominal 3 V level. Figure 21. Output−Voltage Feedback Circuit to program the secondary OVP. protection (set at ~15%), which is latched. based on the feedback voltage (at the FB pin). pin should be grounded (Option 3). Figure 22. Secondary Over−Voltage Protection Circuit

3.7 V , the FAN9611 input voltage sense circuit saturates and

for any VIN voltage above 3.7 V . Figure 23. Input Voltage Sensing Circuit synchronized to the zero crossing of the line waveform. input−voltage feedforward circuit.

pin description for important bypass information. thresholds at the CS1 and CS2 pins are approximately 0.2 V. leading−edge current spike are integrated in the IC. Figure 26. Current−Sense Protection Circuits

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APPLICATION INFORMATION

Synchronization and Timing Functions The FAN9611 employs a sophisticated synchronization sub−system. At the heart of the system is a dual−channel switching−frequency detector that measures the switching period of each channel in every switching cycle and locks their operating phase 180 degrees out of phase from each other. The slower operating frequency channel is dominant, but there is no master−slave arrangement. Moreover, as the frequency constantly changes due to the varying input voltage, either channel can be the slower dominant channel. As opposed to the most common technique, where the phase relationship between the channels is provided by changing the on−time of one of the MOSFETs, the FAN9611 controls the phase relationship by inserting a turn−on delay before the next switching period starts for the faster running phase. As shown in the literature [1], the on−time modulation technique is not stable under all operating conditions, while the off−time modulation (or delaying the turn−on) is unconditionally stable under all operating conditions. Restart Timer and Dead−Phase Detect Protection The restart timer is an integral part of the Sync−Lock synchronizing circuit. It ensures exact 180−degree out−of−phase operation in restart timer operation. This is an important safety feature. In the case of a non−operating phase due to no ZCD detection, missing gate drive connection (for example no gate resistor), one of the power components failing in an open circuit, or similar errors, the other phase is locked into restart timer operation, preventing it from trying to deliver full power to the load. This is called the dead−phase detect protection. The restart timer is set to approximately 16.5 kHz, just above the audible frequency range, to avoid any acoustic noise generation. Frequency Clamp Just as the restart timer, the frequency clamp is integrated into the synchronization and ensures exact 180−degree out−of−phase operation when the operating frequency is limited. This might occur at very light−load operation or near the zero crossing region of the line voltage waveform. Limiting the switching frequency at light load can improve efficiency, but has a negative effect on power factor since the converter also enters true DCM operation. The frequency clamp is set to approximately 525 kHz. Adjusting the Output Voltage with Load Some applications, the output voltage of the PFC boost converter is decreased at low power levels to boost the light load efficiency of the power supply. Implementing this function with a circuit external to the FAN9611 is straightforward because the error amplifier reference (the positive input) is available on the soft−start (SS) pin, as shown in Figure 27. In the FAN9611 architecture, the power of the converter is proportional to the voltage on the COMP pin, minus a small offset. The voltage on the COMP pin is monitored to determine the operating power of the supply. Therefore the voltage on the SS pin can be adjusted lower to achieve the desired lower output voltage. Several possible implementations to adjust the output voltage of the boost stage at light load are described in the application note AN−8021 . It includes the universal output voltage adjust implementation which is modulated by input voltage to avoid the boost converter becoming a peak rectifier at high line and light load. Figure 27. FAN9611 Error Amplifier Configuration adjusting the maximum on time.

www.onsemi.com d. Pull the VIN Pin to GND. Since the VIN sense circuit is configured to ride through a single line cycle dropout test without shutting down the power supply, this method results in a delayed shutdown of the converter. The FAN9611 stops operation approximately 20 ms to 32 ms after the VIN pin is pulled LOW. The delay depends on the phase of the line cycle at which the pull−down occurs. This method triggers the input brownout protection (input under−voltage lockout), which gradually discharges the compensation capacitor. As the output voltage decreases, the FB pin falls, pulling LOW the SS capacitor voltage. Similarly to the shutdown, once the VIN pin is released, operation resumes after several milliseconds of delay needed to determine that the input voltage is above the turn−on threshold. At least one line cycle peak must be detected above the turn−on threshold before operation can resume at the following line voltage zero−crossing. The converter starts following normal soft−start procedure. Layout and Connection Guidelines For high−power applications, two or more PCB layers are recommended to effectively use the ground pattern to minimize the switching noise interference. The FAN9611 incorporates fast−reacting input circuits, short propagation delays, and strong output stages capable of delivering current peaks over 1.5 A to facilitate fast voltage transition times. Many high−speed power circuits can be susceptible to noise injected from their own output or external sources, possibly causing output re−triggering. These effects can be especially obvious if the circuit is tested in breadboard or non−optimal circuit layouts with long input or output leads. The following guidelines are recommended for all layout designs, but especially strongly for the single−layer PCB designs. (For example of a 1−layer PCB design, see the Application Note AN−6086 General

• Keep high−current output and power ground paths separate from analog input signals and signal ground paths.
• For best results, make connections to all pins as short and direct as possible. Power Ground and Analog Ground
• Power ground (PGND) and analog ground (AGND) should meet at one point only.
• All the control components should be connected to AGND without sharing the trace with PGND.
• The return path for the gate drive current and V DD capacitor should be connected to the PGND pin.
• Minimize the ground loops between the driver outputs (DRV1, DRV2), MOSFETs, and PGND.
• Adding the by−pass capacitor for noise on the VDD pin is recommended. It should be connected as close to the pin as possible. Gate Drive
• The gate drive pattern should be wide enough to handle 1 A peak current.
• Keep the controller as close to the MOSFETs as possible. This minimizes the length and the loop area (series inductance) of the high−current gate drive traces. The gate drive pattern should be as short as possible to minimize interference. Current Sensing
• Current sensing should be as short as possible.
• To minimize switching noise, current sensing should not make a loop. Input Voltage Sensing (VIN)
• Since the impedance of voltage divider is large and FAN9611 detects the peak of the line voltage, the VIN pin can be sensitive to the switching noise. The trace connected to this pin should not cross traces with high di/dt to minimize the interference.
• The noise bypass capacitor for VIN should be connected as close to the pin as possible.

Figure 32. Interleaved BCM PFC Schematic Using FAN9611 Use the estimated full−load power conversion efficiency. variation to the per−channel power rating.

www.onsemi.com The output capacitance must be calculated by two different methods. The first equation determines the capacitor value based on the allowable ripple voltage at the minimum line frequency. It is important to remember that the scaled version of this ripple is present at the FB pin. The feedback voltage is continuously monitored by the non−latching over voltage protection circuit. Its threshold is about 8% higher the nominal output voltage. To avoid triggering the OVP protection during normal operation, V OUT,RIPPLE should be limited to less 12% of the nominal output voltage, VOUT. The second expression yields the minimum output capacitance based on the required hold−up time based on the power supply specification. Ultimately, the larger of the two values satisfies both design requirements and has to be selected for C OUT. Step 5: Boost Inductance per Channel LLINE,OFF /C0043 /C0104/C0064V2 LINE,OFF /C0064/C0466VOUT /C00422/C0504/C0064VLINE,OFF/C0467 2 /C0064fSW,MIN /C0064VOUT /C0064PMAX,CH (eq. 9) LLINE,MAX /C0043 /C0104/C0064V2 LINE,MAX /C0064/C0466VOUT /C00422/C0504/C0064VLINE,MAX/C0467 2 /C0064fSW,MIN /C0064VOUT /C0064PMAX,CH (eq. 10) The minimum switching frequency can occur either at the lowest or at the highest input line voltage. Accordingly, two boost inductor values are calculated and the lower of the two inductances must be selected. This L value keeps the minimum operating frequency above f SW,MIN under all operating conditions. Step 6: Maximum On−Time per Channel tON,MAX /C0043 2 /C0064L /C0064PMAX,CH /C0104/C0064V2 LINE,OFF (eq. 11) Step 7: Peak Inductor Current per Channel IL,PK /C0043 2/C0504/C0064VLINE,OFF L /C0064tON,MAX (eq. 12) Step 8: Maximum DC Output Current IOUT,MAX /C0043 2 /C0064PMAX,CH VOUT (eq. 13) Step 9: Zero Current Detect Resistors RZCD1 /C0043RZCD2 /C0043 0.5 /C0064VOUT N /C00640.5 mA (eq. 14) where 0.5 · VOUT is the maximum amplitude of the resonant waveform across the boost inductor during zero current detection; N is the turns ratio of the boost inductor and the auxiliary winding utilized for the zero current detection; and 0.5 mA is the maximum current of the ZCD pin during the zero current detection period. Step 10: Maximum On−Time Setting Resistor RMOT /C00434340 /C0064106 /C0064tON,MAX (eq. 15) where RMOT should be between 40 k/C0087 and 130 k/C0087. Step 11: Output Voltage Setting Resistors (Feedback) RFB2 /C0043 3V /C0064VOUT PFB /C0043 IFB (eq. 16) where 3 V is the reference voltage of the error amplifier at its non−inverting input and P FB or IFB are selected by the designer. If the power loss associated to the feedback divider is critical to meet stand−by power consumption regulations, it might be beneficial to start the calculation by choosing PFB. Otherwise, the current of feedback divider, IFB should be set to approximately 0.4 mA at the desired output voltage set point. This value ensures that parasitic circuit board and pin capacitances do not introduce unwanted filtering effect in the feedback path. If the feedback divider is used to provide startup power for the F AN9611 (see AN−6086 for implementation details), the following equation is used to calculate RFB2: RFB2 /C0043 3V /C0064/C04262/C0504/C0064VLINE,ON /C0042(12.5 V /C00413 /C00640.7 V)/C0427 0.12 mA /C0064VOUT (eq. 17) where 3 V is the reference voltage of the error amplifier at its non−inverting input; 12.5 V is the controller’s UVLO turn−on threshold; 0.12 mA is the worst−case startup current required to start operation; and 3 · 0.7 V accounts for the forward voltage drop of three diodes in series of the startup current. Once the value of RFB2 is determined, RFB1 is given by the following formula: RFB1 /C0043/C0466 VOUT /C00421/C0467/C0064RFB2 (eq. 18) RFB1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type. Step 12: Soft−Start Capacitor CSS /C0043 5 /C0109A /C0064COUT /C0064(RFB1 /C0041RFB2) 0.3 /C0064IOUT,MAX /C0064RFB2 (eq. 19) where 5 /C0109A is the charge current of the soft−start capacitor and 0.3 · IOUT,MAX is the maximum output current charging the output capacitor of the converter during the soft−start process. It is imperative to limit the charge current of the output capacitor to be able to maintain closed−loop soft−start of the converter. The 0.3 factor used in the C SS equation can prevent output over voltage at the end of the soft−start period and provides sufficient margin to supply current to the load while the output capacitor is charging.

4.1 V /C0064COUT /C0064(2 /C0064/C0112/C0064f0)2 /C0064

typically in the 5 Hz to 15 Hz range. maximum charge current of the soft−start capacitor. capability of the error amplifier. can be effectively attenuated.

3.5 V /C0064VOUT,LATCH

0.925 V /C0064V2

PINSNS power loss is in the 50 mW to 100 mW range. hysteresis between the turn−on and turn−off thresholds. Figure 33. Recommended Gate Drive Schematic

110 VAC 220 VAC

1. For full performance operational characteristics at both low line (110 VAC) and high line (220 VAC), as well as at no−load and full−load,

refer to FEB388 Evaluation Board User Guide: 400 W Evaluation Board. Figure 57. Ripple−Current Cancellation (110 VAC) Figure 58. Ripple−Current Cancellation (110 V AC) Figure 59. No−Load Startup at 115 VAC Figure 60. Full−Load Startup at 115 VAC Figure 61. Input Voltage Feedforward

400 W 400 V (1 A)

Figure 62. Measured Efficiency at 115 VAC Figure 63. Measured Efficiency at 230 VAC Figure 64. Measured Efficiency at 115 VAC Figure 65. Measured Efficiency at 230 VAC

Table 3. RELATED PRODUCTS

• AN−6086: Design Consideration for Interleaved Boundary Conduction Mode (BCM) PFC Using FAN9611/12
• AN−9717: onsemi Evaluation Board User Guide FEB388: 400 W Evaluation Board using FAN9611/12
• AN−8021: Building Variable Output V oltage Boost PFC Converters Using FAN9611/12
• onsemi 300−W Low Profile Evaluation Board: FEBFAN9611_S01U300A REFERENCES DCM/BCM Boundary Boost PFC Converters”, Proceedings of APEC ’08, pp. 1010−1016. 2. C. Bridge and L. Balogh, “Understanding Interleaved Boundary Conduction Mode PFC Converters”, Fairchild Power Seminars, 2008−2009. MillerDrive is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries.

SOIC−16, 150 mils CASE 751BG ISSUE O DATE 19 DEC 2008 TOP VIEW PIN#1 IDENTIFICATION E D A e b L h c SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. /C0113 SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 9.80 5.80 3.80

1.27 BSC

1.75 0.25 0.51 0.25 0.50 10.00 6.20 4.00 L 0.40 1.27 1.35 9.90 6.00 3.90 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. 98AON34275EDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1SOIC−16, 150 mils © Semiconductor Components Industries, LLC, 2008 www.onsemi.com

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ADDITIONAL INFORMATION TECHNICAL PUBLICATIONS: Technical Library: www.onsemi.com/design/resources/technical−documentation onsemi Website: www.onsemi.com ONLINE SUPPORT: www.onsemi.com/support For additional information, please contact your local Sales Representative at www.onsemi.com/support/sales