FAN9611 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

ƒ Sync-Lock™ Interleaving Technology for 180° Out- of-Phase Synchronization Under All Conditions ƒ Automatic Phase Disable at Light Load ƒ Dead-Phase Detect Protection ƒ 2.0A Sink, 1.0A Source, High-Current Gate Drivers ƒ High Power Factor, Low Total Harmonic Distortion ƒ Voltage-Mode Control with (VIN)2 Feedforward ƒ Closed-Loop Soft-Start with User-Programmable Soft-Start Time for Reduced Overshoot ƒ Minimum Restart Frequency to Avoid Audible Noise ƒ Maximum Switching Frequency Clamp ƒ Brownout Protection with Soft Recovery ƒ Non-Latching OVP on FB Pin and Latching Second- Level Protection on OVP Pin ƒ Open-Feedback Protection ƒ Power-Limit and Current Protection for Each Phase ƒ Low Startup Current of 80µA Typical ƒ Works with DC and 50Hz to 400Hz AC Inputs

Applications

ƒ 100-1000W AC-DC Power Supplies ƒ Large Screen LCD-TV, PDP-TV, RP-TV Power ƒ High-Efficiency Desktop and Server Power Supplies ƒ Networking and Telecom Power Supplies ƒ Solar Micro Inverters

Description

The FAN9611/12 family of interleaved dual Boundary- Conduction-Mode (BCM) Power-Factor-Correction (PFC) controllers operate two parallel-connected boost power trains 180° out of phase. Interleaving extends the maximum practical power level of the control technique from about 300W to greater than 800W. Unlike the continuous conduction mode (CCM) technique often used at higher power levels, BCM offers inherent zero- current switching of the boost diodes, which permits the use of less expensive diodes without sacrificing efficiency. Furthermore, the input and output filters can be smaller due to ripple current cancellation and effective doubling of the switching frequency. The converters operate with variable frequency, which is a function of the load and the instantaneous input / output voltages. The switching frequency is limited between 18kHz and 600kHz. The Pulse Width Modulators (PWM) implement voltage-mode control with input voltage feedforward. When configured for PFC applications, the slow voltage regulation loop results in constant on-time operation within a line cycle. This PWM method, combined with the BCM operation of the boost converters, provides automatic power factor correction. The controllers offers bias UVLO (10V / 7.5V for FAN9611 and 12.5V / 7.5V for FAN9612), input brownout, input over-voltage, over-current, open- feedback, output over-voltage, and redundant latching over-voltage protections. Furthermore, the converters’ output power is limited independently of the input RMS voltage. Synchronization between the power stages is maintained under all operating conditions. ZCD1 ZCD2 Figure 1. Simplified Application Diagram

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 2 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers

Ordering Information

(Preliminary) RoHS 16-Lead, Small Outline Integrated Circuit (SOIC) Tape and Reel 2,500 FAN9612MX RoHS 16-Lead, Small Outline Integrated Circuit (SOIC) Tape and Reel 2,500 Notes: For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. This device passed wave soldering test by JESD22A-111. Package Outlines ZCD2 5VB VDD CS1ZCD1 MOT 8 9 AGND SS COMP FB DRV2 PGND VIN OVP DRV1 CS2 Figure 2. SOIC-16 (Top View)

  1. Typical ΘJL is specified from semiconductor junction to lead.
  2. Typical ΘJA is dependent on the PCB design and operating conditions , such as air flow. The range of values

covers a variety of operating conditions utilizing natural convection with no heatsink on the package.

  1. This typical range is an estimate; actual values depend on the application.

Figure 5. Pin Layout (Top-View) 1 ZCD1 Zero Current Detector for Phase 1 of the interleaved boost power stage. 2 ZCD2 Zero Current Detector for Phase 2 of the interleaved boost power stage. 3 5VB 5V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC. 4 MOT Maximum On-Time adjust for the individual power stages. 5 AGND Analog Ground. Reference potential for all setup signals. 6 SS Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier.

7 COMP Compensation Network connection to the output of the gM error amplifier

8 FB Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier. 9 OVP Output Voltage monitor for the independent, second-level, latched OVP protection. 10 VIN Input Voltage monitor for brownout protection and input voltage feedforward. 11 PGND Power Ground connection. 12 DRV2 Gate Drive Output for Phase 2 of the interleaved boost power stage. 13 DRV1 Gate Drive Output for Phase 1 of the interleaved boost power stage. 14 VDD External Bias Supply for the IC. 15 CS2 Current Sense Input for Phase 2 of the interleaved boost power stage. 16 CS1 Current Sense Input for Phase 1 of the interleaved boost power stage.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 5 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD Supply Voltage to AGND & PGND -0.3 20.0 V VBIAS 5VB Voltage to AGND & PGND -0.3 5.5 V Voltage On Input Pins to AGND (Except FB Pin) -0.3 V BIAS + 0.3 V Voltage On FB Pin (Current Limited) -0.3 V DD + 0.8 V Voltage On Output Pins to PGND (DRV1, DRV2) -0.3 V DD + 0.3 V IOH, IOL Gate Drive Peak Output Current (Transient) 2.5 A Gate Drive Output Current (DC) 0.05 A TL Lead Soldering Temperature (10 Seconds) +260 ºC TJ Junction Temperature -40 +150 ºC TSTG Storage Temperature -65 +150 ºC ESD Electrostatic Discharge Protection Level Human Body Model, JEDEC JESD22-A114 2 kV Charged Device Model, JEDEC JESD22-C101 1 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage Range 9 12 18 V VINS Signal Input Voltage 0 5 V ISNK Output Current Sinking (DRV1, DRV2) 1.5 2.0 A ISRC Output Current Sourcing (DRV1, DRV2) 0.8 1.0 A LMISMATCH Boost Inductor Mismatch Note: While the recommended maximum inductor mismatch is ±10% for optimal current sharing and ripple-current cancellation, there is no absolute maximum limit. If the mismatch is greater than ±10%, current sharing is proportionately worse requiring over-design of the power supply. However, the accurate 180° out-of-phase synchronization is still maintained providing current cancellation although its effectiveness is reduced. ±5% ±10% TA Operating Ambient Temperature -40 +125 ºC

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 6 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers

Electrical Characteristics

Unless otherwise noted, V DD = 12V, T J = -40°C to +125°C. Currents are def ined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply ISTARTUP Startup Supply Current V DD = VON – 0.2V 80 110 µA IDD Operating Current Output Not Switching 3.7 5.2 mA IDD_DYM Dynamic Operating Current (4) f SW = 50kHz; CLOAD = 2nF 4 6 mA VON UVLO Start Threshold, FAN9611 VDD Increasing 9.5 10.0 10.5 V UVLO Start Threshold, FAN9612 12.0 12.5 13.0 V VOFF UVLO Stop Threshold Voltage V DD Decreasing 7.0 7.5 8.0 V VHYS UVLO Hysteresis, FAN9611 VON – VOFF 2.5 V UVLO Hysteresis, FAN9612 5.0 V Bias Regulator (C5VB = 0.1µF) V5VB 5VB Output Voltage TA = 25°C; ILOAD = 1mA 5.0 V Total Variation Over Line, Load, and Temperature 4.8 5.2 IOUT_MAX Maximum Output Current 5.0 mA Error Amplifier VEA Voltage Reference TA = 25°C 2.95 3.00 3.05 V Total Variation Over Line, Load, and Temperature 2.91 3.075 IBIAS Input Bias Current VFB = 1V to 3V; |VSS – VFB| ≤ 0.1V –0.2 0.2 µA IOUT_SRC Output Source Current V SS = 3V; VFB = 2.9V -13.7 -8 -4 µA IOUT_SINK Output Sink Current V SS = 3V; VFB = 3.1V 4 8 12 µA VOH Output High Voltage 4.5 4.7 V5VB V VOL Output Low Voltage I SINK < 100µA 0.0 0.1 0.2 V gM Transconductance 50 78 115 µmh o PWM VRAMP,OFST PWM Ramp Offset T A = 25°C 120 195 270 mV tON,MIN Minimum On-Time V FB > VSS 0 µs Maximum On-Time VMOT Maximum On-Time Voltage R = 125kΩ 1.16 1.23 1.30 V tON,MAX Maximum On-Time R = 125kΩ; VVIN = 2.5V; VCOMP > 4.5V; TA = 25°C 3.4 5.0 6.6 µs Restart Timer (Each Channel) fSW,MIN Minimum Switching Frequency V FB > VPWM_OFFSET 15.5 18.5 23.0 kHz Frequency Clamp (Each Channel) fSW,MAX Maximum Switching Frequency 520 605 750 kHz Continued on the following page…

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 7 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers Electrical Characteristics (Continued) Unless otherwise noted, V DD = 12V, T J = -40°C to +125°C. Currents are def ined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Current Sense VCS CS Input Threshold Voltage Limit 0.19 0.21 0.23 V ICS CS Input Current V CSX = 0V to 1V –0.2 0.2 µA tCS_DELAY CS to Output Delay CS Stepped from 0V to 5V 85 100 ns Zero Current Detection VZCD_IN Input Voltage Threshold (4) –0.1 0 0.1 V VZCD_H Input High Clamp Voltage I ZCD = 0.5mA 0.8 1.0 1.2 V VZCD_L Input Low Clamp Voltage I ZCD = –0.5mA –0.7 –0.5 –0.3 V IZCD_SRC Source Current Capability (4) 1 mA IZCD_SNK Sink Current Capability (4) 10 mA tZCD_DLY Turn-On Delay (4) ZCDx to OUTx 180 ns Output ISINK OUTx Sink Current, Mid-Voltage (4) V OUTx = VDD/2; CLOAD = 0.1µF 2.0 A ISOURCE OUTx Source Current, Mid- Voltage(4) VOUTx = VDD/2; CLOAD = 0.1µF 1.0 A tRISE Rise Time C LOAD = 1nF, 10% to 90% 10 25 ns tFALL Fall Time C LOAD = 1nF, 90% to 10% 5 20 ns VO_UVLO Output Voltage During UVLO V DD = 5V; IOUT = 100µA 1 V IRVS Reverse Current Withstand (4) 500 mA Soft-Start (CSS = 0.1µF) ISS_MAX Maximum Soft-Start Current V COMP < 3.0V –8 –5 –2 µA ISS_MIN Minimum Soft-Start Current V COMP > 4.5V –0.62 –0.20 –0.05 µA Input Protection VIN_BO Input Brownout Threshold 0.76 0.95 1.10 V VIN_OVP Input OVP Threshold 3.1 3.7 4.3 V VIN_RATIO OVP Threshold / BO Threshold 3.6 4.0 4.3 IVINSNK VIN Sink Current VVIN > 1.1V –0.2 0.2 µA VVIN < 0.8V 1.4 2 2.5 µA Phase Management VPH,DROP Phase Dropping Threshold VCOMP Decreasing, Transition from Dual to Single Phase 0.660 0.740 0.825 V VPH,ADD Phase Adding Threshold VCOMP Increasing, Transition from Single to Dual Phase 0.84 0.92 1.00 V Over-Voltage Protection Using FB Pin – Cycle-by-Cycle (Input) VOVPNL Non-Latching OVP Threshold (+8% above VOUT_NOMINAL) TA = 25°C DRV1=DRV2=0V 3.15 3.25 3.35 V VOVPNL_HYS OVP Hysteresis FB Decreasing 0.24 V Over-Voltage Protection Using OVP Pin – Latching (Input) VOVPLCH Latching OVP Threshold (+15%) DRV1=DRV2=0V 3.36 3.50 3.65 V Note: 4. Not tested in production.

  1. Analog Ground (AGND) and Power Ground

low-impedance trace on the PCB (right under the IC). be connected between the VDD pin and the PGND pin. actively controlling the output voltage during startup. is almost zero and the output voltage can not be raised. the non-inverting input of the error amplifier. Figure 19. Soft-Start Programming

  1. Error Amplifier Compensation (COMP)

terminates the conduction of the boost switches. phase operation when the error voltage exceeds 0.96V. 18.5% of the maximum power capability of the design.

  1. Input Voltage Sensing (V IN)

detector works properly during light-load operation. declared and the FAN9611/12 stops operating. FAN9611/12 stops switching due to input over voltage. Figure 23. Input Voltage Sensing Circuit synchronized to the zero crossing of the line waveform. the input voltage sensing method of the controller.

important bypass information.

  1. Current-Sense Protection (CS1, CS2)

current spike are integrated in the IC. Figure 26. Current-Sense Protection Circuits

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 18 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers

Application Information

  1. Synchronization and Timing Functions The FAN9611/12 employs a sophisticated synchronization sub-system. At the heart of the system is a dual-channel switching-frequency detector that measures the switching period of each channel in every switching cycle and locks their operating phase 180 degrees out of phase from each other. The slower operating frequency channel is dominant, but there is no master-slave arrangement. Moreover, as the frequency constantly changes due to the varying input voltage, either channel can be the slower dominant channel. As opposed to the most common technique, where the phase relationship between the channels is provided by changing the on-time of one of the MOSFETs, the FAN9611/12 controls the phase relationship by inserting a turn-on delay before the next switching period starts for the faster running phase. As shown in the literature [1], the on-time modulation technique is not stable under all operating conditions, while the off-time modulation (or delaying the turn-on) is unconditionally stable under all operating conditions. a. Restart Timer and Dead-Phase Detect Protection The restart timer is an integral part of the Sync-Lock™ synchronizing circuit. It ens ures exact 180-degree out- of-phase operation in restart timer operation. This is an important safety feature. In the case of a non-operating phase due to no ZCD detection, missing gate drive connection (for example no gate resistor), one of the power components failing in an open circuit, or similar errors, the other phase is locked into restart timer operation, preventing it from trying to deliver full power to the load. This is called the dead-phase detect protection. The restart timer is set to approximately 18kHz, just above the audible frequency range, to avoid any acoustic noise generation. b. Frequency Clamp Just as the restart timer, the frequency clamp is integrated into the synchronization and ensures exact 180-degree out-of-phase operation when the operating frequency is limited. This might occur at very light-load operation or near the zero crossing region of the line voltage waveform. Limiting the switching frequency at light load can improve efficiency, but has a negative effect on power factor since the converter also enters true DCM operation. The frequency clamp is set to approximately 600kHz. 2. Adjusting the Output Voltage with Load In some applications, the output voltage of the PFC boost converter is decreased at low power levels to boost the light load efficiency of the power supply. Implementing this function with a circuit external to the FAN9611/12 is straightforward because the error amplifier reference (the positive input) is available on the soft-start (SS) pin, as shown in Figure 27. In the FAN9611/12 architecture, the power of the converter is proportional to the voltage on the COMP pin, minus a small offset. The voltage on the COMP pin is monitored to determine the operating power of the supply. Therefore the voltage on the SS pin can be adjusted lower to achieve the desired lower output voltage. Several possible implementations to adjust the output voltage of the boost stage at light load are described in the application note AN-8021. It includes the universal output voltage adjust implementation which is modulated by input voltage to avoid the boost converter becoming a peak rectifier at high line and light load.

Figure 27. FAN9611/12 Error Amplifier Configuration

  1. Adjusting the Output Voltage with Input

therefore of the overall power supply.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 20 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers c. Pulling the COMP Pin to GND . When the COMP pin is pulled below the PWM ramp offset, approximately 0.195V, the FAN9611/12 stops sending gate drive pulses to the power MOSFETs. This condition is similar to pulse skipping under no- load condition. If any load is still present at the output of the boost PFC stage, the output voltage decreases. Consequently, t he FB pin decreases and the SS capacitor voltage is pulled LOW by the internal clamp between the FB and SS pins. At that point, the operation and eventual recovery to normal operation is similar to the mechanism described above. If the COMP pin is held LOW for long enough to pull the SS pin LOW, the recovery follows normal soft-start procedure when the COMP pin is released. If the SS capacitor is not pulled LOW as a result of a momentary pull-down of the COMP pin, the recovery is still soft due to the fact that a limited current source is charging the compensation capacitors at the output of the error amplifier. Nevertheless, in this case, output voltage overshoot can occur before the voltage loop enters closed-loop operation and resumes controlling the output voltage again. d. Pull the VIN Pin to GND . Since the VIN sense circuit is configured to ride through a single line cycle dropout test without shutting down the power supply, this method results in a delayed shutdown of the converter. The FAN9611/12 stops operation approximately 20ms to 32ms after the VIN pin is pulled LOW. The delay depends on the phase of the line cycle at which the pull-down occurs. This method triggers the input brownout protection (input under-voltage lockout), which gradually discharges the compensat ion capacitor. As the output voltage decreases, the FB pin falls, pulling LOW the SS capacitor voltage. Similarly to the shutdown, once the VIN pin is released, operation resumes after several milliseconds of delay needed to determine that the input voltage is above the turn-on threshold. At least one line cycle peak must be detected above the turn-on threshold before operation can resume at the following line voltage zero-crossing. The converter starts following normal soft-start procedure. 6. Layout and Connection Guidelines For high-power applications, two or more PCB layers are recommended to effectively use the ground pattern to minimize the switching noise interference. The FAN9611/12 incorporates fast-reacting input circuits, short propagation delays, and strong output stages capable of delivering current peaks over 1.5A to facilitate fast voltage transition times. Many high-speed power circuits can be susceptible to noise injected from their own output or external sources, possibly causing output re-triggering. These effects can be especially obvious if the circuit is tested in breadboard or non- optimal circuit layouts with long input or output leads. The following guidelines are recommended for all layout designs, but especially strongly for the single-layer PCB designs. (For example of a 1-layer PCB design, see the Application Note AN-6086.) General ƒ Keep high-current output and power ground paths separate from analog input signals and signal ground paths. ƒ For best results, make connections to all pins as short and direct as possible. Power Ground and Analog Ground ƒ Power ground (PGND) and analog ground (AGND) should meet at one point only. ƒ All the control components should be connected to AGND without sharing the trace with PGND. ƒ The return path for the gate drive current and VDD capacitor should be connected to the PGND pin. ƒ Minimize the ground loops between the driver outputs (DRV1, DRV2), MOSFETs, and PGND. ƒ Adding the by-pass capacitor for noise on the VDD pin is recommended. It should be connected as close to the pin as possible. Gate Drive ƒ The gate drive pattern should be wide enough to handle 1A peak current. ƒ Keep the controller as close to the MOSFETs as possible. This minimizes the length and the loop area (series inductance) of the high-current gate drive traces. The gate drive pattern should be as short as possible to minimize interference. Current Sensing ƒ Current sensing should be as short as possible. ƒ To minimize switching noise, current sensing should not make a loop. Input Voltage Sensing (VIN) ƒ Since the impedance of voltage divider is large and FAN9611/12 detects the peak of the line voltage, the VIN pin can be sensitive to the switching noise. The trace connected to this pin should not cross traces with high di/dt to minimize the interference. ƒ The noise bypass capacitor for VIN should be connected as close to the pin as possible.

and explained in Application Note AN-6086. the power supply specification must be known. their values determine the component selections. other two thresholds, as demonstrated in Figure 30. Figure 30. Simplified Turn-on and Turn-off

1 ZCD1

2 ZCD2

35 V B

Figure 31. Interleaved BCM PFC Schematic Using FAN9611/12 Use the estimated full-load power conversion efficiency. unless a more accurate power budget is available.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 23 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers Step 4: Output Capacitance OUT,RIPPLEOUTLINE,MIN OUT )OUT(RIPPLE VVf4 PC ⋅⋅⋅= (6) OUT,MIN OUT,RIPPLE OUT HOLDOUT OUT(HOLD) VV tP2C −⎟⎟ ⎛ − ⋅⋅= (7) The output capacitance must be calculated by two different methods. The first equation determines the capacitor value based on the allowable ripple voltage at the minimum line frequency. It is important to remember that the scaled version of this ripple is present at the FB pin. The feedback voltage is continuously monitored by the non-latching over voltage protection circuit. Its threshold is about 8% higher the nominal output voltage. To avoid triggering the OVP protection during normal operation, V OUT,RIPPLE should be limited to less 12% of the nominal output voltage, VOUT. The second expression yields the minimum output capacitance based on the r equired hold-up time based on the power supply specification. Ultimately, the larger of the two values satisfies both design requirements and has to be selected for C OUT. Step 5: Boost Inductance per Channel ( ) CHMAX,OUTMINSW, OFFLINE,OUT OFFLINE, OFFLINE, PVf2 V2VVηL ⋅⋅⋅ ⋅−⋅⋅= (8) ( ) CHMAX,OUTSW,MIN LINE,MAXOUT LINE,MAX LINE,MAX PVf2 V2VVηL ⋅⋅⋅ ⋅−⋅⋅= (9) The minimum switching frequency can occur either at the lowest or at the highest input line voltage. Accordingly, two boost induc tor values are calculated and the lower of the two inductances must be selected. This L value keeps the minimum operating frequency above f SW,MIN under all operating conditions. Step 6: Maximum On-Time per Channel OFFLINE, CHMAX, MAXON, Vη PL2t ⋅⋅= (10) Step 7: Peak Inductor Current per Channel ON,MAX OFFLINE, L,PK tL V2I ⋅⋅= (11) Step 8: Maximum DC Output Current OUT CHMAX, OUT,MAX V P2I ⋅= (12) Step 9: Zero Current Detect Resistors 0.5mAN V0.5RR OUT ZCD2ZCD1 ⋅ ⋅== (13) where 0.5 ·VOUT is the maximum amplitude of the resonant waveform across the boost inductor during zero current detection; N is the turns ratio of the boost inductor and the auxiliary winding utilized for the zero current detection; and 0.5mA is the maximum current of the ZCD pin during the zero current detection period. Step 10: Maximum On-Time Setting Resistor MAXON, MOT t104340R ⋅⋅= (14) where RMOT should be between 40kΩ and 130kΩ. Step 11: Output Voltage Setting Resistors (Feedback) FBFB OUT FB2 I P V3VR =⋅= (15) where 3V is the reference voltage of the error amplifier at its non-inverting input and P FB or I FB are selected by the designer. If the power loss associated to the feedback divider is critical to meet stand-by power consumption regulations, it might be beneficial to start the calculation by choosing P FB. Otherwise, the current of feedback divider, I FB should be set to approximately 0.4mA at the desired output voltage set point. This value ensures that paras itic circuit board and pin capacitances do not introduce unwanted filtering effect in the feedback path. If the feedback divider is used to provide startup power for the FAN9611/12 (see AN-6086 for implementation details), the following equation is used to calculate RFB2: ( )[ ] OUT ONLINE, FB2 V0.12mA 0.7V312.5VV23VR ⋅ ⋅+−⋅⋅= (16) where 3V is the reference voltage of the error amplifier at its non-inverting input; 12.5V is the controller’s UVLO turn-on threshold; 0.12mA is the worst-case startup current required to start operation; and 3

  • 0.7V accounts for the forward voltage drop of three diodes in series of the startup current. Once the value of R FB2 is determined, RFB1 is given by the following formula: FB2 OUT FB1 R13V VR ⋅⎟⎟ ⎛ −= (17) RFB1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.0.1 24 FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers Step 12: Soft-Start Capacitor FB2MAXOUT, FB2FB1OUT SS RI0.3 RRCμA5C ⋅⋅ +⋅⋅= (18) where 5 μA is the charge current of the soft-start capacitor and 0.3 ·IOUT,MAX is the maximum output current charging the output capacitor of the converter during the soft-start process. It is imperative to limit the charge current of the output capacitor to be able to maintain closed-loop soft-start of the converter. The 0.3 factor used in the C SS equation can prevent output over voltage at the end of the soft-start period and provides sufficient margin to supply current to the load while the output capacitor is charging. Step 13: Compensation Components () FB2FB1 FB2 0OUT MAXOUT,M LFCOMP, RR R fπ2C4.1V IgC +⋅ ⋅⋅⋅⋅ ⋅= (19) where 4.1V is the control range of the error amplifier and f0 is the desired voltage loop crossover frequency. It is important to consider that the lowest output ripple frequency limits the voltage loop crossover frequency. In PFC applications, that frequency is two times the AC line frequency. Therefore, the voltage loop bandwidth 0), is typically in the 5Hz to 15Hz range. To guarantee closed-loop soft-start operation under all conditions, it is recommended that: SSHFCOMP, C4C ⋅< (20) This relationship is determined by the ratio between the maximum output current of the g M error amplifier to the maximum charge current of the soft-start capacitor. Observing this correlation between the two capacitor values ensures that the compensation capacitor voltage can be adjusted faster than any voltage change taking place across the soft-start capacitor. Therefore, during startup the voltage regulation loop’s response to the increasing soft-start voltage is not limited by the finite current capability of the error amplifier. LFCOMP,0 COMP Cfπ2R ⋅⋅⋅= 1 (21) COMPHFP HFCOMP, Rfπ2C ⋅⋅⋅= 1 (22) where fHFP is the frequency of a pole implemented in the error amplifier compensation network against high- frequency noise in the feedback loop. The pole should be placed at least a decade higher than f 0 to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower then the switching frequency of the converter so noise can be effectively attenuated. The recommended f HFP frequency is around 120Hz in PFC applications. Step 14: Over-Voltage Protection Setting (OVP) OVP LATCHOUT, OV2 P V3.5VR ⋅= (23) where 3.5V is the threshold voltage of the OVP comparator and P OVP is the total dissipation of the resistive divider network. Typical P OVP power loss is in the 50mW to 100mW range. OV2 LATCHOUT, OV1 R13.5V VR ⋅⎟⎟ ⎛ −= (24) ROV1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type. Step 15: Input Line Voltage Sense Resistors INSNS MAXLINE, IN2 P VV.R 73 (25) where 3.7V is the threshold voltage of the line OVP comparator and P INSNS is the total dissipation of the resistive divider network. Typical P INSNS power loss is in the 50mW to 100mW range. IN2 MAXLINE, IN1 R13.7V VR ⋅⎟⎟ −⋅= 2 (26) RIN1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type. μA2 V.0RR RV2 R IN2IN1 IN2ONLINE, INHYST 925 (27) where 0.925V is the threshold voltage of the line under- voltage lockout comparator and 2 μA is the sink current provided at the VIN pin during line under-voltage (brownout) condition. The sink current, together with the terminating impedance of the VIN pin determines the hysteresis between the turn-on and turn-off thresholds.

potential oscillation in the gate drive circuits. Figure 32. Recommended Gate Drive Schematic manufacturing considerations. yields exactly the 1.5 factor used in the calculation.

Table 1. Related Products DCM/BCM Boundary Boost PFC Converters”, Proceedings of APEC ’08, pp. 1010-1016.

  1. C. Bridge and L. Balogh, “Understanding Interl eaved Boundary Conduction Mode PFC Converters”,

Fairchild Power Seminars, 2008-2009.

MS-012, VARIATION AC, ISSUE C. B) ALL DIMENSIONS ARE IN MILLIMETERS. F) DRAWING FILE NAME: M16AREV12.

1.75 MAX

Figure 64. 16-Lead SOIC Package the warranty therein, which covers Fairchild products.

Table 2. Revision History

1.0.0 July 2009 Initial Release of FAN9612

1.0.1 Aug 2009 Preliminary release of FAN 9611 product added to the FAN9612 Released datasheet.