FAN8400D FAIRCHILD | Alldatasheet
Document overview
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- PDF pages: 14
Technical content
Features
- 3-Phase BLDC motor driver IC with speed control
- Phase Locked Loop (PLL) speed control
- Built-in phase locked detector output
- Current linear drive scheme
- External clock for arbitrary motor speed
- Built-in FG amplifier and integrating amplifier
- Auto Gain Control (AGC) circuit for compensation hall amplifier
- Built-in protection circuits (over-current limit, under voltage limit, thermal shut down)
Description
The FAN8400D is a monolithic integrated circuit. it is one driver for laser beam printer (LBP) polygon mirror motor, which has single chip implementation of all circuits. For extremely high rotational precision, it employs the phase locked loop (PLL) speed control scheme. 28-SSOPH-375SG2 Typical application
- Polygon mirror motor drive IC for laser beam printer
- Polygon mirror motor drive IC for facsimile
- Polygon mirror motor drive IC for duplicator
- Polygon mirror motor drive IC for multi function printer
- General 3 phase BLDC motor drive IC
Ordering Information
Device Package Operating Temp FAN8400BD3 28-SSOPH-375SG2 −20°C ~ +80°C FAN8400BD3TF 28-SSOPH-375SG2 −20°C ~ +80°C FAN8400D (FAN8400BD3) 3-Phase BLDC Motor Driver with PLL
FAN8400D (FAN8400BD3) Pin Assignments AGC FIN FIN FGIN- FGS FGOUT S/S NC SGND LD ECLK PD EI EO FC NC VREG VCC PGND RF U V W HV+ HV- HU+ HU- HW+ HW- FAN8400D NC
FAN8400D (FAN8400BD3) Pin Definitions Pin Number Pin Name Pin Function Description
1 AGC AGC amplifier frequency characteristics correction
IN- FG amplifier inverting input 3F G S FG pulse output 4F G OUT FG amplifier output
5 S/S Stop and start
8 SGND Signal ground
9 LD Phase locked loop detector output
10 ECLK External clock
11 PD Phase locked loop detector output
I Error amplifier inverting input
13 E O Error amplifier output
14 F C Control amplifier frequency correction
15 NC -
REG Regulator voltage stabilization output
17 V CC Power supply
18 PGND Power ground
F Output current detection
20 U U output
21 V V output
22 W W output
V+ V hall amplifier non inverting input
24 H V- V hall amplifier inverting input
25 H U+ U hall amplifier non inverting input
26 H U- U hall amplifier inverting input
27 H W+ W hall amplifier non inverting input
28 H W- W hall amplifier inverting input
FAN8400D (FAN8400BD3) Internal Block Diagram AGC FIN FIN FGIN- FGS FGOUT S/S NC SGND LD ECLK PD EI EO FC NC VREG VCC PGND RF U V W HV+ HV- HU+ HU- HW+ HW- VREG VREG Regulator Output Controller Hall AMP Matrix AGC Clock PLL Lock Detector TSD & UVLO S/S OCL V-type Control NC
FAN8400D (FAN8400BD3) Absolute Maximum Ratings (Ta = 25°°°°C) Recommended Operating Conditions (Ta = 25°°°°C) Parameter Symbol Value Unit Remark Maximum supply voltage V CCMAX 30 V - Maximum output current I OMAX 0.6 A - Power dissipation Pd 1.7 W - Operating temperature T OPR −20 ~ +80 °C- Storage temperature T STG −50 ~ +150 °C- Parameter Symbol Min. Typ. Max. Unit Operating voltage range V CC 20 24 28 V
FAN8400D (FAN8400BD3) Electrical Characteristics (Ta = 25°°°°C) Parameter Symbol Conditions Min. Typ. Max. Unit POWER SUPPLY CURRENT Low power supply current I CCL Stop mode, VCC=20V 20 30 40 mA Typical power supply current I CCT Stop mode, VCC=24V 21 31 41 mA High power supply current I CCH Stop mode, VCC=28V 22 32 42 mA OUTPUT POWER TRANSISTOR CHARACTERISTICS (VAGC = 3.5V) U source saturation voltage (1) V SATUU1 IO=0.6A, RF=0Ω -1 . 8 2 . 5 V U source saturation voltage (2) V SATUU2 IO=0.3A, RF=0Ω -1 . 6 2 . 3 V U sink saturation voltage (1) V SATUL1 IO=0.6A, RF=0Ω -0 . 5 1 . 0 V U sink saturation voltage (2) V SATUL2 IO=0.3A, RF=0Ω -0 . 2 5 0 . 7 V V source saturation voltage (1) V SATVU1 IO=0.6A, RF=0Ω -1 . 8 2 . 5 V V source saturation voltage (2) V SATVU2 IO=0.3A, RF=0Ω -1 . 6 2 . 3 V V sink saturation voltage (1) V SATVL1 IO=0.6A, RF=0Ω -0 . 5 1 . 0 V V sink saturation voltage (2) V SATVL2 IO=0.3A, RF=0Ω -0 . 2 5 0 . 7 V W source saturation voltage (1) V SATWU1 IO=0.6A, RF=0Ω -1 . 8 2 . 5 V W source saturation voltage (2) V SATWU2 IO=0.3A, RF=0Ω -1 . 6 2 . 3 V W sink saturation voltage (1) V SATWL1 IO=0.6A, RF=0Ω -0 . 5 1 . 0 V W sink saturation voltage (2) V SATWL2 IO=0.3A, RF=0Ω -0 . 2 5 0 . 7 V U output leakage current I OLEAKU VCC=28V, U=28V - - 100 µA V output leakage current I OLEAKV VCC=28V, V=28V - - 100 µA W output leakage current I OLEAKW VCC=28V, W=28V - - 100 µA UNDER VOLTAGE LIMIT UVLO operating voltage V SD - 7.0 7.6 8.2 V UVLO hysteresis HV SD - 1.0 1.3 1.6 V REGULATOR VOLTAGE OUTPUT Regulator output voltage V REG - 5.8 6.3 6.8 V Power supply variation H VREG1 VCC=20~28V - - 100 mV Load variation H VREG2 ILOAD=0~10mA - - 100 mV HALL AMPLIFIER INPUT BLOCK HU+ hall AMP input bias current I BHA1+ -- 2 1 0 µA HU− hall AMP input bias current I BHA1− -- 2 1 0 µA HV+ hall AMP input bias current I BHA2+ -- 2 1 0 µA HV− hall AMP input bias current I BHA2− -- 2 1 0 µA HW+ hall AMP input bias current I BHA3+ -- 2 1 0 µA HW− hall AMP input bias current I BHA3− -- 2 1 0 µA Hall differential input range V HIN Sine wave input 50 - 350 mVp-p Hall common input range V ICM Differential input : 50mVp-p 3.5 - V CC-3.5 V
FAN8400D (FAN8400BD3) Electrical Characteristics (Continued) Parameter Symbol Conditions Min. Typ. Max. Unit FG AMPLIFIER BLOCK FG AMP. input bias current I BFG -- 1 - 1 µA FG AMP. DC bias level V BFG - 2.90 3.15 3.40 V FG output high level voltage V OHFG No external load V REG-1.1V - - V FG output low level voltage V OLFG No external load - 0.8 1.2 V FG SCHMIDT COMPARATOR BLOCK FGS high / low input hysteresis V SHL -- 5 0 0 5 0 m V FGS low / high input hysteresis V SLH - 100 150 200 mV FGS hysteresis V FGL - 100 - 200 mV FGS input operating level V FGSIL - 400 - - mVp-p FGS output saturation voltage V FGSSAT IFGS=4mA - 0.2 0.4 V FGS output leakage current I FGSLEAK VCC=28V - - 10 µA ERROR AMPLIFIER BLOCK Error AMP. input bias current I BER -- 1 - 1 µA Error AMP. DC bias level V BER - 2.90 3.15 3.40 V Error output high level voltage V OHER No external load V REG-1.1V - - V Error output low level voltage V OLER No external load - - 1.0 V CURRENT LIMIT OPERATION RF output voltage limit V RF - 0.55 0.60 0.65 V CONTROLLER BLOCK Dead zone V DZ - 50 100 300 mV Output idle voltage V ID -- - 5 m V Forward gain G DF+ -0 . 4 0 . 5 0 . 6 - Reverse gain G DF− - -0.6 -0.5 -0.4 - Accelerate command voltage V STA -V REG-1.1V - - V Decelerate command voltage V STO -- 0 . 8 1 . 5 V Forward limit voltage V L+ RF=22Ω -0 . 6 0 -V Reverse limit voltage V L− RF=22Ω -0 . 6 0 -V PHASE COMPARATOR OUTPUT BLOCK PD output high level voltage V PDH No external load 5.2 - - V PD output low level voltage V PDL No external load - - 0.7 V PD output source current I PD+ VPD=0.5*VREG -- - 0 . 6 m A PD output sink current I PD− VPD=0.5*VREG 1.0 - - mA PHASE LOCKED LOOP DETECTOR OUTPUT BLOCK LD output saturation voltage V LDSAT ILD=5mA - 0.1 0.4 V LD output leakage current I LDLEAK VCC=28V - - 10 µA
FAN8400D (FAN8400BD3) Electrical Characteristics (Continued) Parameter Symbol Conditions Min. Typ. Max. Unit EXTERNAL CLOCK INPUT BLOCK External input frequency F CLK External clock mode 0.5 - 7.0 KHz ECLK input open voltage V IOCLK - 3.7 4.2 4.7 V ECLK input high level current I IHCLK VCLK=VREG 100 150 200 µA ECLK input low level current I ILCLK VCLK=0V -400 -300 -200 µA S/S BLOCK S/S input high level voltage V IHSS -3 . 0 - V REG V S/S input low level voltage V ILSS -0 - 1 . 5 V S/S hysteresis V ISSS - 0.3 0.5 0.7 V S/S input open voltage VIOSS - 3.7 4.2 4.7 V S/S input high level current I IHSS VSS=VREG 100 150 200 µA S/S input low level current I ILSS VSS=0V -400 -300 -200 µA
FAN8400D (FAN8400BD3)
Application Information
- Output Block
- 3 Phase power transistor and free wheeling diodes
- Reverse active type upper side diodes and parasitic lower side diodes
- full wave current linear drive with current feedback
- Connection with external capacitor to prevent voltage spike and oscillation by current drive
- Output transistor commutation by "Winner takes all" method
- Built in over current limit (OCL) circuit 2. Hall AMP Block
- Detection of rotor position using 3 phase hall sensors
- Determination of output commutation by hall signal 3. AGC Block
- This block is remained output amplitude.
- It is controlled by envelope through hall signals.NOTES: VAGC is voltage of AGC output. HNI is hall non inverting input voltage. HI is hall inverting voltage. 4. Speed Control Block
- Digital phase locked loop (PLL) circuit
- Generating error pulse between rising edge of clock and falling edge of FG signal.
- High precision stable speed control Hall U Hall V Hall W Forward torque [ Reverse torque] Output U Output V Output W H L H L [H] H [L] M [M] H L L L [H] M [M] H [L] H H L M [M] L [M] H [L] L H L H [L] L [H] M [M] L H H H [L] M [M] L [H] L L H M [M] H [L] L [H] VAGC
FAN8400D (FAN8400BD3) 5. FG AMP & FG Schmidt Comparator Block
- This block measures of motor rotation speed and controls motor speed.
- It is determined FG AMP gain and filter by external component.
- FG schmidt block change sine wave form to square wave form 6. Error AMP Block
- It composes of dumping filter and ripple filter by external component.
- It determines output amplitude of error AMP by width error pulse.
- It is determined output current by output amplitude of error AMP.
- Bidirectional torque control 7. Regulator Block
- Power supply of control circuits in inside.
- Band gap reference circuits. 8. Lock Detector
- It is low when FG frequency reaches capture range of clock frequency.
- Open correct 9. FG Pulse Output
- Monitoring pin for motor rotative speed
- Open correct 10. Stop And Start
- Stop mode: Open or high voltage
- Start mode: Low voltage VDZ Reverse Direction Forward Direction VRF VEOVREG/2
FAN8400D (FAN8400BD3) Test Circuits 3.5V 0.1u VCC 56K VCC 10K VREG 0.1u HW HU HV 0.1u VCC 10u VCC VCC VCC FAN8400D
FAN8400D (FAN8400BD3) Typical Application Circuits HW HU HV VCC FAN8400D M S/S FGS FG Sensor LD ECLK
FAN8400D (FAN8400BD3)
FAN8400D (FAN8400BD3) 11/7/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.