FAN8060 ONSEMI | Alldatasheet
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© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN8060 • Rev. 1.0.1 FAN8060 — 1.2 MHz, 1 A Synchronous Step-Down DC/DC Regulator FAN8060
1.2 MHz, 1 A Synchronous Step-Down DC/DC
Features
Current Mode Control Over 96% Efficient Selectable Continuous Output Current: 500 mA/1 A 2.5 V to 5.5 V Input Voltage Range Output Voltage as Low as 1.2 V 1.2 MHz Operating Frequency Less than 1 µA Shutdown Current External Synchronization from 500 kHz to 2 MHz 100% Duty Cycle Synchronous Switching FET; no Schottky Diode Required Stable with Ceramic Capacitors Light Load Mode with Pulse Skipping External Compensation External Soft-Start Overload / Short-Circuit Protection Under-Voltage Lockout Thermal Shutdown 10-Lead 3x3 mm Green MLP Package
Applications
PDAs GPS Devices MP3 Players Mini PCI Digital Cameras Peripheral Ports DSP Core USB Devices PCMCIA Cable Modem Data Cards
Description
The FAN8060 is a highly efficient , monolithic, current- mode, step-down synchronous regulator. It can provide 1 A continuous current from 2.5 V to 5.5 V input voltage. The output voltage can be adjusted from 1.2 V up to the input voltage with an external voltage divider. External compensation and soft-start allow for design optimization and flexibility. High-frequency operation allows for all -ceramic solutions and small footprints. In addition, a user-selectable current limit provides protection against output overload and short circuit. FAN8060 features pulse skipping to achieve higher efficiency during light load operation. 100% duty cycle capability enables power solutions to extend the drop out voltage. Provision for external synchronization allows users to minimize input capacitors and manage EMI in solutions . FAN8060 is available in a green, low profile, 10-Lead 3x3 mm MLP package. EN FAN8060SS COMP PVIN AVIN FB PGND SW AGND SYNC COUT LOUT CSS INPUT 2.5 to 5.5V HI LO CC RC CA OUTPUT 1.2V to 5.5V CIN Figure 1. Typical Application Circuit
Ordering Information
Temperature Range Package Packing Method FAN8060EMPX -40 to +85°C 10-Pin, 3x3 mm Molded Leadless Package (MLP) Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Figure 2. Pin Configuration (Top View)
- Connect exposed PAD to AGND
1 EN Enable. Enables operation when pulled to logic HIGH. 2 AVIN Analog Input Voltage. All internal control circuits are connected to this supply. 3 PVIN Power Input Voltage. Power stage supply voltage. 4 SW Switching Node. The drains of both PMOS and NMOS.
6 SYNC
pull-down resistor of 450 KΩ. 7 SS Soft-Start. A capacitor connected between this pin and AGND can set soft -start time. 9 FB Output Voltage Feedback. Connect through a resistor divider to set the output voltage. 10 AGND Analog Ground. Ground return for all internal control circuits.
© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN8060 • Rev. 1.0.1 3 FAN8060 — 1.2 MHz, 1 A Synchronous Step-Down DC/DC Regulator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings ar e stress ratings only. All voltage values, except differential voltages, are given with respect to the network ground terminal. Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Symbols Parameter Min. Max. Unit VPVIN PVIN (AGND=PGND) -0.3 6.0 V VAVIN AVIN (AGND=PGND) -0.3 6.0 V VSW Switch Voltage, SW to GND -0.3 VIN + 0.3 or 6.0 V All other pins except COMP -0.3 6.0 V TSTG Storage Temperature -65 +150 °C TJ Junction Temperature -40 +125 °C ESD Electrostatic Discharge Protection Human Body Model, JESD22-A114 2.0 kV Charged Device Model, JESD22-C101 2.5 Note: 2. COMP pin has an internal clamp to 1.5 V. Recommended Operating Conditions The Recommended Operating Conditions table defines the c onditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VIN Supply Voltage 2.5 5.5 V TA Ambient Operating Temperature -40 +85 °C Thermal Information Symbol Parameter Min. Typ. Max. Units TSTG Storage Temperature -65 +150 °C TL Lead Soldering Temperature, 30 Seconds +300 °C θJA Thermal Resistance: Junction-to-Ambient 49 °C/W θJc Thermal Resistance: Junction-to-Case(3) 8 °C/W PD Total Power Dissipation in the package, TA=25°C(3) 1.3 W Note: 3. Typical thermal resistance when mounted on a four-layer PCB. Actual results are dependent upon mounting method and surface related to the design.
© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN8060 • Rev. 1.0.1 4 FAN8060 — 1.2 MHz, 1 A Synchronous Step-Down DC/DC Regulator
Electrical Characteristics
VIN=5.0 V, VOUT=2.5 V, COUT=10 µF, CIN=10 µF, over operating range, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Basic Operation VIN VIN Operating Voltage AVIN=PVIN 2.5 5.5 V IQ Quiescent Current VEN=5 V, VSS=0 V 250 371 500 µA ISD Shutdown Current VEN=0 V 0.34 0.60 µA VUVLO VIN Under-Voltage Lockout Rising VIN 2.10 2.19 2.25 V VUVLOHYS VIN Under-Voltage Lockout Hysteresis 70 mV VENH Enable High Input Voltage 1.70 2.00 V VENL Enable Low Input Voltage 0.80 1.22 V RONPMOS PMOS On Resistance(4) VIN=5 V 200 mΩ VIN=3.3 V 300 RONNMOS NMOS On Resistance(4) VIN=5 V 200 mΩ VIN=3.3 V 300 ILIM P-Channel Current Limit VFB=0.7 V, VIN=5 V, 100% Duty Cycle VSYNC=0 V 1.2 A VSYNC=VIN 0.6 fOSC Oscillator Frequency TA=25°C 1.105 1.210 1.350 MHz VSYNC SYNC Threshold Rising Edge VIN/2 V fSYNC Synchronization Frequency VSYNC=Square Wave 500 2000 KHz tSYNC Minimum SYNC Pulse Width VSYNC On Time 100 ns IAMP Error Amplifier Sink/Source Current 30 45 60 µA GEA (4) 700 1000 1400 µA/V AVEA (4) 550 V/V GCS Current Sense Gain(4) 3 A/V VREF Reference Voltage for Temperature Co-efficient, see Figure 12 Measured at FB Pin TA=25°C 1.181 1.205 1.229 V IFB FB Bias Current TA=25°C -0.10 -0.06 0 µA ISS Soft-Start Current -5.5 -4.5 -3.5 µA Protections TOTP Over-Temperature Threshold(4) +165 °C THYS Over-Temperature Hysteresis +20 °C Note: 4. Guaranteed by design and characterization; not production tested.
Figure 3. Functional Block Diagram
© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN8060 • Rev. 1.0.1 6 FAN8060 — 1.2 MHz, 1 A Synchronous Step-Down DC/DC Regulator Operation Description The FAN8060 is a step-down converter operating in current-mode PWM architecture with a typical switching frequency of 1.2 MHz. At the beginning of each clock cycle, the P-channel transistor is turned on. The current in the inductor ramps up and is sensed via an internal circuit. The P -channel switch is turned off when the sensed current causes the PWM comparator to trip, which is when the output voltage is in regulation or when the inductor current reaches the current limi t (set internally to 1.2 A, typically). After a minimum dead time to prevent shoot -through current, the N -channel transistor is turned on and the current ramps down. As the clock cycle is completed, the N -channel switch is turned off and the next clock cycle starts. Light Load Operation As the output load reduces , the current in the inductor during off time is s ensed across the low side MOSFET . When the current reverses direction, the low-side MOSFET is turned off and the high-side MOSFET is not turned on until the output is out of regulation. 100% Duty Cycle Operation As the input voltage approaches the output voltage, the controller start s to increase the duty cycle to maintain output regulation until duty cycle reaches 85%. The controller then transitions to a 100% duty cycle mode over several cycles to support the load. When the dropout condition is met , the converter turns the P - channel high side continuously on. In this mode, the output voltage is equal to the input voltage, minus the voltage drop across the P-channel MOSFET. Soft Start When the input voltage on AVIN exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. A capacitor connected to the SS pin and AGND is charged by a 4 μA internal current source, causing the voltage on the capacitor to rise. When this voltage reaches 1.2 V, the output is in regulation. The SS voltage continues to rise to AVIN . The time for the output to reach regulation is given by the following equation: ( )VA nFCmst SS 2.1/4 )()( µ= (1) Output overload and short-circuit protection is active during soft-start. When the part is disabled, SS pin is pulled low internally. Overload & Short-Circuit Protection FAN8060 employs cycle-by-cycle current limiting, which limits current by reducing duty cycle during overload. As the load increases beyond the limit, the output voltage starts to reduce, thereby reducing the FB voltage. When the FB node is half the refer ence voltage and the COMP node has reached maximum value, short-circuit protection is detected. At that time, both the SS pin and the COMP pin are pulled to ground until the inductor current crosses zero. At that point, both SS and COMP are released for the current to ramp up again. This continues until the short-circuit condition is released.
Refer to Figure 1 for reference designators.
1.2 V to VIN by an external resistor divider, given by the
where, VOUT equals the output voltage. operate at a lower switching frequency. 35% of the maximum steady-state load current. Table 1. Recommended Inductors (3.3 µH) the final application and its output ripple requirements. where COUT is the output capacitor. IOUTMAX = Maximum output current. Figure 14. Compensation Network VFB = Feedback threshold voltage (1.2 V).
network connected at the COMP pin to GND. where RC is compensation resistor. instability if not properly compensated. where VFB is reference voltage. crossover frequency provides sufficient phase margin. (CA) to set the pole f P3 at the location of the ESR zero. Table 2. Recommended Feedback and Figure 15. Recommended Schematic (5 VIN to
2.5 VO)
consist of VIN, GND, VOUT, and SW. minimizing ground loops to reduce EMI issues. from the error amplifier input/output pins. Figure 16. Recommended PCB Layout
1.55 3.10 0.23 0.02 2.20 0.55 0.78 2.33 2.00 0.25 2.25 2.00 0.50 0.20 0.05 0.00
0.80 MAX
3.0 3.0 2XTOP VIEW 0.10 C A B 3.10 2.90 1.60 1.50 2.30 2.20 0.38 0.30 0.20 0.45 0.35 0.5 3.10 2.90 2.0 PIN #1 IDENT BOTTOM VIEW LAND PATTERN RECOMMENDATION NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION WEED-5 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009 D. LAND PATTERN DIMENSIONS ARE NOMINAL REFERENCE VALUES ONLY E. DRAWING FILENAME: MKT-MLP10Brev2 D 10 6 1 5 610 1 5 0.10 C 0.08 C 0.10 C
0.10 M C A B
0.05 M C
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