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Technical content
Features
- Qualified to AEC Q100
- Floating channel designed for bootstrap operation fully oper - ational up to 300V.
- Tolerance to negative transient voltage on VS pin
- dv/dt immune.
- Gate drive supply range from 4.5V to 20V
- Under-voltage lockout
- CMOS Schmitt-triggered inputs with pull-down and pull-up
- High side output out of phase with input (Inverted input)
- Reset input
- Internal recharge FET for bootstrap refresh Typical Applications
- Diesel and gasoline injectors/valves
- MOSFET-and IGBT high side driver applications For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
Description
The FAN7085_GF085 is a high-side gate drive IC with reset input and built-in recharge FET. It is designed for high voltage and high speed driving of MOSFET or IGBT, which operates up to 300V. Fairchild's high-voltage process and common-mode noise cancellation technique provide stable operation in the high side driver under high-dV/dt noise circumstances. Logic input is compatible with standard CMOS outputs. The UVLO cir- cuits prevent from malfunction when VCC and VBS are lower than the specified threshold voltage. It is available with space saving SOIC-8 Package. Minimum source and sink current capability of output driver is 250mA and 250mA. Built-in recharge FET to refresh bootstrap circuit is very useful for circuit topology requiring switches on low and high side of load. SOIC-8
Ordering Information
mp. FAN7085M_GF085 SOIC-8 -40 C ~ 125 C FAN7085MX_GF085 SOIC-8 -40 C ~ 125 C X : Tape & Reel type
©2012 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Block Diagrams VCC Under Voltage Reset VCC to GND Logic Pulse Filter Level Shifter ON Level Shifter OFF Delay Under Voltage Reset VB to VS Pulse Filter Flip Flop Brake before make RESET- IN- GND VS HO VB Recharge Path Pin Assignments 4 5 8VCC IN- GND RESET- VS NC HO VB Pin Definitions Pin Number Pin Name I/O Pin Function Description
1 VCC P Driver supply voltage, typically 5V
2 IN- I Driver control signal input (Negative Logic)
3 GND P Ground
4 RESET- I Driver enable input signal (Negative Logic)
5 VS P High side floating offset for MOSFET Source connection
6 NC - No connection (No Bond wire)
7 HO A High side drive output for MOSFET Gate connection
8 VB P Driver output stage supply
©2012 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are abso- lute voltages referenced to GND. Parameter Symbol Min. Max. Unit High side floating supply voltage VBS -0.3 25 V High side driver output stage voltage Neg. transient: 0.5 ms, external MOSFET off VB -5 325 V High side floating supply offset voltage Neg. transient 0.2 us Vs -25 300 V High side floating output voltage VHO VS-0.3 VB+0.3 V Supply voltage VCC -0.3 25 V Input voltage for IN- VIN -0.3 Vcc+0.3 V Input voltage for RESET- VRES -0.3 Vcc+0.3 V Power Dissipation 1) Pd 0.625 W Thermal resistance, junction to ambient 1) Rthja 200 C/W Electrostatic discharge voltage (Human Body Model) VESD 1.5K V Charge device model VCDM 500 V Junction Temperature Tj 150 C Storage Temperature TS -55 150 C Note: 1) The thermal resistance and power dissipation rating are measured bellow conditions; JESD51-2: Integrated Circuit Thermal Test Method Envir onmental Conditions - Natural condition(StillAir) JESD51-3: Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Package Recommended Operating Conditions For proper operation the device should be used within the recommended conditions Parameter Symbol Min. Max. Unit High side floating supply voltage(DC) Transient:-10V@ 0.2 us VB VS+4.5 VS+20 V High side floating supply offset voltage(DC) @VBS=7V VS -3 300 V High side floating supply of fset voltage(Transient) 0.2us @VBS<25V VS -25 300 V High side floating output voltage VHO Vs VB V Allowable offset voltage Slew Rate 1) dv/dt - 50 V/ns Supply voltage for logic part VCC 4.5 20 V Input voltage for IN- VIN 0 Vcc V Input voltage for RESET- VRESET 0 Vcc V Switching frequency 2) Fs 200K Hz Minimum low input width 3) tIN(low,min) 1000 - ns Minimum high input width 3) tIN(high,min) 60 - ns Minimum operating voltage of VB related to GND VB(MIN)4) 4 - V Ambient temperature Ta -40 125 C Note: 1) Guaranteed by design. 2) Duty = 0.5, VBS >=7V 3) Guaranteed by design. Pulse widths below the specified values, may be ignored. Output will either follow the input sig nal or will ignore it. No false output state is guaranteed when minimum input width is smaller than tin 4) Guaranteed by design
©2012 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Statics Electrical Characteristics Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50, CL = 2.5nF. Parameter Symbol Conditions Min. Typ. Max. Unit VCC and VBS Supply Characteristics VCC and VBS supply under voltage positive going threshold VCCUV+ VBSUV+ Vcc and VBS rising from 0V - 3.7 4.3 V VCC and VBS supply under voltage negative going threshold VCCUV- VBSUV- Vcc and VBS dropping from 5V 2.8 3.4 - V VCC and VBS under voltage hysteresis VCCUVH VBSUVH - 0.02 0.3 - V Under voltage lockout response time tduvcc tduvbs VCC: 6.5V->2.4V or 2.4V->6.5V VBS: 6.5V->2.4V or 2.4V->6.5V 0.5 0.5 us us Offset supply leakage current I LK VB=VS=300V - - 200 uA Quiescent Vcc supply current IQCC Vcc=20V - - 500 uA Quiescent VBS supply current IQBS1 Static mode, VBS=7V, VIN=0 or 5V 100 uA Quiescent VBS supply current IQBS2 Static mode, VBS=16V, VIN=0 or 5V 200 uA VBS drop due to output turn-on (Design guaranty) VBS VBS=7V, Cbs=1uF, tdIG-IN =3uS, tTEST=100uS 210 mV Input Characteristics High logic level input voltage for IN- VIH 0.6VCC - - V Low logic level input voltage for IN- VIL - - 0.28VCC V Low logic level input bias current for IN- IIN- VIN=0 5 25 60 uA High logic level input bias current for IN- IIN+ VIN=5V - - 5 uA Full up resistance at IN RIN 83 200 1000 High logic level input voltage for RESET- VRH 0.6Vcc - - V Low logic level input voltage for RESET- VRL 0.28Vcc V High logic level input current for RESET- IRES+ VRESET=5V 5 25 60 uA Low logic level input bias current for RESET- IRES- VRESET=0 5 uA Full down resistance at RESET- RRES 83 200 1000 Output characteristics High level output voltage, VB - VHO VOH IO=0 - - 0.1 V Low level output voltage, VHO-GND VOL IO=0 - - 0.1 V Peak output source current IO+ VIN=5V 250 450 - mA Peak output sink current IO- VIN=0 250 450 - mA Equivalent output resistance ROP 15.5 28 RON 15.5 28 Recharge Characteristics Recharge TR turn-on propagation delay Ton_rech 4 7.9 9.8 us Recharge TR turn-off propagation delay Toff_rech 0.2 0.4 us Recharge TR on-state voltage drop VRECH Is=1mA, VIN=5V @125C 1.2 V Dead Time Characteristics High side turn-off to recharge gate turn-on DTHOFF Vcc=5V, VS=7V 4 7.8 9.8 us Recharge gate turn-off to high side turn-on DTHON Vcc=5V, VS=7V 0.1 0.4 0.7 us Note: The input parameter are referenced to GND. The VO and IO parameters are referenced to GND.
©2012 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Dynamic Electrical Characteristics Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50, CL = 2.5nF. Parameter Symbol Conditions Min. Typ. Max. Unit Input-to-output turn-on propagation delay tplh 50% input level to 10% output level, VS = 0V 0.56 1 us Input-to-output turn-off propagation delay tphl 50% input level to 90% output level VS = 0V - 0.15 0.5 us RESET-to-output turn-off propagation delay tphl_res 50% input level to 90% output level - 0.17 0.5 us RESET-to-output turn-on propagation delay tplh_res 50% input level to 10% output level - 0.56 1 us Output rising time tr1 Tj=25C - 65 200 ns tr2 - 400 ns tr3 Tj=25C,VBS=16V 65 200 ns tr4 VBS=16V - 400 ns Output falling time tf1 Tj=25C - 25 200 ns tf2 - 300 ns tf3 Tj=25C,VBS=16V 25 200 ns tf4 VBS=16V - 300 ns
©2012 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET
Application Information
- Logic Tables VCC VBS RESET- IN- Ho RechFET < VCCUVLO- X X X OFF ON X X LOW X OFF ON X X X HIGH OFF ON > VCCUVLO+ > VBSUVLO+ HIGH LOW ON OFF > VCCUVLO+ < VBSUVLO- HIGH LOW OFF OFF Notes: X means independent from signal IN-=LOW indicates that the high side NMOS is ON IN-=HIGH indicates that the high side NMOS is OFF RechFET =ON indicates that t he recharge MOSFET is ON RechFET =OFF indicates that the recharge MOSFET is OFF
©2012 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Typical Application Circuit VCC IN- GND RESET- VB HO NC VS R2C2 VCC D1 Up to 300V Load 1. Typical Application Circuit VCC IN- GND RESET- VB HO NC VS C2 C1 From Charge Pump Voltage Source Load GND From LS Driver 2. Application Example
©2012 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Input-Output Waveforms Toff_rech Ton_rech tphl IN- RESET- VS VHO Recharge tplh 10% 90%90% 10% tr tf Figure.1 Input and Output Timing Diagram and Switching Time Waveform Definition 1. Input/Output Timing Diagrams 2. Reset Timing Diagrams tphl_res tplh_res IN- RESET- VHO Figure.2 Reset and Output Timing Diagram
©2012 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET 3.VB Drop Voltage Diagram VBdrop IN- RESET- VB-VS Ig Brake before make VCC IN- GND RESET- VB HO NC VS 50R 2n5 Ig Figure3.a VB Drop Voltage Diagram Figure3.b VB Drop Voltage Test Circuit
©2012 Fairchild Semiconductor Corporation 13 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET Package Dimensions SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 LAND PATTERN RECOMMENDATION SEATING PLANE 0.10 C C GAGE PLANE x 45° DETAIL A SCALE: 2:1 PIN ONE INDICATOR CM BA0.25 B A 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10
1.75 MAX
0.25 0.19 0.36 0.50 0.25R0.10 R0.10 0.90 0.406 (1.04) OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the draw ing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packagin g area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
©2012 Fairchild Semiconductor Corporation 14 www.fairchildsemi.com FAN7085_GF085 Rev. 1.0.1 FAN7085_GF085 High Side Gate Driver with Recharge FET TRADEMARKS The following includes registered and unregistered t rademarks and service marks, owned by Fairchild Semiconductor and/ or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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