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Technical content
Features
- Automotive qualified to AEC Q100
- Floating channel designed for bootstrap operation up to + 600V
- Tolerance to negative transient voltage on VS pin
- Common mode dv/dt noise cancelling circuit.
- Gate drive supply range from 5.5V to 20V
- Under-voltage lockout
- CMOS Schmitt-triggered inputs with pull-down
- High side output in phase with input
- 3.3V, 5V and 15V logic compatible input
- Matched propagation delay for both channels
- Adjustable dead time
- 8-Lead Small Outline Package (SO 8L NB) Typical Applications
- Automotive DC-DC Converters
- Half and full bridge motor control applications For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
Description
The FAN7080_GF085 is a half-bridge gate drive IC with reset input and adjustable dead time control. It is designed for high voltage and high speed driving of MOSFET or IGBT, which operate up to 600V. Fairchild's high-voltage process and com- mon-mode noise cancellation technique pro vide stable opera- tion in the high side driver u nder high-dV/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS=-5V (typical) at VBS=15V. Logic input is compatible with standard CMOS outputs. The UVLO cir- cuits for both channels prevent malfunction when VCC and VBS are lower than the specified threshold voltage. Combined pin function for dead time adjustment and reset shutdown enable this IC to be packaged in a space saving SO 8L NB Package. Minimum source and sink current capability of output driver is 250mA and 500mA respectively, which is suitable for automo- tive DC-DC converters and half and full bridge motor control applications. SO 8L NB
Ordering Information
mp. FAN7080M_GF085 SO 8L NB -40 C ~ 125 C FAN7080MX_GF085 SO 8L NB -40 C ~ 125 C X : Tape & Reel type
©2012 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver Block Diagrams DEADTIME CONTROL DELAY PULSE GENERATOR PULSE FILTER UVLO R R S Q UVLO VCC COM LO VB HO VS IN SD/DT 500kΩ 500kΩ vreg VCC VCC vreg Pin Assignments 4 5 8VCC IN SD/DT COM LO VS HO VB Pin Definitions Pin Number Pin Name I/O Pin Function Description
1 VCC P Driver supply voltage
2 IN I Logic input for high and low side gate drive output
3 SD/DT I Shut down input and dead time setting
4 COM P Ground
5 LO A Low side gate drive output for MOSFET Gate connection
6 VS A High side floating offset for MOSFET Source connection
7 HO A High side drive output for MOSFET Gate connection
8 VB P Driver output stage supply
©2012 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are abso- lute voltages referenced to COM. Parameter Symbol Min. Max. Unit High side floating supply offset voltage VS VB-25 VB+0.3 V High side floating supply voltage VB -0.3 625 V High side floating output voltage VHO Vs-0.3 VB+0.3 V Low side output voltage VLO -0.3 VCC + 0.3 V Supply voltage VCC -0.3 25 V Input voltage for IN VIN -0.3 Vcc+0.3 V Input injection current. Full function, no latch up;( Guaranteed by design). Test at 10V and 17V on Eng.Samples IIN - +1 mA Power Dissipation Pd(1) 0.625 W Thermal resistance, junction to ambient Rthja(1) 200 C/W Electrostatic discharge voltage (Human Body Model) VESD 1K V Charge device model VCDM 500 V Junction Temperature Tj 150 C Storage Temperature TS -55 150 C Note: 1) The thermal resistance and power dissipation rating are measured bellow conditions; JESD51-2: Integrated Circuit Thermal Test Method Envir onmental Conditions - Natural convection(StillAir) JESD51-3 : Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Package Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Parameter Symbol Min. Max. Unit High side floating supply voltage(DC) Transient:-10V@ 0.1 us VB (1) VS + 6 VS + 20 V High side floating supply offset voltage(DC) Transient: -25V(max) @0.1us @VBS<25V VS -5 600 V High side floating output voltage VHO Vs VB V Low side output voltage VLO 0 VCC V Allowable offset voltage Slew Rate (2) dv/dt - 50 V/ns Supply voltage for logic part VCC 5.5 20 V Logic input voltage VIN 0 Vcc V Switching Frequency (3) Fs 200 KHz Ambient Temperature Ta -40 125 C Note: 1) The Vs offset is tested with all supplies biased at 15V differential. 2) Guaranteed by design. 3) When VDT= 1.2V.
©2012 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver Statics Electrical Characteristics Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 15V, VBS = 15V, VS = 0V, CL = 1nF. Parameter Symbol Conditions Min. Typ. Max. Unit Vcc and VBS supply Characteristics VCC and VBS supply under voltage positive going threshold VCCUV+ VBSUV+ - - 4.2 5.5 V VCC and VBS supply under voltage negative going threshold VCCUV- VBSUV- - 2.8 3.6 - V VCC and VBS supply under voltage hysteresis VCCUVH VBSUVH - 0.2 0.6 - V Under voltage lockout response time tduvcc tduvbs VCC: 6V-->2.5V or 2.5V-->6V VBS: 6V-->2.5V or 2.5V-->6V 0.5 0.5 us us Offset supply leakage current I LK VB=VS=600V - 20 50 uA Quiescent VBS supply current IQBS VIN=0 OR 5V, VSDT = 1.2V 20 75 150 uA Quiescent Vcc supply current IQCC VIN=0 OR 5, VSDT = 1.2V - 350 1000 uA Input Characteristics High logic level input voltage VIH 2.7 - - V Low logic level input voltage VIL - - 0.8 V High logic level input bias current for IN IIN+ VIN=5V - 10 50 uA Low logic level input bias current for IN IIN- VIN=0V - 0 2 uA VSDT dead time setting range VDT 1.2 - 5 V VSDT shutdown threshold voltage VSD - 0.8 1.2 V High logic level resistance for SD/DT RSDT VSDT=5V 100 500 1100 K Low logic level input bias current for SD/DT ISDT- VSDT=0V - 1 2 uA Output characteristics High level output voltage, VCC-VHO VOH(HO) IO=0 - - 0.1 V Low level output voltage, VHO VOL(HO) IO=0 - - 0.1 V Output high short circuit pulse current IO+(HO) 250 300 - mA Output low short circuit pulse current IO-(HO) 500 600 - mA Equivalent output resistance ROP(HO) - - 60 RON(HO) - - 30 High level output voltage, VB-VLO VOH(LO) IO=0 - - 0.1 V Low level output voltage, VLO VOL(LO) IO=0 - - 0.1 V Output high short circuit pulse current IO+(LO) 250 - - mA Output low short circuit pulse current IO-(LO) 500 - - mA Equivalent output resistance ROP(LO) - - 60 RON(LO) - - 30
©2012 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver Dynamic Electrical Characteristics Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 15V, VBS = 15V, VS = 0V, CL = 1nF. Parameter Symbol Conditions Min. Typ. Max. Unit Turn-on propagation delay ton VS=0V - 750 1500 ns Turn-off propagation delay toff VS=0V - 130 250 ns Turn -on rising time tr - - 40 150 ns Turn -off falling time tf - - 25 400 ns Dead time, LS turn-off to HS turn-on and HS turn-on to LS turn-off DT VIN=0 or 5V@ VDT=1.2V VIN=0 or 5V@ VDT=3.3V 250 1600 650 2100 1200 2600 ns Dead time matching time MDT DT1 -DT2@ VDT=1.2V DT1 -DT2@ VDT=3.3V - 35 110 300 ns Delay Matching, HS and LS turn-on MTON VDT=1.2V - 25 110 ns Delay Matching, HS and LS turn-off MTOFF VDT=1.2V 15 60 ns Shutdown propagation delay Tsd - 180 330 ns Switching Frequency Fs1 V CC=VBS=20V - - 200 KHz Fs2 VCC=VBS=5.5V - - 200 KHZ
©2012 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver Typical Application Circuit Up to 600V To Load VCC IN SHUTDOWN /DEAD TIME 4 5 VCC IN SD/DT COM LO VS HO VB VDT VDT = Vdd*R2 / (R1+R2). Vdd is output voltage of Microcontroller. The operating range that allows a VDT range of 1.2~3.3V. When pulled lower than VDT [Typ. 0.5V] the device is shutdown. Care must be taken to avoid Voltage spikes below the shutdown threshold on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to be as short as possible. And a capacitor (Typ 0.02uF )between pin3 and COM can prevent this spike. This pin can not be left floating for the same reason.
©2012 Fairchild Semiconductor Corporation 16 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver Package Dimensions Package drawings are provided as a service to customers considering Fairchil d components. Drawings may change in any manner without notice. Please note the revision and/or date on the draw ing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 LAND PATTERN RECOMMENDATION SEATING PLANE 0.10 C C GAGE PLANE x 45° DETAIL A SCALE: 2:1 PIN ONE INDICATOR CM BA0.25 B A 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10
1.75 MAX
0.25 0.19 0.36 0.50 0.25R0.10 R0.10 0.90 0.406 (1.04) OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE
©2012 Fairchild Semiconductor Corporation 17 www.fairchildsemi.com FAN7080_GF085 Rev. 1.0.1 FAN7080_GF085 Half Bridge Gate Driver TRADEMARKS The following includes registered and unregistered t rademarks and service marks, owned by Fairchild Semiconductor and/ or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I43