DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
Features
Integrated PFC and Flyback Controller Critical-Mode PFC Controller Zero-Current Detection for PFC Stage Quasi-Resonant Operation for PWM Stage Internal Minimum 5µs tOFF for QR PWM Stage Internal 5ms Soft-Start for PWM Brownout Protection High / Low Line Over-Power Compensation Auto-Recovery Over-Current Protection Auto-Recovery Open-Loop Protection Externally Auto-Recovery Triggering (RT Pin) Adjustable Over-Temperature Protection VDD Pin and Output Voltage OVP (Auto-Recovery) Internal Over-Temperature Shutdown (140°C)
Applications
AC/DC NB Adapters Open-Frame SMPS Battery Charger
Description
The highly integrated FAN6920MR combines Power Factor Correction (PFC) cont roller and quasi-resonant PWM controller. Integratio n provides cost-effective design and reduces external components. For PFC, FAN6920MR uses a controlled on-time technique to provide a regulated DC output voltage and to perform natural power-fac tor correction. With an innovative THD optimizer, FAN6920MR can reduce input current distortion at zero-crossing duration to improve THD performance. For PWM, FAN6920MR provides several functions to enhance the power system performance: valley detection, green-mode operation, and high / low line over-power compensation. Pr otection functions include secondary-side open-loop and over-current with auto- recovery protection; external auto-recovery triggering; adjustable over-temperature pr otection by RT pin; and external NTC resistor, internal over-temperature shutdown, V DD pin OVP, and DET pin over-voltage for output OVP, and brown-in / out for AC input voltage UVP. The FAN6920MR controller is available in a 16-pin small-outline package (SOP).
Ordering Information
Part Number OLP Mode Operating Temperature Range Package Packing Method FAN6920MRMY Recovery -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel
Figure 1. Typical Application Circuit
Figure 2. Functional Block Diagram
Figure 3. Marking Diagram Figure 4. Pin Configuration
1 RANGE
sets to high impedance if input voltage is at a high level.
2 COMP
3 INV
PWM startup. Once the FAN6920MR is turned on and VINV exceeds in 2.3V, PWM starts.
4 CSPFC
threshold (0.82V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.
5 CSPWM
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 5 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Pin Definitions (Continued) Pin # Name Description 6 OPFC Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5V. 7 VDD Power supply. The threshold voltages for startup and turn-off are 12V and 7V, respectively. The startup current is less than 30µA and the operating current is lower than 10mA. 8 OPWM Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 17.5V. 9 GND The power ground and signal ground.
10 DET
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following purposes: Producing an offset voltage to compensate the th reshold voltage of PWM current limit for over- power compensation. The offset is generated in accordance with the input voltage when the PWM switch is on. Detecting the valley voltage signal of drain volt age of the PWM switch to achieve the valley voltage switching and minimize the switching loss on the PWM switch. Providing output over-voltage protection. A volt age comparator is built in to the DET pin. The DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output over voltage and this flat voltage are higher than 2.5V, the controller stops all PFC and PWM switching operation. The protection mode is auto-recovery. 11 FB Feedback voltage pin used to receive the output voltage level signal to determine PWM gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, overload protection and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2V for more than 50ms.The input impedance of this pin is a 5kΩequivalent resistance. A 1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB comparator. 12 RT Adjustable over-temperature protection and external protection triggering. A constant current flows out from the RT pin. When RT pin voltage is lower than 0.8V (typical), protection is activated and stops PFC and PWM switching operation. This protection is auto-recovery.
13 VIN
Line-voltage detection for brownin / out protections. This pin can receive the AC input voltage level through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s status, but it can also perform brownin / out protection for AC input voltage UVP.
14 ZCD
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle. When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and the controller stops PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired.
15 NC No connection
16 HV High-voltage startup pin is connected to the AC line voltage through a resistor (100kΩtypical) for providing a high charging current to VDD capacitor.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 6 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VHV HV 500 V VH OPFC, OPWM -0.3 25.0 V VL Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT) -0.3 7.0 V VZCD Input Voltage to ZCD Pin -0.3 12.0 V PD Power Dissipation 800 mW θJA Thermal Resistance (Junction-to-Air) 104 °C/W θJC Thermal Resistance (Junction-to-Case) 41 °C/W TJ Operating Junction Temperature -40 +150 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C ESD Human Body Model, JESD22-A114 (All Pins Except HV Pin)(3) 4500 V Charged Device Model, JESD22-C101 (All Pins Except HV Pin)(3) 1250 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltag es, are given with respect to the GND pin. 3. All pins including HV pin: CDM=750V, HBM 1000V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit TA Operating Ambient Tem perature -40 +105 °C
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 7 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller
Electrical Characteristics
VDD=15V, TA=-40°C~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VOP Continuously Operating Voltage 25 V VDD-ON Turn-On Threshold Voltage 10.5 12.0 13.5 V VDD-PWM-OFF PWM Off Threshold Voltage 6 7 8 V VDD-OFF Turn-Off Threshold Voltage 4 5 6 V IDD-ST Startup Current VDD = VDD-ON - 0.16V, Gate Open 20 30 µA IDD-OP Operating Current VDD = 15V, OPFC, OPWM = 100kHz, CL-PFC, CL-PWM = 2nF 10 mA IDD-GREEN Green-Mode Operating Supply Current (Average) VDD = 15V, OPWM = 450Hz, CL-PWM = 2nF 5.5 mA IDD-PWM-OFF Operating Current at PWM-Off Phase VDD = VDD-PWM-OFF - 0.5V 70 120 170 µA VDD-OVP VDD Over-Voltage Protection (Auto-Recovery) 26.5 27.5 28.5 V tVDD-OVP V DD OVP Debounce Time 100 150 200 µs HV Startup Current Source Section IHV Supply Current Drawn from HV Pin VAC = 90V (VDC = 120V), VDD = 0V 1.3 mA HV = 500V, VDD = VDD-OFF +1V 1.0 µA VIN and RANGE Section VVIN-UVP Threshold Voltage for AC Input Under-Voltage Protection 0.95 1.00 1.05 V VVIN-RE-UVP Under-Voltage Protection Reset Voltage VVIN-UVP +0.15V VVIN-UVP +0.20V VVIN-UVP +0.25V V tVIN-UVP Under-Voltage Protection Debounce Time 70 100 130 ms VVIN-RANGE-H High VVIN Threshold for RANGE Comparator 2.40 2.45 2.50 V VVIN-RANGE-L Low VVIN Threshold for RANGE Comparator 2.20 2.25 2.30 V tRANGE Range-Enable / Disable Debounce Time 60 90 120 ms VRANGE-OL Output Low Voltage of RANGE Pin I O = 1mA 0.5 V IRANGE-OH Output High Leakage Current of RANGE Pin RANGE = 5V 50 nA tON-MAX-PFC PFC Maximum On Time RMOT = 24k 22 25 28 µs Continued on the following page…
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 8 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units PFC STAGE Voltage Error Amplifier Section Gm Transconductance (4) 100 125 150 µmho VREF Feedback Comparator Reference Voltage 2.465 2.500 2.535 V VINV-H Clamp High Feedback Voltage RANGE = Open 2.70 2.75 2.80 V RANGE = Ground 2.60 2.65 2.70 VRATIO Clamp High Output Voltage Ratio(4) VINV-H / VREF, RANGE = Open 1.06 1.14 V/V VINV-H / VREF, RANGE = Ground 1.04 1.08 VINV-L Clamp Low Feedback Voltage 2.25 2.35 2.45 V VINV-OVP Over-Voltage Protection for INV Input RANGE = Open 2.90 2.95 V RANGE = Ground 2.75 2.80 tINV-OVP Over-Voltage Protection Debounce Time 50 70 90 µs VINV-UVP Under-Voltage Protection for INV Input 0.35 0.45 0.55 V VINV-PWMON PWM ON Threshold Voltage on INV Pin 2.2 2.3 2.4 V VHYST-PWMON Hysteresis for PWM ON Threshold Voltage on INV Pin VINV- PWMON -1.6 VINV- PWMON -1.5 VINV- PWMON -1.4 V tINV-UVP Under-Voltage Protection Debounce Time 50 70 90 µs VINV-BO PWM and PFC Off Threshold for Brownout Protection 1.15 1.20 1.25 V VCOMP-BO Limited Voltage on COMP Pin for Brownout Protection 1.55 1.60 1.65 V ICOMP-BURST Internal Bias Current for PFC Burst Mode 120 150 180 µA VCOMP-H Comparator Output High Voltage 4.80 5.20 V Comparator Output High Voltage at PFC Burst Mode VFB = 1.3V, VVIN = 2V 1.80 1.90 2.00 VCOMP-L Comparator Output Low Voltage at PFC Burst Mode RANGE = Open, VFB = 1.3V 0.9 1.0 1.1 V VOZ Zero Duty Cycle Voltage on COMP Pin 1.10 1.25 1.40 V ICOMP Comparator Output Source Current VINV = 2.3V, VCOMP = 1.5V 15 30 45 µA VINV = 1.5V 0.50 0.75 1.00 mA Comparator Output Sink Current RANGE = Open, VINV = 2.75V, VCOMP = 5V 20 30 40 µA RANGE = Ground, VINV = 2.65V, VCOMP = 5V 20 30 40 Continued on the following page…
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 9 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units PFC Current-Sense Section VCSPFC Threshold Voltage for Peak Current Cycle-by-Cycle Limit VCOMP = 5V 0.77 0.82 0.87 V tPD Propagation Delay 110 200 ns tBNK Leading-Edge Blanking Time 110 180 250 ns AV CSPFC Compensation Ratio for THD 0.90 0.95 1.00 V/V PFC Output Section VZ PFC Gate Output Clamping Voltage VDD = 25V 14.0 15.5 17.0 V VOL PFC Gate Output Voltage Low V DD = 15V, IO = 100mA 1.5 V VOH PFC Gate Output Voltage High V DD = 15V, IO = 100mA 8 V tR PFC Gate Output Rising Time VDD = 12V, CL = 3nF, 20~80% 30 65 100 ns tF PFC Gate Output Falling Time VDD = 12V, CL = 3nF, 80~20% 30 50 70 ns PFC Zero-Current Detection Section VZCD Input Threshold Voltage Rising Edge VZCD Increasing 1.9 2.1 2.3 V VZCD-HYST Threshold Voltage Hysteresis V ZCD Decreasing 0.25 0.35 0.45 V VZCD-HIGH Upper Clamp Voltage I ZCD = 3mA 8 10 V VZCD-LOW Lower Clamp Voltage 0.35 0.45 0.55 V VZCD-SSC Starting Source Current Threshold Voltage 0.70 0.90 1.10 V tDELAY Maximum Delay from ZCD to Output Turn-On VCOMP = 5V, fS = 60kHz 100 200 ns tRESTART-PFC Restart Time 300 500 700 µs tINHIB Inhibit Time (Maximum Switching Frequency Limit) VCOMP = 5V 1.5 2.5 3.5 µs VZCD-DIS PFC Enable / Disable Function Threshold Voltage 0.15 0.20 0.25 V tZCD-DIS PFC Enable / Disable Function Debounce Time VZCD = 100mV 100 150 200 µs Continued on the following page…
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 10 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units PWM STAGE Feedback Input Section AV Input-Voltage to Current Sense Attenuation(4) AV = VCS /VFB , ZFB Input Impedance(4) VFB > VG 3 5 7 k Ω IOZ Bias Current V FB = VOZ 1.2 2.0 mA VOZ Zero Duty Cycle Input Voltage 0.7 0.9 1.1 V VFB-OLP Open-Loop Protection Threshold Voltage 3.9 4.2 4.5 V tFB-OLP The Debounce Time for Open- Loop Protection 40 50 60 ms tFB-SS Internal Soft-Start Time (4) V FB = 0V~3.6V 4 5 6 ms DET Pin OVP and Valley Detection Section VDET-OVP Comparator Reference Voltage 2.45 2.50 2.55 V Av Open-Loop Gain (4) 60 dB BW Gain Bandwidth (4) 1 MHz tDET-OVP Output OVP (Auto-Recovery) Debounce Time 100 150 200 µs IDET-SOURCE Maximum Source Current V DET = 0V 1 mA VDET-LOW Lower Clamp Voltage I DET = 1mA 0.15 0.25 0.35 V tVALLEY-DELAY Delay Time from Valley Signal Detected to Output Turn-On(4) 150 200 250 ns tOFF-BNK Leading-Edge Blanking Time for DET-OVP (2.5V) and Valley Signal when PWM MOS Turns Off (4) 2.5 µs tTIME-OUT Time-Out After t OFF-MIN (4) 8 9 10 µs PWM Oscillator Section tON-MAX-PWM Maximum On-Time 38 45 52 µs tOFF-MIN Minimum Off-Time VFB ≧ VN, TA = 25°C 5 µs VFB = VG 20.5 VN Beginning of Green-On Mode at FB Voltage Level 1.95 2.10 2.25 V VG Beginning of Green-Off Mode at FB Voltage Level 1.00 1.15 1.30 V ΔVG Hysteresis for Beginning of Green-Off Mode at FB Voltage Level(4) 0.1 V Continued on the following page…
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 11 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40°C~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VCTRL-PFC-BM Threshold Voltage on FB Pin for PFC Burst Mode RANGE Pin Internally Open 1.65 1.70 1.75 V RANGE Pin Internally Ground 1.60 1.65 1.70 VCTRL-PFC-ON Threshold Voltage on FB Pin for PFC Normal Operating 1.75 1.80 1.85 V tPFC-BM Debounce Time for PFC Burst Mode PFC Normal Operating Burst Mode 100 ms tPFC-ON Debounce Time for PFC Recovery to Normal Operating PFC Burst Mode Normal Operating 200 µs tSTARTER-PWM Start Timer (Time-Out Timer) VFB ＜ VG, TA = 25°C 1.85 2.25 2.65 ms VFB ＞ VFB-OLP, TA = 25°C 22 28 34 µs PWM Output Section VCLAMP PWM Gate Output Clamping Voltage VDD = 25V 16.0 17.5 19.0 V VOL PWM Gate Output Voltage Low V DD = 15V, IO = 100mA 1.5 V VOH PWM Gate Output Voltage High V DD = 15V, IO = 100mA 8 V tR PWM Gate Output Rising Time CL = 3nF, VDD = 12V, 20~80% 80 110 ns tF PWM Gate Output Falling Time CL = 3nF, VDD = 12V, 20~80% 40 70 ns Current Sense Section tPD Delay to Output 150 200 ns VLIMIT Limit Voltage on CSPWM Pin for Over-Power Compensation IDET ＜ 75µA, TA = 25°C 0.81 0.84 0.87 V IDET = 185µA, TA = 25°C 0.69 0.72 0.75 IDET = 350µA, TA = 25°C 0.55 0.58 0.61 IDET = 550µA, TA = 25°C 0.37 0.40 0.43 VSLOPE Slope Compensation (4) tON = 45µs, RANGE = Open 0.25 0.30 0.35 V tON = 0µs 0.05 0.10 0.15 tON-BNK Leading-Edge Blanking Time 300 ns VCS-FLOATING CSPWM Pin Floating VCSPWM Clamped High Voltage CSPWM Pin Floating 4.5 5.0 V tCS-H Delay Time, CS Pin Floating CSPWM Pin Floating 150 µs Continued on the following page…
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 12 FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40°C~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units RT Pin Over-Temperature Protection Section TOTP Internal Threshold Temperature for OTP(4) 125 140 155 °C TOTP-HYST Hysteresis Temperature for Internal OTP(4) 30 °C IRT Internal Source Current of RT Pin 90 100 110 µA VRT-AR Protection Triggering Volt age 0.75 0.80 0.85 V VRT-OTP-LEVEL Threshold Voltage for Two-Level Debounce Time 0.45 0.50 0.55 V tRT-OTP-H Debounce Time for OTP 10 ms tRT-OTP-L Debounce Time for Externally Triggering VRT < VRT-OTP-LEVEL 70 110 150 µs Note: 4. Guaranteed by design.
Figure 48. 16-Pin Small Outline Package (SOIC) warranty therein, which covers Fairchild products.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6920MR • Rev. 1.0.3 24 FAN6920MR — Integrated Critical Mode PFC and Quasi-Resonant Current Mode PWM Controller