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Technical content
Features
High-Voltage Startup Low Operating Current: 2.7mA Adaptive Decreasing PWM Frequency to 22KHz Built-in Full-Range Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 65KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Internal Auto-Recovery Open-Loop Protection GATE Output Maximum Voltage Clamp: 18V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP), Auto Recovery / Latch for Option Internal Auto-Recovery Sense Short-Circuit Protection for Option Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis Built-in 5ms Soft-Start Function Built-in LATCH Pin Pull HIGH (> 5.2V) Latch Function
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS
Description
The highly integrated FAN6753 PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power c onsumption, a proprietary adaptive green-mode functi on provides frequency modulation at light-load condi tions. To avoid acoustic- noise problems, the minimum PWM frequency is set above 22KHz. This green-m ode function enables the power supply to meet inter national power conservation requirements. With the in ternal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further r educe power consumption, FAN6753 is manufactured usi ng the BiCMOS process, which allows an operating current of only 2.7mA. FAN6753 integrates a full-range frequency-hopping function internally that hel ps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak- current-mode control. The pr oprietary internal line compensation ensures constant output power limit over a wide AC input voltage range, from 90V AC to 264VAC. FAN6753 provides many protection functions. In addition to cycle-by-cycle curr ent limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until V DD drops below the UVLO lower limit, when the controller starts up again. As long as V DD exceeds ~26V, the internal OVP circuit is triggered. Available in the 8-pin SOP package.
Ordering Information
Temperature Range Package Packing Method FAN6753MY -40C to +105C 8-Lead, Small Outline Package Tape & Reel
Figure 1. Top Mark Figure 2. Pin Configuration (Top View)
1 LATCH
voltage on this pin is 1V (under VLATCHth=5.2V). determined in response to the signal on this pin and the current-sense signal on the SENSE pin. 5 GATE The totem-pole output driver. Soft-driv ing waveform is implemented for improved EMI. 8 HV For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6753 • Rev. 1.0.3 4 FAN6753 — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage (1, 2) 30 V VFB FB Pin Input Voltage -0.3 7.0 V VSENSE SENSE Pin Input Voltage -0.3 7.0 V VLATCH LATCH Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA＜50°C) 400 mW JA Thermal Resistance (Junction-to-Air) 141 C/W TJ Operating Junction Temperature -40 +125 C TSTG Storage Temperature Range -55 +150 C TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 C ESD Electrostatic Discharge Capability Human Body Model, JEDEC:JESD22-A114 5500 V Charged Device Model, JEDEC:JESD22-C101 1500 Notes: 1. All voltage values, except diffe rential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximu m Ratings may cause permanent damage to the device
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6753 • Rev. 1.0.3 5 FAN6753 — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VOP Continuously Operating Voltage 22 V VDD-ON Start Threshold Vo ltage 14.5 15.5 16.5 V VDD-OFF Minimum Operating Vo ltage 8.5 9.5 10.5 V IDD-ST Startup Current V DD-ON – 0.16V 30 µA IDD-OP Operating Supply Current V DD=15V, GATE Open 2.7 3.7 mA IDD-OLP Internal Sink Current VTH-OLP+0.1V 30 60 90 µA VTH-OLP I DD-OLP Off Voltage 6.5 7.5 8.0 V VDD-OVP V DD Over-Voltage Protection 25 26 27 V tD-VDDOVP V DD Over-Voltage Protection Debounce Time 75 125 200 µs HV Section IHV Supply Current Drawn from HV Pin VAC=90V (VDC=120V), VDD=0V 2.0 3.5 5.0 mA IHV-LC Leakage Current after Startup HV=500V, VDD=VDD-OFF+1V 1 20 µA Oscillator Section fOSC Frequency in Nominal Mode Center Frequency 62 65 68 KHz Hopping Range ±3.7 ±4.2 ±4.7 tH-OP Hopping Period 4.4 ms fOSC-G Green-Mode Frequency 18 22 26 KHz fDV Frequency Variation vs. V DD Deviation V DD=11V to 22V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-20 to 85C 5 % Continued on the following page… Figure 5. V
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6753 • Rev. 1.0.3 6 FAN6753 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) VDD=15V and TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units LATCH Section VLATCHth Latch-Off Threshold Voltage VLATCHth > 5.2V, after 100µs Latch Off 5.0 5.3 5.6 V tD-LATCH Latch-Off De-bounce Time VLATCH< VLATCHth 40 100 160 µs ILATCH Output Current from LATCH Pin 92 100 108 µA Feedback Input Section AV Input Voltage to Current-Sense A ttenuation 1/4.5 1/4.0 1/3.5 V/V ZFB Input Impedance 4 7 k Ω VFB-OPEN Output High Voltage FB Pin Open 5.0 5.3 5.6 V VFB-OLP FB Open-Loop Trigger Level 4.6 4.8 5.0 V tD-OLP Delay Time of FB Pin Open-Loop Protection 50 56 62 ms VFB-N Green-Mode Entry FB Voltage 2.8 3.0 3.2 V VFB-G Green-Mode Ending FB Vo ltage 2.2 2.4 2.6 V IFB-ZDC Zero Duty-Cycle FB Current 1.5 mA Current-Sense Section ZSENSE Input Impedance 12 K Ω VSTHFL Current Limit Flatten Threshold Voltage Duty>40% 0.87 0.90 0.93 V VSTHVA Current Limit Valley Threshold Voltage VSTHFL–VSTHVA Duty=0% 0.30 0.34 0.38 V tPD Delay to Output 100 200 ns tLEB Leading-Edge Blanking Time 100 140 180 ns tSS Period During Soft-Startup Time Startup Time 4.3 5.0 5.7 ms GATE Section DCYMAX Maximum Duty Cycle 60 65 70 % VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V tr Gate Rising Time V DD=15V, CL=1nF 150 250 350 ns tf Gate Falling Time V DD=15V, CL=1nF 30 50 90 ns IGATE-SOURCE Gate Source Current V DD=15V, GATE=6V 250 mA VGATE-CLAMP Gate Output Clamping Voltage V DD=22V 18 V Over-Temperature Protection Section (OTP) TOTP Protection Junction Temperature (3) +135 °C TRestart Restart Junction Temperature (4) TOTP- 25 °C Notes: 3. When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enab ling the output again and resetting the latch, after over-temperature protection has been activated.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6753 • Rev. 1.0.3 9 FAN6753 — Highly Integrated Green-Mode PWM Controller Functional Description Startup Current For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, R HV, (1N4007 / 100K Ω recommended). Typical startup current drawn from the HV pin is 3.5mA and charges the hold-up capacitor through t he diode and resistor. When the V DD capacitor level reaches V DD-ON, the startup current switches off. At this moment, the V DD capacitor only supplies the FAN6753 before the auxiliary winding of the main transformer prov ides the operating current. For higher than 6KV surge test, R HV of 100KΩ or above is recommended. Operating Current Operating current is around 2.7mA. The low operating current enables better efficiency and reduces the requirement of V DD hold-up capacitance. Green-Mode Operation The proprietary green-mode function provides off-time modulation to reduce the sw itching frequency in light- load and no-load conditions. The on time is limited for better abnormal or brownout protection. V FB, which is derived from the voltage feedba ck loop, is taken as the reference. Once VFB is lower than the threshold voltage, the switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pul se current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and V FB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP=(VFB–0.6)/4, the switch cycle is terminated immediately. V COMP is internally clamped to a variable voltage around 0.9V for output power limit. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense re sistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 15.5V and 9.5V, respectively . During startup, the hold- up capacitor must be char ged to 15.5V through the startup resistor to enable t he IC. The hold-up capacitor continues to supply V DD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 9.5V during startup. This UVLO hysteresis window ensures that the hold-up capacitor is adequate to supply VDD during startup. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. Soft-Start For many applications, it is necessary to minimize the inrush current at star tup. The built-in 5ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Built-in Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub- harmonic oscillation. FAN6753 inserts a synchronized, positive-going ramp at every switching cycle. Constant Output Power Limit When the SENSE voltage across sense resistor R S reaches the threshold volt age, around 0.9V , the output GATE drive is turned off after a small delay, t PD. This delay introduces an additional current proportional to t PD • V IN / L P. Since the delay is nearly constant regardless of the input voltage V IN, higher input voltage results in a larger additi onal current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp si gnal fed to the inverting input of the OCP comparator . This results in a lower current limit at high-line inputs than at low-line inputs. VDD Over-Voltage Protection (OVP) VDD over-voltage protection is built in to prevent damage due to abnormal conditions. If the V DD voltage is over the over-voltage pr otection voltage (V DD-OVP) and lasts for tD-VDDOVP, the PWM pulses are disabled until the V DD voltage drops below the UVL O, then starts again. Over- voltage conditions are usually caused by open feedback loops. External Latch Function (LATCH Pin) The LATCH pin can be used to control the FAN6753 entering latch mode by pulling this pin over 5.2V for 100µs. If floating, the LATCH pin is internally pulled HIGH to 3.5V. It is not recommended to float or short the LATCH pin to GND. This pin also includes a test mode to disable the jitter function. LATCH pin internally sources 100µA, so place a resistor in series to GND. Do not let this voltage exceed 5.2V for the FAN6753 to function normally.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6753 • Rev. 1.0.3 10 FAN6753 — Highly Integrated Green-Mode PWM Controller Functional Description (Continued) Limited Power Control The feedback (FB) voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than t D-OLP, PWM output is turned off. As PWM output is turned off, VDD begins decreasing. When VDD goes below the turn-off threshold (~9.5V), the controller is totally shut down. V DD is charged up to the turn-on threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. Slope compens ation helps alleviate this problem. Good placem ent and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN 6753, and increasing the power MOS gate resistance also improve performance. Over-Temperature Protection (Internal OTP) The built-in temperature-s ensing circuit shuts down PWM output once the juncti on temperature exceeds 135°C. While PWM output is shut down, V DD gradually drops to the UVLO volt age (around 7.5V). Then V DD charges up to the startup threshold voltage of 15.5V through the startup resist or until PWM output is restarted. This “hiccup” mode protection occurs repeatedly as long as the temperature remains above 130°C. The temperature hysteresis window for the OTP circuit is 25°C.
B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
1.75 MAX
Figure 19. 8-Pin Small Outline Package (SOP) specifically the warranty therein, which covers Fairchild products.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6753 • Rev. 1.0.3 12 FAN6753 — Highly Integrated Green-Mode PWM Controller