FAN6747 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
High-Voltage JFET Startup AC-Line Brownout Protection by HV Pin Constant Output Power Limit by HV Pin (Full AC-Line Range) Two-Level Over-Current Protection (OCP) with 220ms Delay Short-Circuit Protection (SCP) with 15ms Delay as Output Short Peak-Current Mode Operation with Cycle-by-Cycle Current Limiting Low Startup Current: 30µA Low Operating Current: 1.7mA Over-Temperature Protection (OTP) with an External Negative-Temperature-Coefficient (NTC) Thermistor PWM Frequency Decreasing at Green-Mode VDD Over-Voltage Protection (OVP) Internal Latch Circuit for OVP, OTP, SCP, and OCP
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters SMPS with Peak-Current Output, such as for Printers, Scanners, Motor Drivers AC/DC NB Adapters Open-Frame SMPS
Description
The highly integrated FAN6747 PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to decrease the switching frequency with load condition. Under zero-load condition, the power supply enters burst mode and burst frequency can be low to save more power. Green-mode function enables the power supply to meet international power conservation requirements. The FAN6747 is especially designed for SMPS with peak-current output. It incorporates a cycle-by-cycle current limiting and two-level Over-Current-Protection (OCP) that can handle peak load with a delay time. Once the current is over the threshold level, it triggers the first counter 15ms and checks if V DD is below 10V; if it is, the PWM latches off for SCP. If V DD is higher than 10V; it keeps counting to 220ms, then the PWM latches off for OCP. FAN6747 also integrates a frequency-hopping function internally to help reduce EMI emission of a power supply with minimum line filters. Built-in proprietary internal synchronized slope compensation achieves constant output power limit over universal AC line range. The gate output is clamped at 14V to protect the external MOSFET from over-voltage damage. Other protection functions include AC-line brownout protection with hysteresis and V DD over-voltage protection. For over-temperature protection, an external NTC thermistor can be applied to sense the ambient temperature. When OCP, OVP, SCP, or OTP is activated, an internal latch circuit latches off the controller. The latch is reset when the V DD supply is removed.
Ordering Information
FAN6747LMY -40 to +105°C Green 8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .15-Inch Narrow Body Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Figure 3. Top Mark Figure 4. Pin Assignments placed between VDD and GND is recommended. connected from this pin to GND. The impedance of the NTC decreases at high temperatures.
6 SENSE
7 VDD
Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin. startup and turn-off are 16.5V and 9V, respectively. The operating current is lower than 2mA.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6747 • Rev. 1.0.1 4 FAN6747 — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VHV Suddenly Input Voltage to HV Pin within 1 Second (Series connect with RHV) 640 V VL Input Voltage to FB, SENSE, RT Pin -0.3 7.0 V PD Power Dissipation (T A<50°C) 400 mW ΘJA Thermal Resistance (Junction-to-Ambient) 141 °C/W TJ Operating Junction Temperature -40 +125 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C ESD Electrostatic Discharge Capability, All Pins Except HV Pin Human Body Model, JESD22-A114 4.50 kV Charge Device Model, JESD22-C101 1.5 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, ar e given with respect to the network ground terminal. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Typ. Max. Unit TA Operating Ambient Temperature -40 +105 °C VHV Input Voltage to HV Pin 500 V RHV HV Startup Resistor 150 200 250 k Ω
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6747 • Rev. 1.0.1 5 FAN6747 — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VOP Continuously Operating Voltage 24 V VDD-ON Turn-On Threshold Voltage 15.5 16.5 17.5 V VDD-OFF PWM Turn-Off Threshold Voltage 8 9 10 V VDD-OLP Threshold Voltage on VDD for HV JFET Turn-On in Protection Condition After Trigger OCP/ SCP/ OVP/ OTP 5.5 6.5 7.5 V VDD-LH Threshold Voltage on VDD Pin for Latch-Off Release Voltage 3.5 4.0 4.5 V VDD-AC Threshold Voltage on VDD Pin for Disable AC Recovery to Avoid Startup Failed VDD-OFF +2.5 VDD-OFF +3.0 VDD-OFF +3.5 V VDD-SCP Threshold Voltage on VDD Pin for Short-Circuit Protection (SCP) VFB > VFBO VDD-OFF +0.5 VDD-OFF +1.0 VDD-OFF +1.5 V ILH Holding Current Under Latch-Off Conduction VDD=5V 80 100 120 μA IDD-ST Startup Current V DD-ON – 0.16V 30 μA IDD-OLP Holding Current at PWM-Off Phase VDD-OLP+0.1V 235 270 305 μA IDD-OP1 Operating Supply Current when PWM Operating VDD=20V, VFB=3V Gate Open 1.7 2.0 mA IDD-OP2 Operating Supply Current when PWM Stop VDD=20V, VFB=3V Gate Open 1.2 1.5 mA VDD-OVP Threshold Voltage on VDD Pin for VDD Over-Voltage Protection (Latch-Off) 24 25 26 V tD-OVP VDD OVP Debounce Time V FB > VFB-N 75 160 245 μs Figure 5. UVLO Specification
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6747 • Rev. 1.0.1 9 FAN6747 — Highly Integrated Green-Mode PWM Controller VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units Current Sense Section tPD Delay to Output 65 200 ns tLEB Leading-Edge Blanking Time 230 270 310 ns Vlimit-L Current Limit at Low Line (VAC-RMS=86V) VDC=122V, Series R=200kΩ to HV 0.790 0.825 0.860 V Vlimit-H Current Limit at High Line (VAC-RMS=259V) VDC=366V, Series R=200kΩ to HV 0.690 0.725 0.760 V VOCP-L OCP Trigger Level at Low Line (VAC-RMS=86V) VDC=122V, Series R=200kΩ to HV 0.450 0.480 0.510 V VOCP-H OCP Trigger Level at High Line (VAC=259V) VDC=366V, Series R=200kΩ to HV 0.390 0.420 0.450 V tSOFT-START Period During Startup Startup Time 7 8 9 ms tD-OCP Delay Time for Output OCP V CS>VOCP 190 215 240 ms tD-SCP Delay Time for Output SCP VCS>VOCP and VDD< VDD-SCP 12 15 18 ms PWM Output Section DCYMAX Maximum Duty Cycle 88.0 89.5 91.0 % VOL Output Voltage Low V DD = 15V, IO=50mA 1.5 V VOH Output Voltage High V DD = 12V, IO=50mA 8 V tR Rising Time GATE=1nF 95 ns tF Falling Time GATE=1nF 30 ns VCLAMP Gate Output Clamping Voltage V DD=22V 11.0 13.5 16.0 V Over-Temperature Protection Section IRT Output Current of RT Pin 92 100 108 μA VOTP-LATCH- OFF Threshold Voltage for Over- Temperature Protection 1.00 1.05 1.10 V tD_OTP-LATCH Over-Temperature Latch-Off Debounce VFB > VFB-N 14 16 18 ms VFB < VFB-G 40 51 62 ms VOTP2-LATCH- OFF Second Threshold Voltage for Over-Temperature Protection 0.65 0.70 0.75 V tD_OTP2-LATCH Second Over-Temperature Latch-Off Debounc VFB > VFB-N 110 185 260 µs VFB < VFB-G 320 605 890
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6747 • Rev. 1.0.1 12 FAN6747 — Highly Integrated Green-Mode PWM Controller Operation Description Startup Current For startup, the HV pin is connected to the line input through an external diode and resistor, R HV, (1N4007 / 200KΩ recommended). Peak startup current drawn from the HV pin is (V AC × 2 )/RHV and charges the hold-up capacitor through the diode and resistor. When the V DD capacitor level reaches V DD-ON, the startup current switches off. At this moment, the V DD capacitor only supplies the FAN6747 to maintain the V DD before the auxiliary winding of the main transformer provides the operating current. Operating Current Operating current is around 2mA. The low operating current enables better efficiency, power saving, and reduces the requirement of V DD hold-up capacitance. Green-Mode Operation The proprietary green-mode function provides off-time modulation to reduce the switching frequency in light- load and no-load conditions. V FB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz. Two-Level Over-Current Protection (OCP) The cycle-by-cycle current limiting shuts down the PWM immediately when the sense voltage is over the limited threshold voltage (0.825V at low line). Additionally, when the sense voltage is higher than the OCP threshold (0.48V at low line), the internal counter counts for 220ms, then latches off PWM. When OCP occurs, PWM output is turned off and V DD begins decreasing. When VDD goes below the turn-off threshold (~9V), the controller is totally shut down. V DD continues to discharge below VDD-OLP by IDD-OLP. Then VDD is charged up to the turn-on threshold voltage of 16.5V through the startup resistor. When VDD is charged to 16.5V, it cycles again. This phenomenon is called two-level UVLO. Brownout and Constant Power Limited HV Pin Unlike previous PWM controllers, FAN6747’s HV pin isn’t only used for startup; it can also detect the AC line voltage to perform brownout function and set the current limit level. Through a fast diode and startup resistor to sample the AC line voltage, the peak value refreshes and stores in register at each sampling cycle. W hen internal update time is met, this peak value is used to for brownout and current-limit level judgment. Equations 1 and 2 can be used to calculate out the level of brown-in or brownout converted to RMS value. For power saving, FAN6747 enlarges the sampling cycle to lower the power loss from HV sampling at light-load condition. 2/)6.1 6.19.0()( +×=− HV ONAC RRMSV (1) 2/)6.1 6.181.0()( +×=− HV OFFAC RRMSV (2) Short-Circuit Protection (SCP) This protection is used to handle the huge output demand if the power supply output is suddenly shorted to ground. If V DD drops under 10V and the sensed voltage is higher than the limited threshold voltage, SCP is triggered and PWM output is latched off. This latch condition is reset only if V DD is discharged under 4V or by unplugging AC power line. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16.5V and 9V, respectively. During startup, the hold-up capacitor must be charged to 16.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply V DD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 9V during startup. This UVLO hysteresis window ensures that the hold-up capacitor is adequate to supply V DD during startup. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and can not switch off the gate driver. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13.5V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. VDD Over-Voltage Protection (OVP) VDD over-voltage protection is built in to prevent damage due to abnormal conditions. If the V DD voltage is over the over-voltage protection voltage (V DD-OVP) and lasts for t D-OVP, the PWM pulses are disabled until the V DD voltage drops below 4V, then restarts again. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6747 • Rev. 1.0.1 13 FAN6747 — Highly Integrated Green-Mode PWM Controller Built-In Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6747 inserts a synchronized, positive-going, ramp at every switching cycle. Constant Output Power Limit When the SENSE voltage across sense resistor R S reaches the threshold voltage, the output GATE drive is turned off after a small delay, t PD. This delay introduces an additional current proportional to t PD • VIN / LP. Since the delay is nearly constant regardless of the input voltage V IN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a power-limiter is controlled by HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line input than at low-line input. Over-Temperature Protection (OTP) A NTC thermistor, R NTC, in series with a resistor, R A, is connected from the RT pin to GND pin. A constant current I RT is output from this pin. The voltage of the RT pin can be expressed as V RT = IRT • (RNTC + R A), where IRT is 100µA, the headroom of V RT is limited at around 5V by internal circuitry. As high ambient temperatures occur, R NTC is smaller, such that the V RT decreases. When V RT is less than 1.05V(V OTP) but over 0.7V, the PWM turns off after t D_OTP-LATCH. The other threshold, VDD under 0.7V, is used for fast shut down of FAN6747 after a short time. Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6747, and increasing the power MOS gate resistance improve performance.
B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
1.75 MAX
Figure 28. 8-Lead, Small Outline Integrated Circuit (SOIC) Package warranty therein, which covers Fairchild products.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6747 • Rev. 1.0.1 15 FAN6747 — Highly Integrated Green-Mode PWM Controller