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Technical content
Features
- Wide Input V oltage Range: 4.5 V to 65 V
- Continuous Output Current: 8 A
- Fixed Frequency V oltage Mode PWM Control with Input V oltage Feed−forward
- 0.6 V Reference V oltage with 0.67% Accuracy
- Adjustable Switching Frequency: 100 kHz to 1 MHz
- Dual LDOs for Single Supply Operation and to Reduce Power Loss
- Selectable CCM PWM Mode or PFM Mode for Light Loads
- External Compensation for Wide Operation Range
- Adjustable Soft−Start & Pre−Bias Startup
- Enable Function with Adjustable Input V oltage Under−V oltage−Lock−Out (UVLO)
- Power Good Indicator
- Over Current Protection, Thermal Shutdown, Over V oltage Protection, Under V oltage Protection and Short−circuit Protection
- High Performance Low Profile 6 mm x 6 mm PQFN Package
- This Device is Pb−Free and RoHS Compliant
Applications
- High V oltage POL Module
- Telecommunications: Base Station Power Supplies
- Networking: Computing, Battery Management Systems, USB−PD
- Industrial Equipment: Automation, Power Tools, Slot Machines PQFN35 6x6 CASE 483BE MARKING DIAGRAM www.onsemi.com See detailed ordering and shipping information on page 23 of this data sheet.
ORDERING INFORMATION
Z = Assembly Location X = Year / Lead Free YY = Week KK = Lot FAN65005A = Specific Device Code
Figure 1. Typical Application
4.5 V~65 V
Table 1. APPLICATION DESIGN EXAMPLE
Figure 2. Block Diagram
Figure 3. Pin Assignment (Bottom View) Table 2. PIN DESCRIPTION GND 18, 25 Analog ground for VCC, RT, SYNC, MODE, etc.
Table 2. PIN DESCRIPTION (continued) Table 3. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- Units, temperatures must be in degrees Celsius, power values (Q) must be in watts. Measured on 2s2p board, 80 x 80 mm2 with 546 mm2
Table 4. RECOMMENDED OPERATING CONDITIONS the Recommended Operating Ranges limits may affect device reliability. Table 5. ELECTRICAL CHARACTERISTICS
Table 5. ELECTRICAL CHARACTERISTICS (continued)
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Figure 40. LDO Block Diagram voltage level on PVCC for internal bias and MOSFET drive. shows which LDO will be selected and the LDO work status. Table 6. LDO SELECTION AND WORK MODE Both LDOs are designed to deliver up to 150 mA current. decouple any noise from high frequency driver currents. the regulator control circuit blocks are disabled. diagram and application configuration. R2 and R3 are both in k/C0087. Figure 41. EN/UVLO Block Diagram
- Non-master mode: The MODE pin connected to
Figure 44. Frequency Synchronization ~1.67% with 1 MHz frequency. frequency synchronization block diagram. and frequency synchronization. modulation (Short-formed DCM with Pulse Skipping). so that the power loss is reduced. Table 7. OPERATION MODES WITH MODE
0.6 V), PGOOD signal is asserted after a delay, tPG_DL, and
Figure 45. PGOOD Block Diagram MOSFETs are used to compare with this reference voltage. condition, its current flows from ground to switching node. 10 M/C0087 is considered to be open. high- and low-side MOSFETs in a different way. constantly and provides cycle by cycle peak current limit. voltage, the system enters hiccup mode. operation after the fault event is released. which are defined below respectively.
- OVP1 is protection when FB voltage is above
initiates a new PWM signal at the next clock cycle.
- OVP2 is protection when FB voltage is above
go into a soft start sequence and try to regulate.
www.onsemi.com Under Voltage Protection (UVP) Under voltage is a condition when output voltage is below 35% of its regulated level (checked on FB pin). If VFB ≤ 35% is met, then under voltage protection (UVP) is initiated, where IC enters hiccup mode. Over Temperature Protection (OTP) The device keeps monitoring the junction temperature. When the sensed temperature is above the protection point, T J_SD, over temperature protection (OTP) event occurred and the system shuts down. OTP is released when the sensed temperature is 20° lower than the trip point, T J_SD, where the system resets through soft-start. Output Inductor Selection The output inductor is selected to meet the output ripple requirements. The inductor value determines the converter’s ripple current /C0068IL. Largest ripple current occurs at highest Vin voltage. /C0068IL /C0043 /C0466VIN /C0042VOUT/C0467/C0466VOUT/C0467 FSW /C0064L /C0064VIN (eq. 6) Lower ripple current reduced core losses in the inductor and output voltage ripple. Highest efficiency is obtained at low frequency with small ripple current, however with a disadvantage of using a large inductor. Inductor value can be chosen based on the equation below in order to not exceed a max ripple current (usually 30% to 70% of max inductor current) L /C0119 /C0466VIN /C0042VOUT/C0467 FSW /C0064/C0068IL /C0064D (eq. 7) Output Capacitor Selection In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. 1. For ripple voltage considerations; the output bulk maintains the DC output voltage. The use of ceramic capacitors is recommended to sustain a low output voltage ripple. At switching frequency the ceramic capacitors are capacitance dominante use the following equation for calculating C out where the ripple output voltage is within 1% of V out. /C0068OUT /C0043VOUT /C0064(1 /C0042D) 8 /C0064FSW /C0064L /C0064COUT (eq. 8) And the RMS current through it is ICOUT(RMS) /C0043IOUT /C0064/C0068IL(pp) 12/C0504 (eq. 9) 2. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is shown CMIN /C0043 L /C0064IPK /C0466VOV /C0041VOUT/C0467 /C0042VOUT (eq. 10) where IPK is defined as: IPEAK /C0043IOUT,MAX /C0064 /C0068IL 2 (eq. 11) Where CMIN is the minimum value of output capacitor required, L is the output inductor, IPK is the peak load current, VOV is the increase in output voltage during a load release, VOUT is output voltage. Input Capacitor Selection V oltage and RMS current rating of the input capacitors are critical factors. Typically input capacitor is designed based on input voltage ripple of 2%. Capacitor voltage rating must be at least 1.25x greater than max input voltage . Maximum RMS current supplied by the input capacitance occurs at 50% duty cycle and when Vin =2 x V out. RMS current varies with load as shown below: ICIN(RMS) /C0043IOUT /C0064D /C0064/C04661 /C0042D /C0041/C0068IL(pp)2 12 /C0467/C0504 (eq. 12) Ceramic capacitors are best known for low ESR and are highly recommended. Loop Compensation Selecting External Compensation: The FAN65004B is a voltage mode buck regulator with an error amplifier compensated by external components to achieve accurate output voltage regulation and to respond to fast transient events. The goal of the compensation network is to provide a loop gain function with the highest cross−over frequency at adequate phase and gain margins. The output stage (LC) of the buck regulator is a double pole system. The resonance frequency of this lowpass filter is shown below: ƒp0 /C00431 2/C0112/C0064LCOUT/C0504 (eq. 13) The output filter has a zero that is calculated from the output capacitance and output capacitor ESR: ƒz0 /C0043 1 2/C0112/C0064ESR /C0064COUT (eq. 14) The bode plot of the power stage, error amplifier and the desired loop gain are drawn in the figure below. The first zero (fz1) compensates the phase lag of the pole located at the origin followed by a second zero (fz2) to compensate for one of the poles of the LC filter in order to crossover (f c) at −20 dB slope. The second pole (fp2) is aimed to cancel the ESR zero and finally the third pole (f p3) is to provide attenuation for frequencies above fsw/2.
Figure 46. Power Stage, Loop Gain and Compensator
- Place RT resistor and SS capacitor close to RT and
- Use a low impedance source such as a logic gate to
- Components of digital signals like EN/UVLO,
- Place BOOT capacitor right next to BOOT and PH
- Place inductor on top layer. Restrict the SW trace
wide as possible for thermal relief.
- Avoid all the compensation components from
- Keep the switching nodes away from sensitive
- Place decoupling caps right next to PVCC, VCC ,
- The output capacitors should be placed as close to
Table 8. ORDERING INFORMATION
www.onsemi.com PACKAGE DIMENSIONS PQFN35 6X6, 0.5P CASE 483BE ISSUE O
www.onsemi.com PACKAGE DIMENSIONS PQFN35 6X6, 0.5P CASE 483BE ISSUE O
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