FAN6300 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
High-Voltage Startup Quasi-Resonant Operation Cycle-by-Cycle Current Limiting Peak-Current-Mode Control Leading-Edge Blanking Internal Minimum tOFF Internal 2ms Soft-Start Over-Power Compensation GATE Output Maximum Voltage Auto-Recovery Short-Circuit Protection (FB Pin) Auto-Recovery Open-Loop Protection (FB Pin) VDD Pin & Output Voltage (DET Pin) OVP Latched
Applications
AC/DC NB Adapters Open-Frame SMPS
Description
The highly integrated FAN6300 PWM controller provides several features to enhance the performance of flyback converters. A built-in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the V DD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled immediately to improve power consumption. An internal valley voltage detector ensures the power system operates at Quasi-Resonant operation in wide- range line voltage and any load conditions and reduces switching loss to minimize switching voltage on drain of power MOSFET. To minimize standby power consumption and light-load efficiency, a proprietary green-mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. FAN6300 controller also provides many protection functions. Pulse-by-pulse cu rrent limiting ensures the fixed peak current limit level, even when a short circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as V DD drops below the turn-off threshold voltage, controller also disables PWM output. The gate output is clamped at 18V to protect the power MOS from high gate-source voltage conditions. The minimum t OFF time limit prevents the system frequency from being too high. If the DET pin reaches OVP, internal OTP is triggered, and the power system enters latch-mode until AC power is removed. FAN6300 controller is available in both 8-pin DIP and SOP packages.
Ordering Information
Temperature Range Eco Status Package Packing Method FAN6300DZ -40 to +105°C RoHS 8-Lead, Dual Inline Package (DIP) Tube FAN6300SZ -40 to +105°C RoHS 8-Lead, Small Outline Package (SOP) Reel & Tape For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Figure 3. Marking Information
Figure 4. Pin Configuration
1 DET
- Generates a ZCD signal once the secondary-side switching current falls to zero.
and minimize the switching losses. secondary shunt regulator are used. error-amplifier is equipped at the secondary-side of the power converter. ground for feedback-loop compensation. between the FB and the PWM circuit is used for the loop gain attenuation. voltage (around 4.2V) more than 55ms. voltage for peak current limit is 0.8V. clamped gate output voltage is 18V. current is less than 20µA and the operating current is lower than 4.5mA.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6300 • Rev. 1.0.1 5 FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VHV HV Pin 500 V VH GATE Pin -0.3 25.0 V VL V FB, VCS, VDET -0.3 7.0 V SOP-8 400 mW PD Power Dissipation DIP-8 800 mW TJ Operating Junction Temperature +150 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature, Soldering 10 Seconds +270 °C ESD Capability, Human Body Model 2.0 KV ESD ESD Capability, Machine Model 200 V Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential volt ages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit TA Operating Ambient Temperature -40 +105 °C
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6300 • Rev. 1.0.1 6 FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Electrical Characteristics
VDD=15V, TA=25℃, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VDD SECTION VOP Continuously Operating Voltage 25 V VDD-ON Turn-on Threshold Voltage 16 V VDD-PWM-OFF PWM Off Threshold Voltage 10 V VDD-OFF Turn-Off Threshold Voltage 8 V IDD-ST Startup Current 0V< VDD < VDD-ON GATE Open 30 µA IDD-OP Operating Current VDD=15V, fs=60KHz, CL=2nF 4.5 5.5 mA IDD-PWM-OFF Operating Current at PWM-Off Phase V DD=VDD-PWM-OFF-0.5V 80 µA VDD-OVP V DD Over-Voltage Protection (Latch-Off) 27 V tVDD-OVP V DD OVP Debounce Time 150 µs HV START-UP CURRENT SOURCE SECTION IHV Supply Current Drawn From HV Pin VAC=90V (VDC=120V), VDD=0V 1.2 mA IHV-LC Leakage Current After Startup HV=500V, VDD=VDD-OFF +1V 1 20 µA FEEDBACK INPUT SECTION AV Input-voltage to Current Sense Attenuation AV=ΔVCS/ΔVFB ZFB Input Impedance 3 5 7 K Ω IOZ Bias Current FB=V OZ 1.2 2.0 mA VOZ Zero Duty Cycle Input Voltage 1 V VFB-OLP Open-Loop Protection Threshold Voltage 3.9 4.2 4.5 V tD-OLP Debounce Time for Open-Loop / Overload Protection 55 ms tSS Internal Soft-Start Time 1.6 2.0 2.4 ms DET PIN OVP AND VALLEY DETECTION SECTION VDET-OVP Comparator Reference Voltage 2.45 2.50 2.55 V VV-HIGH Output High Voltage 4.5 V VV-LOW Output Low Voltage 0.5 V tDET-OVP Output OVP (Latched) Debounce Time 100 150 200 µs IDET-SOURCE Maximum Source Current 1 mA VDET-HIGH Upper Clamp Voltage 5 V VDET-LOW Lower Clamp Voltage 0.1 0.3 V tOFF-BNK Leading-Edge Blanking Time for DET- OVP, PWM MOS Turns Off(3) 4 µs Note: 3. Guaranteed by design.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6300 • Rev. 1.0.1 7 FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=25℃, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units OSCILLATOR SECTION tON-MAX Maximum On Time 40 45 50 µs VFB≧VN 8 µs tOFF-MIN Minimum Off Time (Maximum Frequency) VFB=VG 38 µs VN Beginning of Green-On Mode at FB Voltage Level 2.1 V VG Beginning of Green-Off Mode at FB Voltage Level 1.2 V ΔVFBG Green-Off Mode VFB Hysteresis Voltage 0.1 V VFB<VG 500 µs tSTARTER Start Timer (Time-out Timer) VFB>VFB-OLP 30 µs tTIME-OUT Timeout After tOFF-MIN (If No Valley Signal) 9 µs OUTPUT SECTION VOL Output Voltage Low V DD=15V, IO=150mA 1.5 V VOH Output Voltage High V DD=12V, IO=150mA 7.5 V tR Rising Time 120 ns tF Falling Time 60 ns VCLAMP GATE Output Clamping Voltage 17 18 19 V CURRENT SENSE SECTION tPD Delay to Output 150 250 ns VLIMIT Cycle-by-cycle Current Limit Threshold Voltage 0.75 0.80 0.85 V tON=45µs 0.3 V VSLOPE Slope Compensation tON=0µs 0.1 V tBNK Leading Edge Blanking Time (MOS Turns On) 225 300 375 ns VCS-H V CS Camped High Voltage CS Pin Floating 4.5 5.0 V tCS-H Delay Time CS Pin Floating 100 150 200 µs
Figure 24. 8-Lead, Small Outline Package (SOP) specifically the warranty therein, which covers Fairchild products.
Figure 25. 8-Lead, Dual Inline Package (DIP) specifically the warranty therein, which covers Fairchild products.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6300 • Rev. 1.0.1 14 FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller