FAN6204 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

ƒ SR Controller ƒ Suited for Flyback Converter in QR, DCM, and CCM Operation ƒ Suited for Forward Freewheeling Rectification ƒ Internal Green Mode for Lower No-Load Power Consumption and Higher Light-Load Efficiency ƒ PWM Frequency Tracking with Secondary-Side Winding Voltage Detection ƒ Ultra-Low VDD Operating Voltage for Various Output Voltage Applications (5V~24V) ƒ Ultra-Low Green Mode Operating Current: 1.1mA Typical ƒ VDD Pin Over-Voltage Protection (OVP) ƒ 12V (Typical) Gate Driver Clamp ƒ 8-Pin SOP Package

Applications

ƒ AC/DC NB Adapters ƒ Open-Frame SMPS ƒ Battery Charger

Description

FAN6204 is a secondary-side synchronous rectification (SR) controller to drive SR MOSFET for improving efficiency. The IC is suitable for flyback converters and forward free-wheeling rectification. FAN6204 can be applied in continuous or discontinuous conduction mode (CCM and DCM) and quasi-resonant (QR) flyback converters based on the proprietary innovative linear-predict timing-control technique. The benefits of this technique include a simple control method without current-sense circuitry to accomplish noise immunity. With PWM frequency tracking and secondary-side winding voltage detection, FAN6204 can operate in both fixed- and variable-frequency systems. In Green Mode, the SR controller stops all SR switching operation to reduce the operating current. Power consumption is maintained at minimum level in light- load condition.

Ordering Information

Temperature Range Package Packing Method FAN6204MY -40°C to +105°C 8-Pin, Small Outline Package (SOP) Tape & Reel

Figure 4. Marking Diagram Figure 5. Pin Assignments

1 AGND Signal Ground

2 AGND Signal Ground

3 GATE Driver Output. The totem-pole output driver for driving the power MOSFET. 4 GND Ground. MOSFET source connection. 5 VDD Power Supply. The threshold voltages for startup and turn-off are 4.8V and 4.5V, respectively.

6 AGND Signal Ground

7 RES

© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6204 • Rev. 1.0.0 4 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VL LPC, RES -0.3 7 V PD Power Dissipation(T A=25°C) 45 W ΘJA Thermal Resistance (Junction-to-Air) 151 °C/W ΘJC Thermal Resistance (Junction-to-Case) 58 °C/W TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Soldering 10 Seconds) +260 °C ESD Human Body Model 5 KV Charged Device Model 2 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit TA Operating Ambient Temperature -40 +105 °C

© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6204 • Rev. 1.0.0 5 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification

Electrical Characteristics

Unless otherwise specified, VDD=4.5V~25V and TA=-40°C ~ 105°C. Symbol Parameter Conditions Min. Typ. Max. Unit VOP Continuously Operating Voltage VDD- OFF 28.5 V VDD-ON Turn-On Threshold Voltage 4.3 4.8 5.3 V VDD-OFF Turn-Off Threshold Voltage 4.0 4.5 5.0 V IDD-OP Operating Current VDD=15V, LPC=50KHz, MOSFET CISS=6000pF 7 8 mA IDD-GREEN Operating Current in Green Mode V DD=15V 1.1 1.3 mA IDD-ST Startup Current V DD< VDD-ON 150 200 μA VDD-OVP V DD Over-Voltage Protection 26 27.5 28.5 V VDD-OVP-HYST Hysteresis Voltage for V DD OVP 1.8 2.1 2.4 V tVDD-OVP V DD OVP Debounce Time 40 70 100 μs Output Driver Section VZ Gate Output Clamp Voltage 10 12 14 V VOL Output Voltage Low V DD=6V, IO=50mA 0.5 V VOH Output Voltage High V DD=6V, IO=50mA 4 V tR Rising Time VDD=12V, CL=6nF, OUT=2V~9V 30 70 120 ns VDD=6V, CL=6nF, OUT=0.4V~4V 70 120 170 ns tF Falling Time VDD=12V, CL=6nF, OUT=9V~2V 20 50 100 ns VDD=6V, CL=6nF, OUT=4V~0.4V 20 90 130 ns tPD_HIGH_LPC Propagation Delay to OUT HIGH (LPC Trigger) tR: 0V~2V, VDD = 12V 250 ns tPD_LOW_LPC Propagation Delay to OUT LOW (LPC Trigger)(3) tF: 100%~90%, VDD = 12V 180 ns tMAX-PERIOD Limitation between LPC Rising Edge to Gate Falling Edge 22.5 25.0 28.0 μs VPMOS-ON Internal PMOS Turn-On to Pull-HIGH Gate (3) 8.3 V VPMOS-ON- HYS Hysteresis Voltage On(3) 0.9 V tINHIBIT Gate Inhibit Time M2 Option (Enable) 1.6 2.2 2.8 μs VGATE-PULL- HIGH Gate Pull-HIGH Voltage V DD = 5V 4.5 V LPC Section tBNK Blanking Time for Charging CT 400 500 600 ns tDELAY-COMP Sampling Continuous Time for t BNK Compensation(3) 1 μs VLPC-SOURCE LPC Lower Clamp Voltage Source I LPC=5µA 0.1 0.2 0.3 V ILPC-SOURCE LPC Source Current V LPC=0V 40 80 120 μA VLPC-EN SR Enabled Threshold Voltage VLPC-EN = VLPC-HIGH x 0.83 at VLPC- HIGH x 0.83< 2V, VO=15V, VO=VDD, VLPC-HIGH = 1.2V 0.85 1.00 1.15 V VEN-CLAMP SR Enable Threshold Clamp Voltage VLPC-EN =2V at VLPC-HIGH x 0.83 > 2V 2 V VLPC-TH-HIGH Threshold Voltage on LPC Rising tBNK-DIS Blanking Time LPC is HIGH During SR Gate Turn-On Period Prevent LPC Spike to Turn-Off Gate 350 ns

© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6204 • Rev. 1.0.0 6 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Unless otherwise specified, VDD=4.5V~25V and TA=-40°C ~ 105°C. Symbol Parameter Conditions Min. Typ. Max. Unit LPC Section (Continued) VLPC-CLAMP-H Higher Clamp Voltage (3) 6 V VLPC-DIS LPC Voltage to Disable SR Gate 4.0 4.2 4.4 V tLPC-HIGH Debounce Time for Disable SR Gate 1 μs tLPC-EN-RES No LPC Signal, Reset V LPC-EN 100 μs RES Section VRES-EN Threshold Voltage of V RES to Enable SR MOS 0.60 0.75 0.90 V tRES-LOW Debounce Time for Disable RES Function 1 2 µs VRES-CLAMP-H Higher Clamp Voltage (3) 6 V KRES-DROP RES Dropping Protection Ratio within One Cycle 90 % tRES-DROP Debounce Time for RES Dropping Protection 1.5 µs Internal Timing Section tCT Linear Operation Range of CT V LPC=1.5V 27 30 33 μs VLPC Linear Operation Range of LPC for CT Charge VDD<5V 0.8 3.4 V VDD>5V 0.8 4.0 V VDD-RES Linear Operation Range of VDD-RES for CT Discharge VDD<5V 0.8 3.4 V VDD>5V 0.8 4.0 V RatioLPC-RES Ratio Between LPC and RES 4.65 5.00 5.35 tLPC-EN Minimum LPC Time to Enable SR_Gate, V DET>VDET_TH_HIGH 0.9 1.1 1.3 µs tgate-limit t on-SR(n+1)< tgate-limitx ton-SR(n) 105 120 % Green Section tGREEN-OFF CT Capacitor tDIS Time to Leave Green Mode fS=65KHz 4.60 5.35 6.10 µs tGREEN-ON CT Capacitor tDIS Time to Enter Green Mode fS=65KHz 4.25 4.80 5.35 µs tGREEN-TIME- enter Cycle Time to Enter Green Mode CT Discharge Time < t GREEN-ON 3 Times tGREEN-TIME- leave Cycle Time to Leave Green Mode CT Discharge Time > t GREEN-OFF 7 Times tGREEN-ENTER No Gate Signal to Enter Green Mode (3) 75 µs Causal Function Section tCAUSAL If tS-PWM(n+1) > tCAUSALxtS-PWM(n) ÆSR Stops Switching, Enter Green Mode fS =65KHz Æ 40KHz 120 % tDEAD-CAUSAL SR Turn-off Dead Time by Causal Function fS=65KHz 380 580 780 ns tDEAD-CFR CFR Start to Shrink Timing (Last Time from SR Gate Falling to LPC Rising) CFR (Causal Function Regulator) 150 ns tDEAD-RE-CFR SR Gate Narrowed Down Width when t DEAD-CFR Triggered 1.5 μs Internal Over-Temperature Protection Section TOTP Internal Threshold Temperature for OTP (3) 140 °C TOTP-HYST Hysteresis Temperature for Internal OTP (3) 20 °C Note: 3. Guaranteed by design.

Figure 18. Typical Waveforms of Linear-Predict Timing Control in CCM and DCM/QR Flyback linear-predict timing control. to zero, the SR controller turns off the SR MOSFET.

Figure 19. Simplified Linear-Predict Block the same as inductor current discharge time (t L.DIS). shorter than tL.DIS. It is typical to set K around 5~5.5. proportional to VIN, so VCT also increases linearly. MOSFET is naturally turned off. the SR MOSFET turns off, to prevent fault triggering. the most stringent power conservation requirements. normal operation, as shown in Figure 21.

3 Times

Figure 20. Entering Green Mode Figure 21. Resuming Normal Operation function can guarantee reliable operation. Figure 22. Causal Function Operation

  1. Since the rising edge of V LPC among switching

be terminated to prevent fault trigger. Figure 23. Fault Causal Timing Protection Figure 24. When output load changes rapidly from light Figure 24. Gate Expand Limit Protection activated to prevent overlap. Figure 25. VRES Dropping Protection

© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6204 • Rev. 1.0.0 12 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification LPC Pin Open / Short Protection LPC-Open Protection: If V LPC is higher than V LPC-DIS (4.2V) for longer than debounce time tLPC-HIGH, FAN6204 stops switching immediately and enters Green Mode. V LPC is clamped at 6V to avoid LPC pin damage. LPC-Short Protection: If V LPC is pulled to ground and the charging current of timing capacitor (C T) is near zero, SR gate is not output. RES Pin Open / Short Protection RES-Open Protection: If V RES is pulled to HIGH level, the gate signal is extremely small and FAN6204 enters Green Mode. In addition, VRES is clamped at 6V to avoid RES pin damage. RES-Short Protection: If V RES is lower than V RES-EN (0.7V) for longer than debounce time tRES-LOW, FAN6204 stops switching immediately and enters Green Mode. Under-Voltage Lockout (UVLO) The power ON and OFF VDD threshold voltages are fixed at 4.8V and 4.5V, respectively. With an ultra-low V DD threshold voltage, the FAN6204 can be used in various output voltage applications. VDD Pin Over-Voltage Protection (OVP) Over-voltage conditions are usually caused by an open feedback loop. V DD over-voltage protection prevents damage on the SR MOSFET. When the voltage on VDD pin exceeds 27.5V, the SR controller stops switching the SR MOSFET. Over-Temperature Protection (OTP) To prevent SR gate from fault triggering in high temperatures, internal over-temperature protection is integrated in FAN6204. Once the temperature is over 140°C, SR gate is disabled until the temperature drops below 120°C.

B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

1.75 MAX

Figure 26. 8-Pin, Small Outline Package (SOP) warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/.

© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6204 • Rev. 1.0.0 14 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification