FAN604 ONSEMI | Alldatasheet
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© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: March 2017- Rev. P0 FAN604 FAN604 Offline Quasi-Resonant PWM Controller The FAN604 is an advanced PWM controller aimed at achieving power density of ≥10W/in 3 in universal input range AC/DC flyback isolated power supplies. It incorporates Quasi -Resonant (QR) control with proprietary Valley Switching with a limited frequency variation. QR switching provides high efficiency by reducing switching losses while Valley Switching with a limited frequency variation bounds the frequency band to overcome the inherent limitation of QR switching. FAN604 features mWSaver® burst mode operation with extremely low operating current (300 μA) and significantly reduces standby power consumption to meet the most stringe nt efficiency regulations such as Energy Star’s 5-Star Level and CoC Tier II specifications. FAN604 includes several user configurable features aimed at optimizing efficiency, EMI and protections. FAN604 has a wide blanking frequency range that improves light load efficiency and eliminating audio noise for adaptive application . It incorporates user -configurable constant current reference, which allows controlling the maximum output current from primary-side, thereby optimizing transformer design to improv e the overall efficiency . It also includes several rich programmable protection features such as over -voltage protection (OVP), precise constant o utput current regulation (CC).
Features
Higher Average Efficiency by Quasi-Resonant Switching Operation with Wide Blanking Time Range Wide Input and Output Conditions Achieve High Power Density Power Supply Optimization Transformer Design for Adaptive Charger Application User Configurable Constant Current Reference (CCR) to Limit the Maximum Output Current Precise Constant Output Current Regulation with Programmable Line Compensation mWSaver® Technology for Ultra Low Standby Power Consumption (<20 mW) Forced and Inherent Frequency Modulation of Valley Switching for Low EMI Emissions and Common Mode Noise Built-In and User Configurable Over-Voltage Protection (OVP), Under-Voltage Protection (UVP) and Over-Temperature Protection (OTP) Programmable Over-Temperature-Protection through External NTC Resistor Fully Programmable Brown-In and Brownout Protection Built-In High-Voltage Startup to Reduce External Components Typical Applications Battery Charges for Smart Phones, Feature Phones, and Tablet PCs AC-DC Adapters for Portable Devices or Battery Chargers that Require CV/CC Control www.onsemi.com MARKING DIAGRAM ZXYTT 604 TM Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (M=SOIC) M: Manufacture Flow Code PIN CONNECTIONS HV NC CS GND FB SD 8FAN604MX VDD VS5 GATE CCR (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet.
www.onsemi.com VO DR COCSNP Np DSNP RSNP CBLK2 Ns Na RVS1 RVS2CVS LF CBLK1 AC IN Bridge HV GATE CS VDD VSGND FB CSNPRSNS RF1 RF2 CVDD CCSF RCS_COMP RCS RGF RGR DG Photo coupler Photo coupler Shunt Regulator RBias2RBias1 RComp CComp1 CComp2 RHV1 CCR SD CFB TX ChokeFuse RCCRCCCR RHV2 DAUX XC FAN604 RSD NTC Figure 1 FAN604 Typical Application
www.onsemi.com PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 HV High Voltage. This pin connects to DC bus for high-voltage startup. 2 NC No Connect. 3 CS Current Sense. This pin connects to a current-sense resistor to sense the MOSFET current for Peak-Current-Mode control for output regulation. The current sense information is also used to estimate the output current for CC regulation. 4 GATE PWM Signal Output. This pin has an internal totem-pole output driver to drive the power MOSFET. The gate driving voltage is internally clamped at 7.5V. 5 VDD Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically connected to an external VDD capacitor. 6 VS Voltage Sense. The VS voltage is used to detect resonant valleys for quasi-resonant switching. This pin detects the output voltage information and diode current discharge time based on the auxiliary winding voltage. It also senses input voltage for Brown-out protection. 7 CCR Constant Current Reference. This pin connects to external resistor to program the reference voltage of constant output current. 8 SD Shut Down. This pin is implemented for external over-temperature-protect by connecting NTC thermistor. 9 FB Feedback. Typically Opto-Coupler is connected to this pin to provide feedback information to the internal PWM comparator. This feedback is used to control the duty cycle in CV regulation. 10 GND Ground. 5.25V ZFB FB CSLEB VDD HV Start-up HV VS
7 CCR
S/H = Sampling and Hold Valley Detection Forced Frequency Modulation VCS-LIM IO Estimator VS OVP Fault OSC VS UVP Fault tDIS tDIS VFB VDD OVP FaultVVDD-OVP VDD UVLO 17.2V/5.5V Debounce VD VS_SH D C Q Q CLK VDD Driver Control GATE Maximum On Time VS UVP Fault Burst/Green Mode VFB VDD OVP Fault 10GND Peak Current Auto-Restart Protection OTP Fault VS OVP Fault Brown OUT VDD UVLO VDD UVLO VCS VCS ICOMP VCCR ICCR Brown INHV VNVS VNVS ISD SD Fault VSD-TH 8SD VCS Fault SD Fault VS Protection AV CS ProtectionVCS Fault VCS AV-CC Figure 2 FAN604 Block Diagram
www.onsemi.com MAXIMUM RATINGS 1. All voltage values, except differential voltages, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD ratings including HV pin: HBM=2.0 kV, CDM=0.75kV. RECOMMENDED OPERATING RANGES 4. The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditio ns are specified to ensure optimal performance. ON does not recommend exceeding them or designing to Absolute Maximum Ratings. Rating Symbol Value Unit Maximum Voltage on HV Pin VHV 500 V DC Supply Voltage VVDD 30 V Maximum Voltage on GATE Pin VGETE -0.3 to 30 V Maximum Voltage on Low Power Pins (Except Pin 1, Pin 4, Pin 5) Vmax -0.3 to 6 V Power Dissipation (TA=25C) PD 850 mW Thermal Resistance (Junction-to-Ambient) θJA 140 C/W Thermal Resistance (Junction-to-Top) ΨJT 13 C/W Operating Junction Temperature TJ -40 to +150 C Storage Temperature Range TSTG -40 to +150 C Human Body Model, JEDEC:JESD22_A114 (Except HV Pin) ESD 2.0 kV Charged Device Model, JEDEC:JESD22_C101 (Except HV Pin) 0.75 Rating Symbol Min Max Unit HV Pin Supply Voltage VHV 50 400 V VDD Pin Supply Voltage VVDD 6 25 V VS Pin Supply Voltage VVS 0.65 2.3 V CS Pin Supply Voltage VCS 0 0.9 V FB Pin Supply Voltage VFB 0 5.25 V CCR Pin Supply Voltage VCCR 0.2 1.7 V SD Pin Supply Voltage VSD 0 5 V Operating Temperature TA -40 +85 C
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ELECTRICAL CHARACTERISTICS
For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit HV Section Supply Current Drawn from HV Pin VHV=120 V, VDD=0 V IHV 1.2 2.0 10 mA Leakage Current Drawn from HV Pin VHV=500 V, VDD=VDD-OFF+1 V IHV-LC 0 0.8 10 μA Brown-In Threshold Voltage RHV=150kΩ, VIN =80VAC VBrown-IN 100 110 120 V VDD Section Turn-On Threshold Voltage VDD Rising VDD-ON 15.3 17.2 18.7 V Turn-Off Threshold Voltage VDD Falling VDD-OFF 5.0 5.5 5.7 V Threshold Voltage for HV Startup TJ = 25C VDD-HV-ON 4.1 4.7 5.4 V Startup Current VDD=VDD-ON-0.16 V IDD-ST - 300 450 μA Operating Supply Current VCS=5.0 V, VVS=3 V, VFB=3 V CGATE=1nF IDD-OP - 2 3 mA Burst-Mode Operating Supply Current VCS=0.3 V, VVS=0 V, VFB=0 V; VDD=VDD-ONVDD-OVP10 V, CGATE=1nF IDD-Burst - 300 600 μA VDD Over-Voltage-Protection Level TJ = 25C VVDD-OVP 27.5 29.0 29.5 V VDD Over-Voltage-Protection Debounce Time tD-VDDOVP - 70 105 μs Oscillator Section Maximum Blanking Frequency VFB > VFB-BNK-H fBNK-MAX 125 130 135 kHz Minimum Blanking Frequency VFB < VFB-BNK-L fBNK-MIN 16.5 18.5 20.5 kHz Minimum Frequency VVS = 1V fOSC-MIN 15 17 19 kHz Forced Frequency Modulation Range VFB> VFB-Burst--H ΔtFM-Range 210 265 310 ns Forced Frequency Modulation Period ΔtFM-Period 2.1 2.5 2.9 ms Feedback Input Section FB Pin Input Impedance ZFB 39 42 45 kΩ Internal Voltage Attenuator of FB Pin (Note 5) AV 1/3 1/3.5 1/4 V/V FB Pin Pull-Up Voltage FB Pin Open VFB-Open 4.55 5.25 5.90 V Frequency Foldback Starting/Stopping VFB TJ = 25C VFB-BNK-H 2.10 2.25 2.40 V TJ = 25C VFB-BNK-L 1.10 1.25 1.40 V FB Threshold to Enable/Disable Gate Drive in Burst Mode VFB Rising VFB-Burst-H 0.65 0.75 0.85 V VFB Falling VFB-Burst-L 0.60 0.70 0.80 V
www.onsemi.com ELECTRICAL CHARACTERISTICS (CONTINUED) For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit Voltage-Sense Section Maximum VS Source Current Capability IVS-MAX - - 3 mA VS Sampling Blanking Time 1 after GATE Pin Pull-Low VFB Falling and VFB < 2.0V tVS-BNK1 0.84 1.0 1.23 μs VS Sampling Blanking Time 2 after GATE Pin Pull-Low VFB Rising and VFB > 2.2V tVS-BNK2 1.45 1.8 2.15 μs Delay from VS Voltage Zero Crossing to PWM ON (Note 5) VVS=0V, CGATE=1nF tZCD-to PWM 175 ns VS Source Current Threshold to Enable Brown-out IVS-Brown-Out 360 450 530 μA Brown-Out Debounce Time tD-Brown-Out 12.5 16.5 21 ms Output Over-Voltage-Protection with Vs Sampling Voltage VVS-OVP 2.2 2.3 2.4 V Output Over-Voltage-Protection Debounce Pulse Counts NVS-OVP - 2 - Pulse Output Under-Voltage-Protection with Vs Sampling Voltage TJ = 25C VVS-UVP 0.625 0.650 0.675 V Output Over-Voltage-Protection Debounce Pulse Counts NVS-UVP - 2 - Pulse Output Under-Voltage Protection Blanking Time at start-up tVS-UVP-BLANK 25 40 55 ms Auto-Restart Cycle Counts when Extend Auto- Restart Mode is triggered VVS < VVS-UVP NVDD-Hiccup - 2 - Cycle Over-Temperature Protection Section Threshold Temperature for Over-Temperature-Protection (Note 5) TOTP - 140 - C Current-Sense Section Current Limit Threshold Voltage FB Pin Open VCS-LIM 0.865 0.890 0.915 V High Threshold Voltage of Current Sense VFB > VFB-BNK-L VCS-IMIN-H 0.39 0.44 0.51 V Middle Threshold Voltage of Current Sense VFB = 1V, TJ = 25C VCS-IMIN-M 0.30 0.35 0.40 V Low Threshold Voltage of Current Sense VFB < VFB-Burst-H, TJ = 25C VCS-IMIN-L 0.21 0.25 0.29 V GATE Output Turn-Off Delay (Note 5) tPD - 50 100 ns Leading-Edge Blanking Time (Note 5) tLEB - 150 200 ns
www.onsemi.com 5. Design guaranteed. ELECTRICAL CHARACTERISTICS (CONTINUED) For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit Shut-Down Function Section SD Pin Source Current ISD 90 103 110 μA Threshold Voltage for Shut-Down Function Enable VSD-TH 0.95 1.00 1.05 V Debounce Time for Shut-Down Function tD-SD 200 400 600 μs Ratio between threshold voltage and source current ZSD-TH 8.5 10 11 kΩ Hysteresis of Threshold Voltage for Shut- Down Function Enable VSD-TH-ST 1.30 1.35 1.40 V Duration of VSD-TH-ST at startup tSD-ST 0.4 1.0 1.6 ms Constant Current Correction Section High Line Compensation Current VIN = 264 Vrms ICOMP-H 90 100 110 μA Low Line Compensation Current VIN = 90 Vrms ICOMP-L 32 36 40 μA Constant Current Estimator Section CCR Pin Source Current ICCR 18.2 20 21.8 μA Constant Current Control Reference Offset Voltage (Note 5) VREF_CC_Offset 0.8 V Peak Value Amplifying Gain (Note 5) APK 3.6 V/V FB CC Pull-Up Voltage CC (Note 5) VFB-CC-Open 4.0 V Internal Voltage Attenuator of FB CC (Note 5) AV-CC 0.444 V/V GATE Section Gate Output Voltage Low VGATE-L 0 - 1.5 V Internal Gate PMOS Driver ON VDD Falling VDD-PMOS-ON 7.0 7.5 8.0 V Internal Gate PMOS Driver OFF VDD Rising VDD-PMOS-OFF 9.0 9.5 10.0 V Rising Time VCS=0 V, VS=0 V, CGATE=1nF tr 100 135 180 ns Falling Time VCS=0 V, VS=0 V, CGATE=1nF TJ = 25C tf 30 50 70 ns Gate Output Clamping Voltage VDD=25 V VGATE-CLAMP 6.8 7.5 8.2 V Maximum On Time VFB=3V, VCS=0.3V tON-MAX 20 22 25 μs
www.onsemi.com CCM Prevention The constant current calculation logic is based on flyback converter operation in DCM. The output current is estimated by calculating the averag e of output diode current in one switching cycle . If flyback converter goes into CCM operation , the discharge time of magnetizing current will be fixed. Once this discharge time is fixed, it will increase the average of output diode current. During the CC region, w hen output voltage becomes lower, the time that the magnetizing current decreases down to zero is longer , as shown in Figure 30. FAN604 provides the lower operation frequency that can be down to 17 kHz (fOSC-MIN) to prevent the system goes into CCM operation. VDS tON tD fOSC-MIN ILm VIN nVO nVO nVO tD tD IO VO CV-CC Curve CC Region CV Region UVP Figure 30 The Minimum Operation Frequency HV Startup and Brown-In Figure 31 shows the high -voltage (HV) startup circuit. An Internal JFET provides a high voltage current source, whose characteristics are shown in Figure 32. To improve reliability and surge immunity, it is typical to use a R HV resistor between the HV pin and the bulk capacitor voltage. The actual current flowing into the HV pin at a given bulk capac itor voltage and startup resistor value is determined by the intersection point of characteristics I -V line and the load line as shown in Figure 32. During startup, the internal startup circuit is enabled and the bulk capacitor voltage supplies the current, I HV, to charge the hold -up capacitor, C VDD, through R HV. When the V DD voltage reaches V DD-ON, the sampling circuit shown in Figure 31 is turned on for tHV-det (100 µs) to sample the bulk capacitor voltage. Voltage across R LS is compared with reference which generates a signal to start switching. If brown -in condition is not detected within this time, switching does not start. Equation 8 can be used to progra m the brown -in of the system. If line voltage is lower than the prog rammed brown-in voltage, FAN604 goes in auto-restart mode. REF LS HVJEFTLS IN VR RRRV (eq. 8) Once switching starts, the internal HV startup circuit is disabled. During normal switching, the line voltage information is obtained from the I VS signal. Once the HV startup circuit is disabled, the energy stored in C VDD supplies the IC operating current until the transformer auxiliary winding voltage reaches the nominal value. Therefore, C VDD should be properly designed to prevent VDD from dropping below VDD-OFF threshold (typically
5.5 V) before the auxiliary winding bu ilds up enough
voltage to supply V DD. During startup, the IC current is limited to IDD-ST (300 μA). AC Line CDD HV VDD RHV VDD.ON/ VDD.OFF VDD Good RLS=1.2kΩ CX1 CX2 Brown IN -Vref = 0.845V VDD=VDD-ON(17.2V) RJFET=6.4kΩ Figure 31 HV Startup Circuit 500V100V 200V 300V 400V 10mA IHV 1.2mA 2mA BLK HV V R BLKV VHV Figure 32 Characteristics of HV pin
www.onsemi.com Pulse-by-Pulse Current Limit During startup or overload condition, the feedback loop is saturated to high and is unable to control the primary peak current. To limit the current during such conditions, FAN604 has pulse -by-pulse current limit protection which forces the GATE to turn off when the CS pin voltage reaches the current limit threshold, V CS-LIM (0.89 V). Secondary-Side Diode Shot Protection When the secondary -side diode is damaged, the slope of the primary -side peak current will be sharp within leading-edge blanking time. To limit the current during such conditions, FAN604 has secondary-side diode short protection which forces the GATE to turn off when the CS pin voltage reaches 1.6 V. After one switching cycle, it will operate in Auto-Restart mode as shown in Figure 38. Current Sense Short Protection Current sense short protection prevents damage caused by CS pin open or short to ground. After two switching cycle, it will operate in Auto-Restart mode. Figure 38 shows the internal circuit of current sense short protection. When abnormal system conditions occur, which cause CS pin voltage lower than 0.2 V after de - bounce time (t CS-short) for more than 2 consecutive switching cycles, PWM pulses are disabled and FAN604 enters Auto-Restart protection. The I CS-Short is an internal current source, which is proportional to line voltage. The de-bounce time (t CS-short) is created by I CS-short, capacitor (2 pF) and threshold voltage ( 3.0 V). This de -bounce time (t CS-short) is inversely proportional to the DC link capacitor voltage, VBLK. 2pF 3.0V ICS-Short 0.2V CCSF RCS_COMP RCS IDS GATE CS D Q PWM Counter Auto Restart Np GATE tCS-Short VBLK 1.6V 0.89V D Q Counter Auto Restart PWM LEB Pulse-by-Pulse Figure 38 Current Sense Protection Circuit
www.onsemi.com PCB Layout Guideline Print circuit board (PCB) layout and design are very import for switching power supplies where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes excessive EMI and prevent the power supply from being disrupted during surge/ ESD tests. The following guidelines are recommended for layout designs. To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors C BLK1 and C BLK2 first, then to the transformer and MOSFET. The primary -side high -voltage current loop is CBLK2 - Transformer - MOSFET - RCS - CBLK2. The area enclosed by this current loop should be as small as possible . The trace for the control signal (FB, CS, VS and GATE ) should not go across this primary high-voltage current loop to avoid interference. Place RHV for protection against the inrush spike on the HV pin (150kΩ is recommended). RCS should be connected to the ground of C BLK2 directly. Keep the trace short and wide (Trace 4 to 1) and place it close to the CS pin to reduce switching noise. High -voltage traces related to the drain of MOSFET and RCD snubber should be away from control circuits to prevent unnecessary interference. If a heat sink is used for the MOSFET, connect this heat sink to ground. As indicated by 2, the area enclosed by the transformer auxiliary winding, D AUX and C VDD, should also be small. Place C VDD, C VS, R VS2, C FB, RCCR, CCCR, RCS_COMP and C CSF close to the controller for good decoupling and low switching noise. As indicated by 3, the ground of the control circuits should be connected as a single point first, then to other circuitry. Connect ground by 3 to 2 to 4 to 1 sequence. This helps to avoid common impedance interference for the sense signal. Regarding the ES D discharge path, use the shortcut pad between AC line and DC output (most recommended). Another method is to discharge the ESD energy to the AC line through the primary -side main ground 1. Because ESD energy is delivered from the secondary side to the primary side through the transformer stray capacitor or the Y capacitor, the controller circuit should not be placed on the discharge path. 5 shows where the point - discharge route can be placed to effectively bypass the static electricity energy. For the surge path, select fusible resistor of wire wound type to reduce inrush current and surge energy and use π input filter (two bulk capacitors and one inductance) to share the surge energy. VO DR COCSNP Np DSNP RSNP CBLK2 Ns Na RVS1 RVS2CVS LF CBLK1 AC IN Bridge HV GATE CS VDD VSGND FB CSNPRSNS RF1 RF2 CVDDCCSF RCS_COMP RCS RGF RGR DG Photo coupler Photo coupler Shunt Regulator RBias2RBias1 RComp CComp1 CComp2 RHV1 CCR SD CFB TX ChokeFuse RCCRCCCR RHV2 DAUX XC FAN604 RSD NTC 4 CY Figure 39 Recommended Layout for FAN604
www.onsemi.com †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D Device Operating Temperature Range Package Shipping † FAN604MX -40C to +125C 10-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch Narrow Body Tape & Reel
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