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Technical content
Features
- Quiescent Current in PFM Mode: 60 /C0109A (Typical)
- Digitally Programmable Output V oltage: ♦ 0.6 −1.3875 V in 12.5 mV Steps
- Best−in−Class Load Transient
- Continuous Output Current Capability: 5 A
- 2.5 V to 5.5 V Input V oltage Range
- Programmable Slew Rate for V oltage Transitions
- Fixed−Frequency Operation: 2.4 MHz
- I2C−Compatible Interface Up to 3.4 Mbps
- Internal Soft−Start
- Input Under−Voltage Lockout (UVLO)
- Thermal Shutdown and Overload Protection
- 20−Bump Wafer−Level Chip Scale Package (WLCSP)
Applications
- Graphic, and DSP Processors ARM/C0116, Krait/C0116, OMAP/C0116, NovaThor/C0116, ARMADA/C0116
- Hard Disk Drives
- Tablets, Netbooks, Ultra−Mobile PCs
- Smart Phones
- Gaming Devices
ORDERING INFORMATION
Power−Up Defaults I2C Slave Address Device ID Device Marketing PackageVSEL0 VSEL1 FAN53200UC35X OFF 1.15 V C0 0000 B9 WLCSP−20 FAN53200UC44X 1.15V 0.85 V C0 0000 CD WLCSP−20 www.onsemi.com WLCSP−20 CASE 567SH Figure 1. Typical Application
Figure 2. Pin Assignment (Top View) Table 1. PIN DESCRIPTIONS A4 VOUT VOUT. Sense pin for VOUT. Connect to COUT. B4 AGND Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin. VIN Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path. SW Switching Node. Connect to the inductor.
Table 2. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. Table 3. RECOMMENDED OPERATING CONDITIONS performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. THERMAL PROPERTIES
- See Thermal Considerations in the Application Information section.
Table 5. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at VIN = 2.5 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C, VIN = 5 V, and EN = HIGH. performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 6. SYSTEM CHARACTERISTICS
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, Auto PFM Mode, TA = 25°C; circuit and components according to Figure 1. Figure 3. Efficiency vs. Load Current and Input Figure 4. Output Regulation vs. Load Current Figure 5. Output Regulation vs. Load Current, Figure 6. PFM Entry / Exit Level vs. Input Figure 7. Output Ripple vs. Load Current Figure 8. Frequency vs. Load Current
2.7 VIN
3.6 VIN
5.0 VIN
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, Auto PFM Mode, TA = 25°C; circuit and components according to Figure 1. Figure 9. Quiescent Current vs. Input Voltage, Figure 10. Shutdown Current vs. Input Figure 11. Load Transient, IOUT = 0.1 A /C0064
1.2 A, Auto PFM Mode, TR = TF = 100 ns
Figure 12. Line Transient, VIN = 3.0 V /C0064 3.6 V, Figure 13. Startup, Rload = 50 /C0087
- Dynamically re−program the output voltage in 12.5 mV steps;
- Reprogram the mode to enable or disable PFM;
- Control voltage transition slew rate; or
- Enable / disable the regulator. Control Scheme The FAN53200 uses a proprietary non−linear, fixed− frequency PWM modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. The regulator performance is independent of the output capacitor ESR, allowing for the use of ceramic output capacitors. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. For very light loads, the FAN53200 operates in Discontinuous Conduction Mode (DCM) single−pulse PFM, which produces low output ripple compared with other PFM architectures. Transition between PWM and PFM is relatively seamless, providing a smooth transition between DCM and Continuous Conduction Mode (CCM). PFM can be disabled by programming the MODE bit HIGH in the VSEL registers. Enable and Soft−Start When the EN pin is LOW; the IC is shut down, all internal circuits are off, and the part draws very little current. In this state, I2C cannot be written to or read from. All registers are reset to default values when EN pin is LOW. When the OUTPUT_DISCHARGE bit in the CONTROL register is enabled (logic HIGH) and the EN pin is LOW or the BUCK_ENx bit is LOW, a load is connected from VOUT to GND to discharge the output capacitors. Raising EN while the BUCK_ENx bit is HIGH activates the part and begins the soft−start cycle. During soft−start, the modulator’s internal reference is ramped slowly to minimize surge currents on the input and prevent overshoot of the output voltage. Synchronous rectification is inhibited during soft−start, allowing the IC to start into a pre−charged capacitive load. If large output capacitance values are used, the regulator may fail to start. Maximum C OUT capacitance for successfully starting with a heavy constant−current load is approximately: COUTMAX /C0091/C0466ILIMPK /C0042ILOAD/C0467/C0064320 /C0109 VOUT (eq. 1) where COUTMAX is expressed in /C0109F and ILOAD is the load current during soft−start, expressed in A. If the regulator is at its current limit for 16 consecutive current limit cycles, the regulator shuts down and enters tri−state before reattempting soft−start 1700 /C0109s later. This limits the duty cycle of full output current during soft−start to prevent excessive heating. The IC allows for software enable of the regulator, when EN is HIGH, through the BUCK_EN bits. Only BUCK_EN1 is initialized HIGH.
Table 7. HARDWARE AND SOFTWARE ENABLE
0 X X X OFF OFF
SLEW bits in the CONTROL register (Table 12). Table 8. TRANSITION SLEW RATE
HS Mode clock rate and timing. separated by REPEATED START conditions (Figure 17). All addresses and data are MSB first. Table 10. I2C BIT DEFINITIONS Figure 18. Write Transaction
1 A Data A
Figure 19. Read Transaction Table 11. REGISTER MAP
00 VSEL0 Controls VOUT settings when VSEL pin = 0
01 VSEL1 Controls VOUT settings when VSEL pin = 1
03 ID1 Read−only register identifies vendor and chip type
04 ID2 Read−only register identifies die revision
05 MONITOR Indicates device status
The following table defines the operation of each register bit. Table 12. BIT DEFINITIONS HIGH, BUCK_EN bit takes precedent. 6 MODE0 0 0 0: Allow Auto PFM Mode during light load. 5:0 NSEL0 101000 101100 Sets VOUT value from 0.6V to 1.3875 V in 12.5 mV steps (see Equation 2). HIGH, BUCK_EN bit takes precedent. 6 MODE1 0 0 0: Allow Auto PFM Mode during light load. 5:0 NSEL1 101100 010100 Sets VOUT value from 0.6V to 1.3875 V in 12.5 mV steps (see Equation 2). 7 OUTPUT_DISCHARGE 1 0 0: When the regulator is turned off, VOUT is not discharged. 6:4 SLEW 000 000 Sets the slew rate for positive voltage transitions (see Table 8).
3 Reserved 0 0 Always reads back 0
2 RESET
0 0 1: Reset all registers to default values.
4 Reserved 0 Always reads back 0
7 PGOOD 1 1: buck is enabled and soft−start is completed
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Application Information
The output inductor must meet both the required inductance and the energy−handling capability of the application. The inductor value affects the average current limit, the output voltage ripple, and the efficiency. The ripple current (/C0068I) of the regulator is: /C0068I /C0091 VOUT VIN /C0064/C0466VIN /C0042VOUT L /C0064fSW /C0467(eq. 3) The maximum average load current, I MAX(LOAD), is related to the peak current limit, I LIM(PK)by the ripple current such that: IMAX(LOAD) /C0043ILIM(PK) /C0042/C0068I 2 (eq. 4) The FAN53200 is optimized for operation with L = 330 nH, but is stable with inductances up to 1.0 /C0109H (nominal). The inductor should be rated to maintain at least 80% of its value at I LIM(PK). Failure to do so lowers the amount of DC current the IC can deliver. Efficiency is affected by the inductor DCR and inductance value. Decreasing the inductor value for a given physical size typically decreases the DCR; but since /C0068I increases, the RMS current increases, as do core and skin−effect losses. IRMS /C0043IOUT(DC) 2 /C0041/C0068I2 12/C0504 (eq. 5) The increased RMS current produces higher losses through the R DS(ON) of the IC MOSFETs as well as the inductor ESR. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. Table 13. EFFECTS OF INDUCTOR VALUE (from higher currents than the DC rating of the inductor. where COUT is the effective output capacitance. which occurs when the regulator is in PWM Mode. least 30 /C0109F of COUT should be used to ensure stability. fSW is reduced, causing /C0068VOUT to increase. the division ratio COUT ESL and the output inductor (LOUT). produce twice the square wave ripple as two x 10 /C0109F 0805. ratio of length to width. 0805s have lower ESL than 1206s. produce 0508 or 0612 capacitors with ultra−low ESL. reduces the high−frequency ripple components. between the inductance of the power source leads and CIN.
impact on regulator performance. from junction to ambient (ΔT). outer layer copper weight and one−ounce inner layers. temperature (TJ) should be maintained below 125°C.
- Use efficiency graphs to determine efficiency for
the desired VIN, VOUT, and load conditions.
- Calculate total power dissipation using:
- Determine IC losses by removing inductor losses
- Determine device operating temperature:
Table 14. RECOMMENDED CAPACITORS Table 15. RECOMMENDED INDUCTORS
www.onsemi.com PACKAGE DIMENSIONS WLCSP20 2.015x1.615x0.586 CASE 567SH ISSUE O
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