FAN5240

FAN5240 FAIRCHILD | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• CPU Core power: 0.925V to 2.0V output range
• ±1% reference precision over temperature
• Dynamic voltage setting with 5-bit DAC
• 5V to 24V input voltage range
• 2 phase interleaved switching
• Active droop to reduce output capacitor size
• Differential remote voltage sense
• High efficiency: >90% efficiency over wide load range >80% efficiency at light load
• Excellent dynamic response with V oltage Feed-Forward and Average Current Mode control
• Dynamic duty cycle clamp minimizes inductor current build up
• Lossless current sensing on low-side MOSFET or Precision current sensing using sense resistor
• Fault protections: Over-voltage, Over-current, and Thermal Shut-down
• Controls: Enable, Forced PWM, Power Good, Power Good Delay
• QSOP28, TSSOP28

Applications

• AMD Mobile Athlon CPU V CORE Regulator
• AMD Mobile Duron CPU V CORE Regulator General Description The FAN5240 is a single output 2-Phase synchronous buck controller to power AMD’s mobile CPU core. The FAN5240 includes a 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925VDC to 2.0VDC, which may be changed during operation. Special measures are taken to allow the output to transition with controlled slew rate to comply with AMD’s Power Now technology. The FAN5240 includes a precision reference, and a proprietary architecture with integrated compensation providing excellent static and dynamic core voltage regula- tion. The regulator includes special circuitry which balances the 2 phase currents for maximum efficiency. At light loads, when the filter inductor current becomes discontinuous, the controller operates in a hysteretic mode, dramatically improving system efficiency. The hysteretic mode of operation can be inhibited by the FPWM control pin. The FAN5240 monitors the output voltage and issues a PGOOD (Power-Good) when soft start is completed and the output is in regulation. A pin is provided to add delay to PGOOD with an external capacitor. A built-in over-voltage protection (OVP) forces the lower MOSFET on to prevent the output from exceeding a set voltage. The PWM controller's overcurrent circuitry moni- tors the converter load by sensing the voltage drop across the lower MOSFET. The overcurrent threshold is set by an exter- nal resistor. If precision overcurrent protection is required, an optional external current-sense resistor may be used. FAN5240 Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM

Figure 1. AMD Mobile Athlon/Duron CPU Core Supply Table 1. BOM for Figure 1

4 C13–C16 Panasonic EEFUE0D271R

1 L1, L2 Panasonic ETQP6F0R8LFA

1 Q1, Q4 Fairchild FDS6694

1 Q2, Q3, Q5, Q6 Fairchild FDS6676S

2 PGND2

17 VCORE D

PRODUCT SPECIFICATION FAN5240 REV. 1.1.7 8/29/02 Pin Configuration Pin Definitions Pin Number Pin Name Pin Function Description LDRV2 LDRV1 Low-Side Drive. The low-side (lower) MOSFET driver output. PGND2 PGND1 Power Ground. The return for the low-side MOSFET driver. BOOT2 BOOT1 BOOT. The positive supply for the upper MOSFET driver. Connect as shown in Figure 1. HDRV2 HDRV1 High-Side Drive. The high-side (upper) MOSFET driver output. SW2 SW1 Switching node. The return for the high-side MOSFET driver. ISNS2 ISNS1 Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 7 - 11 VID4 - VID0 Voltage Identification Code. Input to VID DAC. Sets the output voltage according to the codes set as defined in Table 2. These inputs have 1 µ A internal pull-up.

12 FPWM

Forced PWM mode. When logic high, inhibits the chip from entering hysteretic operating mode. If tied low, hysteretic mode will be allowed.

13 ILIM

Current Limit. A resistor from this pin to GND sets the current limit. 14 EN ENABLE. This pin enables IC operation when either left open, or pulled up to VCC. Toggling EN will also reset the chip after a latched fault condition.

15 AGND

Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin.

16 DELAY

Power Good / Over-Current Delay. A capacitor to GND on this pin delays the PGOOD from going high as well delaying the over-current shutdown. VCORE+ VCORE– VCORE Output Sense. Differential sensing of the output voltage. Used for regulation as well as PGOOD, under-voltage and over-voltage protection and monitoring. A resistor in series with this VCORE+ sets the output voltage droop.

19 PGOOD

Power Good Flag. An open-drain output that will pull LOW when the core output below 825mV. PGOOD delays its low to high transition for a time determined by CDELAY when VCORE rises above 875mV. LDRV2 PGND2 BOOT2 HDRV2 SW2 ISNS2 VID4 VID3 VID2 VID1 VID0 FPWM ILIM EN FAN5240 VCC LDRV1 PGND1 BOOT1 HDRV1 SW1 ISNS1 VIN SS PGOOD VCORE+ VCORED DELAY AGND QSOP-28 or TSSOP-28 θJA = 90°C/W

FAN5240 PRODUCT SPECIFICATION REV. 1.1.7 8/29/02 Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Recommended Operating Conditions 20 SS Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization as well as in operation. This pin is used as the reference against which the output is compared. During initialization, this pin is charged with a 25 µ A current source. Once this pin reaches 0.5V, its function changes, and it assumes the value of the voltage as set by the VID programming. The current driving this pin is then limited to ±500 µ A, that together with C SS sets a controlled slew rate for VID code changes.

21 VIN

Input voltage from battery. This voltage is used by the oscillator for feed-forward compensation of input voltage variation.

28 VCC

VCC. This pin powers the chip. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). Parameter Min. Typ. Max. Units VCC Supply Voltage: 6.5 V VIN 27 V BOOT, SW, HDRV Pins 33 V BOOT to SW 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (T J ) –10 150 °C Storage Temperature –65 150 °C Lead Soldering Temperature, 10 seconds 300 °C Parameter Conditions Min. Typ. Max. Units Supply Voltage VCC 4.75 5 5.25 V Supply Voltage VIN 6 24 V Ambient Temperature (T A ) –20 85 °C Pin Definitions (continued) Pin Number Pin Name Pin Function Description

PRODUCT SPECIFICATION FAN5240 REV. 1.1.7 8/29/02 Electrical Specifications (VCC = 5V, VIN = 6V–24V, and T A = recommended operating ambient temperature range using circuit of Figure 1, unless otherwise noted.) Note 1: Guaranteed by slew rate testing. Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current Operating, C L = 10pF 2 mA Shut-down (EN=0) 1 10 µ A VIN Current Operating 25 µ A Shut-down (EN=0) 1 µ A UVLO Threshold Rising VCC 4.3 4.45 4.6 V Falling VCC 3.8 3.95 4.10 V Regulator / Control Functions Output voltage per Table 2 0.925 2.00 V Error Amplifier Gain 86 dB Error Amplifier GBW 2.7 MHz Error Amplifier Slew Rate 1 V/ µ S VCORE+ Input Current 25 30 35 µ A ILIM Voltage R ILIM = 30K Ω 0.89 0.91 V ILIM T HOLDOFF C DELAY = 22nF 1.16 mS Over-voltage Threshold 2.2 2.35 2.5 V Over-voltage Protection delay 2 µ S EN, input threshold Logic LOW 0.8 V Logic HIGH 2 V Phase to Phase current mismatch IC contribution only Guaranteed by design ±5 % Over-Temperature Shut-down 150 °C Over-Temperature Hysteresis 25 °C Output Drivers (note 1) HDRV Output Resistance Sourcing 3.8 5 Ω Sinking 1.6 3 Ω LDRV Output Resistance Sourcing 3.8 5 Ω Sinking 0.8 1.5 Ω Oscillator Frequency 255 300 345 KHz Ramp Amplitude, pk–pk VIN = 16V 2 V Ramp Offset 0.5 V Ramp Gain 125 mV/V Reference, DAC and Soft-Start VID input threshold Logic LOW 0.8 V Logic HIGH 2.0 V VID pull-up current to VCC 1 µ A DAC output accuracy –11 % Soft Start Charging current (I SS SS < 90% of Programmed output 20 27 34 µ A V SS > 90% of Programmed output 350 500 650 µ A RampAmplitude VIN

Figure 2. IC Block Diagram

PRODUCT SPECIFICATION FAN5240 REV. 1.1.7 8/29/02 Circuit Description Overview The FAN5240 is a 2-phase, single output power management IC, which supplies the low-voltage, high-current power to modern processors for notebook PCs. Using very few exter- nal components, the IC controls a precision programmable synchronous buck converter driving external N-Channel power MOSFETs. The output voltage is adjustable from 0.925V to 2.0V by changing the DAC (VID) code settings (see Table 2). The output voltage of the core converter can be changed on-the-fly with programmable slew rate, which meets a key requirement of AMD's Mobile Athlon/Duron processors. The converter can operate in two modes: fixed frequency PWM, and variable frequency hysteretic depending on the load. At loads lower than the point where filter inductor cur- rent becomes discontinuous, hysteretic mode of operation is activated. Switchover from PWM to hysteretic operation at light loads improves the converter's efficiency and prolongs battery run time. As the filter inductor resumes continuous current, the PWM mode of operation is restored. Output Voltage Programming The output voltage of the converter is programmed by an internal DAC in discrete steps of 25mV from 0.925V to 1.300V and then in 50mV steps from 1.300V to 2.00V: Table 2. Output voltage VID 1 - Logic High or open, 0 = Logic Low VID0–4 pins will assume a logic 1 level if left open as each input is pulled up with a 1 µ A internal current source. VID4 VID3 VID2 VID1 VID0 VOUT to CPU 11111 0.000 11110 0.925 11101 0.950 11100 0.975 11011 1.000 11010 1.025 11001 1.050 11000 1.075 10111 1.100 10110 1.125 10101 1.150 10100 1.175 10011 1.200 10010 1.225 10001 1.250 10000 1.275 01111 0.000 01110 1.300 01101 1.350 01100 1.400 01011 1.450 01010 1.500 01001 1.550 01000 1.600 00111 1.650 00110 1.700 00101 1.750 00100 1.800 00011 1.850 00010 1.900 00001 1.950 00000 2.000

old, an internal Power-On Reset function disables the chip. change when the processor commands to do so. Figure 3. Soft-Start function of the total soft-start time, so TSS is essentially T90%. For 12mS of TDLY , CDELAY = 22nF.

1. Under-voltage - VCORE is below a fixed voltage.
2. Chip shut-down due to over-temperature or over-current

ence voltage set by the DAC, which appears on the SS pin. well as for phase balancing and current limiting. path from the error amplifier to the PWM comparator. during transients normally expected from the load.

0.9 V VID× CSS×

1. Spread between the two hysteretic thresholds
2. Output Inductor and Capacitor ESR

tion into hysteretic mode occurs. Figure 4. Transitioning between PWM and Hysteretic Mode

The following discussion refers to Figure 6. which is about 1K for the components in Figure 1. VCORE in anticipation of a step decrease in load current. Figure 5. Active Droop be scaled to match the output capacitor’s ESR voltage drop. tors required to handle CPU current transients to be reduced. a system without Active Droop. Figure 6. Current Limit and Active Droop Circuits

5 ISNS1

Figure 9. Compensation short circuit (over-current), and over-voltage conditions. value. This limits the current supplied by the DC input. Figure 10. Over-current shut-down delay logic

1. the IC is shut-down because the timer timed out:

power or toggling the EN pin.

1. ILIM det does not go high at least once per 8 clock

logic are reset, and a chip shut-down is averted.

16 Clock

Figure 11. Improving current sensing accuracy

1. This approach causes higher losses, but yields greater

therefore, 1/2 of the slew current comes from a single phase. turned on, when the current is near its peak in the cycle. old, the OVP comparator is disengaged. ing in a full soft-start cycle.

22 PGND

FAN5240 PRODUCT SPECIFICATION 14 REV. 1.1.7 8/29/02 Design and Component Selection Guidelines As an initial step, define operating voltage range and mini- mum and maximum load currents for the controller. For this discussion, Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the ripple current to be somewhere from 15% to 35% of the nominal current. At light load, the ripple current also determines the point where the converter will automatically switch to hysteretic mode of operation (I MIN) to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. where ∆I is the inductor ripple current, which we will choose for 20% of the full load current (12.5A in each phase) and OUT is the maximum output ripple voltage allowed. for this example we’ll use: VIN = 20V , VOUT = 1.5V ∆I = 20% *12.5A (per phase) = 2.5A FSW = 300KHz. Therefore, L ≈ 1.8µH The inductor's current rating should be chosen per the ILIMIT calculated above. Some transient currents over the inductor current rating may be tolerable if the inductor’s saturation characteristic is sufficiently “soft”. Output Capacitor Selection The output capacitor serves two major functions in a switch- ing power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The filtering requirements are a function of the switching frequency and the ripple current allowed, and are usually easy to satisfy in high frequency converters. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. Modern microprocessors produce transient load rates in excess of 10A/µs. High frequency ceramic capacitors placed beneath the processor socket initially supply the transient and reduce the slew rate seen by the bulk capacitors. The bulk capacitor values are generally determined by the total allowable ESR rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the processor power pins as physically possible. Consult with the processor manufacturer for specific decoupling requirements. Use only specialized low-ESR electrolytic capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a transient. In most cases, multiple electro- lytic capacitors of small case size perform better than a single large case capacitor. Input Capacitor Selection The input capacitor should be selected by its ripple current rating. For a 2 phase converter, the RMS currents is calcu- lated: This equation produces the worst case value at maximum duty cycle. For our example, that occurs when VIN = 5.5V and VOUT = 2V . For 25A maximum output the maximum RMS current at C IN: Power MOSFET Selection For the example in the following discussion, we will be selecting components for: VIN from 5V to 20V V OUT = 1.5V @ ILOAD(MAX) = 12.5A/phase The FAN5240 converter’s output voltage is very low with respect to the input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Therefore, Q2 should be selected to be a MOSFET with low R DS(ON) to minimize conduction losses. In contrast, Q1 is on for a maximum of 20% (when VIN = 5V) of the cycle, and its conduction loss will have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge G(SW)). IOUT Max 25A VIN 5.5 to 21 V VOUT 0.925 to 2 V ∆I2 I MIN× ∆VOUT L VIN VOUT– VOUT VIN dL IRMS IPK IRMS MAX() 5.6A=

Figure 12. Switching losses and QG Figure 13. Drive Equivalent Circuit SO-8 MOSFET thermal information).

19 HDRV

FAN5240 PRODUCT SPECIFICATION 16 REV. 1.1.7 8/29/02 Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substan- tial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feed- back functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV , for example. All sur- rounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces con- nected to the feedback components adjacent to these traces. It is not recommended to use High Density Interconnect Systems, or micro-vias on these signals. The use of blind or buried vias should be limited to the low current signals only. The use of normal thermal vias is left to the discretion of the designer. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak cur- rents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respec- tive pins of the IC. The FAN5240 utilizes advanced packaging technology that will have lead pitch of 0.6mm. High performance analog semiconductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area sur- rounding these devices. It is not recommended to use any type of rosin or acid core solder, or the use of flux in either the manufacturing or touch up process as these may contrib- ute to corrosion or enable electromigration and/or eddy cur- rents near the sensitive low current signals. When chemicals such as these are used on or near the PWB, it is suggested that the entire PWB be cleaned and dried completely before applying power.

PRODUCT SPECIFICATION FAN5240 REV. 1.1.7 8/29/02 17 Mechanical Dimensions 28-Pin QSOP A 0.069 1.75 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 0.004 0.10 0.061 1.54 0.053 1.35 0.010 0.25 A2 - - B 0.008 0.012 0.20 0.30 D 0.386 0.394 9.81 10.00 H 0.150 0.157 3.81 3.98 0.016 0.050 0.41 1.27 E 0.025 BSC 0.635 BSCe h L 0.228 0.244 0.0099 0.0196 5.80 6.19 0.26 0.49 0° 8° 0° 8° N2 8 2 8 α C 0.007 0.010 0.18 0.25 Notes: 10. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. Dimensioning and tolerancing per ANSI Y14.5M-1982. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions shall not exceed 0.25mm (0.010 inch) per side. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. The chamber on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. "L" is the length of terminal for soldering to a substrate. "N" is the maximum number of terminals. Terminal numbers are shown for reference only. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. HE A A2 D e B – C – ccc C LEAD COPLANARITY SEATING PLANE α L C

FAN5240 PRODUCT SPECIFICATION 18 REV. 1.1.7 8/29/02 Mechanical Dimensions 28-Pin TSSOP 9.7 ± 0.1 – B – 0.1 C PIN # 1 IDENT

14 ALL Lead Tips

0.2 LAND PATTERN RECOMMENDATION 0.65 0.42BA – A – 4.4 ± 0.1 1.78 4.16 7.72

0.51 TYP

3.2 6.4

1.2 MAX

0.65 0.19 –0.30 0.13

0.90 See Detail A

0.09–0.20 0.10 ± 0.05 0°–8° R0.31 R0.16 .025 GAGE PLANE SEATING PLANE DETAIL A 0.61 ± 0.1 DIMENSIONS ARE IN MILLIMETERS NOTES: A. Conforms to JEDEC registration MO-153, variation AB, Ref. Note 6, dated 7/93. B. Dimensions are in millimeters. C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions. D Dimensions and Tolerances per ANsI Y14.5M, 1982 1.00 12.00° Top & Botom +0.15 –0.10 BCA – C –

FAN5240 PRODUCT SPECIFICATION 8/29/02 0.0m 003 Stock#DS30005240 2002 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Ordering Information

Part Number Temperature Range Package Packing FAN5240QSC -10 °C to 85°C QSOP-28 Rails FAN5240QSCX -10 °C to 85°C QSOP-28 Tape and Reel FAN5240MTC -10 °C to 85°C TSSOP-28 Rails FAN5240MTCX -10 °C to 85°C TSSOP-28 Tape and Reel