FAN5236MTCX

FAN5236_04 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• Highly flexible dual synchronous switching PWM controller includes modes for: – DDR mode with in-phase operation for reduced channel interference – 90˚ phase shifted two-stage DDR Mode for reduced input ripple – Dual Independent regulators 180° phase shifted
• Complete DDR Memory power solution TT Tracks VDDQ/2 – VDDQ/2 Buffered Reference Output
• Lossless current sensing on low-side MOSFET or precision over-current using sense resistor CC Under-voltage Lockout
• Converters can operate from +5V or 3.3V or Battery power input (5 to 24V)
• Excellent dynamic response with V oltage Feed-Forward and Average Current Mode control
• Power-Good Signal
• Also supports DDR-II and HSTL
• Light load Hysteretic mode maximizes efficiency
• QSOP28, TSSOP28

Applications

• DDR V DDQ and V TT voltage generation
• Mobile PC dual regulator
• Server DDR power
• Hand-Held PC power General Description The FAN5236 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range from 0.9V to 5.5V that are required to power I/O, chip-sets, and memory banks in high-performance notebook comput- ers, PDAs and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. The hysteretic mode of operation can be disabled separately on each PWM converter if PWM mode is desired for all load levels. Efficiency is even further enhanced by using MOSFET’s R DS(ON) as a current sense component. Feed-forward ramp modulation, average current mode con- trol scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180 degree phase shift reduces input current ripple. The con- troller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode of operation one of the channels tracks the out- put voltage of another channel and provides output current sink and source capability — features essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5236 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is auto- matically restored when the over-voltage conditions go away. Under-voltage protection latches the chip off when either output drops below 75% of its set value after the soft- start sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision cur- rent-sensing is required, an external current-sense resistor may optionally be used. FAN5236 Dual Mobile-Friendly DDR / Dual-output PWM Controller

FAN5236 PRODUCT SPECIFICATION REV. 1.1.9 7/12/04 Pin Configurations Pin Definitions Pin Number Pin Name Pin Function Description

1 AGND

Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. LDRV1 LDRV2 Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. PGND1 PGND2 Power Ground. The return for the low-side MOSFET driver. Connect to source of low- side MOSFET. SW1 SW2 Switching node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. HDRV1 High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. BOOT1 BOOT2 BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3. ISNS1 ISNS2 Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. EN1 EN2 Enable . Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open. FPWM1 FPWM2 Forced PWM mode. When logic low, inhibits the regulator from entering hysteretic mode. Otherwise tie to VOUT. The regulator uses VOUT on this pin to ensure a smooth transition from Hysteretic mode to PWM mode. When VOUT is expected to exceed VCC, tie to VCC. VSEN1 VSEN2 Output Voltage Sense. The feedback from the outputs. Used for regulation as well as PG, under-voltage and over-voltage protection and monitoring.

11 ILIM1

Current Limit 1. A resistor from this pin to GND sets the current limit. SS1 SS2 Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5 µ A current source.

13 DDR

DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out of phase. AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 FPWM1 VSEN1 ILIM1 SS1 DDR VIN FAN5236 VCC LDRV2 PGND2 SW2 HDRV2 BOOT2 ISNS2 EN2 FPWM2 VSEN2 ILIM2/REF2 SS2 PG2/REF2OUT PG QSOP-28 or TSSOP-28 θJA = 90°C/W

PRODUCT SPECIFICATION FAN5236 REV. 1.1.9 7/12/04 Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Recommended Operating Conditions Note 1: Industrial temperature range (–40 to + 85°C) may be special ordered from Fairchild. Please contact your authorized Fairchild representative for more information.

14 VIN

Input Voltage. Normally connected to battery, providing voltage feed-forward to set the amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V input, connect through 100K to ground, which will set the appropriate ramp gain and synchronize the channels 90˚ out of phase.

15 PG1

Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a ±10% range of the 0.9V reference.

16 PG2 /

Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference.

18 ILIM2 /

Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2.

28 VCC

VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). Parameter Min. Typ. Max. Units VCC Supply Voltage: 6.5 V VIN 27 V BOOT, SW, ISNS, HDRV 33 V BOOTx to SWx 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (T J ) –40 150 °C Storage Temperature –65 150 °C Lead Soldering Temperature, 10 seconds 300 °C Parameter Conditions Min. Typ. Max. Units Supply Voltage VCC 4.75 5 5.25 V Supply Voltage VIN 24 V Ambient Temperature (T A ) Note 1 –10 85 °C Pin Definitions (continued) Pin Number Pin Name Pin Function Description

FAN5236 PRODUCT SPECIFICATION REV. 1.1.9 7/12/04 Electrical Specifications Recommended operating conditions, unless otherwise noted. Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current LDRV, HDRV Open, VSEN forced above regulation point 2.2 3.0 mA Shut-down (EN=0) 30 µ A VIN Current – Sinking VIN = 24V 10 30 µ A VIN Current – Sourcing VIN = 0V –15 –30 µ A VIN Current – Shut-down 1 µ A UVLO Threshold Rising VCC 4.3 4.55 4.75 V Falling 4.1 4.25 4.45 V UVLO Hysteresis 300 mV Oscillator Frequency 255 300 345 KHz Ramp Amplitude, pk–pk VIN = 16V 2 V Ramp Amplitude, pk–pk VIN = 5V 1.25 V Ramp Offset 0.5 V Ramp / VIN Gain VIN 3V 125 mV/V Ramp / VIN Gain 1V < VIN < 3V 250 mV/V Reference and Soft Start Internal Reference Voltage 0.891 0.9 0.909 V Soft Start current (I SS ) at start-up 5 µ A Soft Start Complete Threshold 1.5 V PWM Converters Load Regulation I OUTX from 0 to 5A, VIN from 5 to 24V -2 +2 % VSEN Bias Current 50 80 120 nA VOUT pin input impedance 45 55 65 K Ω Under-voltage Shutdown as % of set point. 2 µ S noise filter 70 75 80 % Over-voltage threshold as % of set point. 2 µ S noise filter 115 120 125 % I SNS Over-Current threshold R ILIM = 68.5K Ω see Figure 11. 112 140 168 µ A Output Drivers HDRV Output Resistance Sourcing 12 15 Ω Sinking 2.4 4 Ω LDRV Output Resistance Sourcing 12 15 Ω Sinking 1.2 2 Ω PG (Power Good Output) and Control pins Lower Threshold as % of set point, 2 µ S noise filter –86 –94 % Upper Threshold as % of set point, 2 µ S noise filter 108 116 % PG Output Low IPG = 4mA 0.5 V Leakage Current V PULLUP = 5V 1 µ A PG2/REF2OUT Voltage DDR = 1, 0 mA < I REF2OUT 10mA 99 1.01 % VREF2

Figure 3. IC Block Diagram Recommended operating conditions, unless otherwise noted.

Figure 4. DDR Regulator Application Table 1. DDR Regulator BOM . Refer to Power MOSFET Selection, page 15 for more information.

1 C1 AVX TPSV686*025#0150

1 C4 AVX TAJB686*006

2 C6A, C6B Panasonic EEFUE0G181R

19 VSEN2

26 PGND2

10 VSEN1

Figure 5. Dual Regulator Application Table 2. Dual Regulator BOM

1 Capacitor 68µf, Tantalum, 25V, ESR 95mΩ 1 C1 AVX TPSV686*025#095

2 Capacitor 10nf, Ceramic 2 C2, C3 Any

4 Capacitor 150nF, Ceramic 2 C5, C7 Any

5 Capacitor 330µf, Poscap, 4V, ESR 40mΩ 2 C6, C8 Sanyo 4TPB330ML

27 Schottky Diode 30V 2 D1, D2 Fairchild BAT54

29 Dual MOSFET with Schottky 1 Q1 Fairchild FDS6986S (note 1)

30 DDR Controller 1 U1 Fairchild FAN5236

Figure 8. Noise-susceptible In-Phase operation for DDR2 from the decision points of the other converter. Figure 9. Optimal 90° phasing for DDR2 0.9 is in seconds if CSS is in µF.

1. This mode of operation achieves high efficiency at nomi-

0.9 C SS×

Figure 10. Transitioning between PWM and Hysteretic Mode

the mode is changed to PWM on the next clock cycle. VSNS rises over the higher threshold (5mV above VREF).

1. Spread between the two hysteretic thresholds
2. Output Inductor and Capacitor ESR

Figure 11. Current Limit / Summing Circuits

The following discussion refers to Figure 11. its operating die temperature below 125°C. Figure 12. Improving current sensing accuracy

1. This approach causes higher losses, but yields greater

is disabled and the maximum duty cycle is 87%. performance over a wide range of operating conditions. source voltages of both upper and lower MOSFETs. MOSFET has decreased to less than approximately 1 volt. dead-time circit and shoot-through may occur.

100 R SENSE+()

Figure 15. Over-Current protection waveforms threshold, the OVP comparator is disengaged. set point, the regulator will shut down. asserted, resulting in a full soft-start cycle. synchronization by tying the VIN pin to +5V . help to choose the proper value of the output filter inductor.

8 CLK

FAN5236 PRODUCT SPECIFICATION REV. 1.1.9 7/12/04 15 Output Capacitor Selection The output capacitor serves two major functions in a switch- ing power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor require- ments are usually dictated by ESR, Inductor ripple current (∆I) and the allowable ripple voltage (∆V). In addition, the capacitor’s ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 5 is 120mV P-P. Some additional ripple will appear due to the capacitance value itself: which is only about 1.5mV for the converter in Figure 5 and can be ignored. The capacitor must also be rated to withstand the RMS current which is approximately 0.3 X (∆I), or about 400mA for the converter in Figure 5. High frequency decoupling capacitors should be placed as close to the loads as physically possible. Input Capacitor Selection The input capacitor should be selected by its ripple current rating. Two-Stage Converter Case In DDR mode (Figure 4), the VTT power input is powered by the VDDQ output, therefore all of the input capacitor rip- ple current is produced by the VDDQ converter. A conserva- tive estimate of the output current required for the 2.5V regulator is: As an example, if average I VDDQ is 3A, and average IVTT is 1A, IVDDQ current will be about 3.5A. If average input volt- age is 16V , RMS input ripple current will be: where D is the duty cycle of the PWM1 converter: therefore: Dual Converter 180° phased In Dual mode (Figure 5), both converters contribute to the capacitor input ripple current. With each converter operating 180° out of phase, the RMS currents add in the following fashion: which for the dual 3A converters of Figure 5, calculates to: Power MOSFET Selection Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN5236 converter’s output volt- age is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to mini- mize conduction losses, thereby selecting a MOSFET with low R DS(ON). In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and it’s conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge. High-Side Losses: Figure 15 shows a MOSFET’s switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing V GS vs. time with a constant current charging the gate. The x-axis therefore is also representative of gate charge (Q G) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. ESR ∆V ∆V ∆I IREG1 IVDDQ IVTT IRMS IOUT MAX() DD 2–= (15) D VOUT VIN IRMS 3.5 2.5  2 – 1.49A== (17) IRMS IRMS 1()

2 IRMS 2()

2+ o r= (18a) IRMS I1() 2 D1 D1 2–() I2() 2 D2 D2 2–()+ = (18b) IRMS 1.4A=

FAN5236 PRODUCT SPECIFICATION REV. 1.1.9 7/12/04 17 Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substan- tial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedi- cate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV , for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use High Density Intercon- nect Systems, or micro-vias on these signals. The use of blind or buried vias should be limited to the low current signals only. The use of normal thermal vias is left to the discretion of the designer. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ring- ing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respec- tive pins of the IC. The FAN5236 utilizes advanced packaging technologies with lead pitches of 0.6mm. High performance analog semi- conductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area surround- ing these devices.

PRODUCT SPECIFICATION FAN5236 18 REV. 1.1.9 7/12/04 Mechanical Dimensions 28-Pin QSOP A 0.069 1.75 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 0.004 0.10 0.061 1.54 0.053 1.35 0.010 0.25 A2 - - B 0.008 0.012 0.20 0.30 D 0.386 0.394 9.81 10.00 H 0.150 0.157 3.81 3.98 0.016 0.050 0.41 1.27 E 0.025 BSC 0.635 BSCe h L 0.228 0.244 0.0099 0.0196 5.80 6.19 0.26 0.49 0° 8° 0° 8° N2 8 2 8 α C 0.007 0.010 0.18 0.25 Notes: 10. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. Dimensioning and tolerancing per ANSI Y14.5M-1982. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions shall not exceed 0.25mm (0.010 inch) per side. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. The chamber on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. "L" is the length of terminal for soldering to a substrate. "N" is the maximum number of terminals. Terminal numbers are shown for reference only. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. HE A A2 D e B – C – ccc C LEAD COPLANARITY SEATING PLANE α L C

FAN5236 PRODUCT SPECIFICATION REV. 1.1.9 7/12/04 19 Mechanical Dimensions 28-Pin TSSOP 9.7 ± 0.1 – B – 0.1 C PIN # 1 IDENT

14 ALL Lead Tips

0.2 LAND PATTERN RECOMMENDATION 0.65 0.42BA – A – 4.4 ± 0.1 1.78 4.16 7.72

0.51 TYP

3.2 6.4

1.2 MAX

0.65 0.19 –0.30 0.13

0.90 See Detail A

0.09–0.20 0.10 ± 0.05 0°–8° R0.31 R0.16 .025 GAGE PLANE SEATING PLANE DETAIL A 0.61 ± 0.1 DIMENSIONS ARE IN MILLIMETERS NOTES: A. Conforms to JEDEC registration MO-153, variation AB, Ref. Note 6, dated 7/93. B. Dimensions are in millimeters. C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions. D Dimensions and Tolerances per ANsI Y14.5M, 1982 1.00 12.00° Top & Botom +0.15 –0.10 BCA – C –

PRODUCT SPECIFICATION FAN5236 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/12/04 0.0m 004 Stock#DS30005236  2004 Fairchild Semiconductor Corporation

Ordering Information

Part Number Temperature Range Package Packing FAN5236QSC -10 °C to 85°C QSOP-28 Rails FAN5236QSCX -10 °C to 85°C QSOP-28 Tape and Reel FAN5236MTC -10 °C to 85°C TSSOP-28 Rails FAN5236MTCX -10 °C to 85°C TSSOP-28 Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.