FAN5234 FAIRCHILD | Alldatasheet
Document overview
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- PDF pages: 15
Technical content
Features
- W ide input voltage range (2 to 24V) for Mobile systems
- Excellent dynamic response with V oltage Feed-Forward and Average Current Mode control
- Lossless current sensing on low-side MOSFET or precision over-current using sense resistor
- VCC Under-voltage Lockout
- P ower-Good Signal
- Light load Hysteretic mode maximizes efficiency
- QSOP16, TSSOP16
- 300Khz or 600Khz operation
Applications
- Mobile PC regulator
- Hand-Held PC power General Description The FAN5234 PWM controller provides high efficiency and regulation with an adjustable output from 0.9V to 5.5V that are required to power I/O, chip-sets, memory banks or peripherals in high-performance notebook computers, PDAs and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. The hysteretic mode of operation can be disabled if PWM mode is desired for all load levels. Efficiency is even further enhanced by using MOSFET’s R DS(ON) as a current sense component. Feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to load transients. The FAN5234 monitors these outputs and generates a PGOOD (power good) signal when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over- voltage conditions go away. Under-voltage protection latches the chip off when the output drops below 75% of its set value after the soft-start sequence is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. Typical Application
Figure 1. 1.8V Output Regulator (see Table 2, page 12 for BOM)
6 VSEN
FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 Pin Configurations Pin Definitions Pin Number Pin Name Pin Function Description
1 VIN
Input Voltage. Connect to main input power source (battery). Also used to program operating frequency for low input voltage operation. See Table 1.
2 PGOOD
Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a ±10% range of the 0.9V reference. 3E N ENABLE . Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. This is a CMOS inputs whose state is indeterminate if left open.
4 ILIM
Current Limit. A resistor from this pin to GND sets the current limit. 5V OUT Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth transitions during mode changes. When VOUT is expected to exceed VCC, tie this pin to VCC. Output Voltage Sense. The feedback from the output. Used for regulation as well as PGOOD, under-voltage, and over-voltage protection and monitoring. 7S S Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5 µ A current source. 8A GND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin.
9 PGND
Power Ground. The return for the low-side MOSFET driver. Connect to source of low- side MOSFET.
10 LDRV
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET.
11 VCC
VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling).
12 ISNS
Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 13 SW Switching node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain.
14 HDRV
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET.
15 BOOT
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2.
16 FPWM
Forced PWM mode. When logic HIGH, inhibits the regulator from entering hysteretic mode. VIN PGOOD EN ILIM VOUT VSEN SS AGND FAN5234 FPWM BOOT HDRV SW ISNS VCC LDRV PGND QSOP-16 or TSSOP-16 θJA = 112°C/W
FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Recommended Operating Conditions Parameter Min. Typ. Max. Units VCC Supply Voltage: 6.5 V VIN 27 V BOOT, SW, ISNS, HDRV 33 V BOOT to SW 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (T J ) –10 150 °C Storage Temperature –65 150 °C Lead Soldering Temperature, 10 seconds 300 °C Parameter Conditions Min. Typ. Max. Units Supply Voltage VCC 4.75 5 5.25 V Supply Voltage VIN 52 4 V Ambient Temperature (T A 10 85 °C
PRODUCT SPECIFICATION FAN5234 REV. 1.0.10 5/3/04 Electrical Specifications Recommended operating conditions, unless otherwise noted. Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current LDRV, HDRV Open, VSEN forced above regulation point 850 1300 µ A Shut-down (EN=0) 5 15 µ A VIN Current - Sinking VIN pin = input voltage source 10 20 30 µ A VIN Current - Sourcing VIN pin = GND 7 15 20 µ A VIN Current - Shut-down 1 µ A UVLO Threshold Rising VCC 4.3 4.55 4.75 V Falling 4.1 4.27 4.5 V Hysteresis 0.1 0.5 V Oscillator Frequency VIN > 5V 255 300 345 KHz VIN = 0V 510 600 690 KHz Ramp Amplitude, pk–pk VIN = 16V 2 V Ramp Amplitude, pk–pk VIN < 5V 1.25 V Ramp Offset 0.5 V Ramp / VIN Gain VIN > 3V 125 mV/V Ramp / VIN Gain 1V < VIN < 3V 250 mV/V Reference and Soft Start Internal Reference Voltage 0.891 0.9 0.909 V Soft Start current (I SS ) at start-up 5 µ A Soft Start Complete Threshold 1.5 V PWM Converter Load Regulation I OUT from 0 to 3A, VIN from 2 to 24V -1 +1 % VSEN Bias Current 50 80 120 nA VOUT pin input impedance 40 55 65 K Ω Under-voltage Shutdown as % of set point. 2 µ S noise filter 70 75 80 % I SNS Over-Current threshold R ILIM = 68.5K Ω . See Figure 4 115 144 172 µA Over-voltage threshold as % of set point. 2 µ S noise filter 113 120 % Output Driver HDRV Output Resistance Sourcing 8 15 Ω Sinking 3.2 4 Ω LDRV Output Resistance Sourcing 8 15 Ω Sinking 1.5 2.4 Ω PGOOD (Power Good Output) and Control pins Lower Threshold as % of set point, 2 µ S noise filter 86 92 % Upper Threshold as % of set point, 2 µ S noise filter 110 115 % PGOOD Output Low I PGOOD = 4mA 0.5 V Leakage Current V PULLUP = 5V 1 µ A Soft Start Voltage when PGOOD Enabled 1.5 V EN, FPWM Inputs Input High 2 V Input Low 0.8 V
Figure 2. IC Block Diagram in fixed frequency PWM mode or in a hysteretic mode. ational modes and reduced channel-to-channel interaction. Table 1. Converter Operating modes tion on the VIN pin (Table 1).
the SW node and settle out at the value of the output voltage. the mode is changed to PWM on the next clock cycle.
0.9 C SS×
Figure 3. Transitioning between PWM and Hysteretic Mode
Figure 4. Current Limit / Summing Circuits VSEN rises over the higher threshold (5mV above VREF).
- Spread between the two hysteretic thresholds
- Output Inductor and Capacitor ESR
can be disabled by setting the FPWM pin HIGH. The following discussion refers to Figure 4. its operating die temperature below 125°C.
100 R SENSE+()
cycling the VCC voltage or by toggling the EN pin. pulse-skipping circuit is activated and HDRV is inhibited. restored and the over-current circuit resets itself. Figure 7. Over-Current protection waveforms overvoltage protection comparator will force LDRV high. threshold, the OVP comparator is disengaged. resulting in a full soft-start cycle.
8 CLK
PRODUCT SPECIFICATION FAN5234 10 REV. 1.0.10 5/3/04 Setting the Output Voltage The internal reference is 0.9V . The output is divided down by a voltage divider to the VSEN pin (for example, R1 and R2 in Figure 1). The output voltage therefore is: To minimize noise pickup on this node, keep the resistor to GND (R2) below 2K. We selected R2 at 1.82K. Then choose R5: Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the ripple current to be somewhere from 15% to 35% of the nominal current. At light load, the ripple current also determines the point where the converter will automatically switch to hysteretic mode of operation (I MIN) to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. where ∆I is the inductor ripple current, which we will choose for 20% of the full load current and ∆V OUT is the maximum output ripple voltage allowed. for this example we'll use: VIN = 20V , VOUT = 1.8V FSW = 300KHz. therefore L ≈ 8µH Output Capacitor Selection The output capacitor serves two major functions in a switch- ing power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor require- ments are usually dictated by ESR, Inductor ripple current (∆I) and the allowable ripple voltage (∆V). For our example, In addition, the capacitor's ESR must be low enough to allow the converter to stay in regulation during a load step. The rip- ple voltage due to ESR for the converter in Figure 1 is 100mV P-P. Some additional ripple will appear due to the capacitance value itself: which is only about 1.5mV for the converter in Figure 1 and can be ignored. The capacitor must also be rated to withstand the RMS cur- rent which is approximately 0.3 X (∆I), or about 210mA for our example. High frequency decoupling capacitors should be placed as close to the loads as physically possible. Input Capacitor Selection The input capacitor should be selected by its ripple current rating. The input RMS current at maximum load current (I is: where the converter duty cycle; , which for the circuit in Figure 1, with VIN=6 calculates to: Power MOSFET Selection Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND ) losses. In typical applications, the FAN5234 converter's output volt- age is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should be therefore be selected to min- imize conduction losses, thereby selecting a MOSFET with low R DS(ON). In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and it's conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge. High-Side Losses: Figure 8 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing V GS vs. time with a constant current charging the gate. The x-axis therefore is also representative of gate charge (QG) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either speci- fied or can be derived from MOSFET datasheets. 0.9V VOUT 0.9V– ∆I2 I MIN– ∆VOUT L VIN VOUT– VOUT VIN ESR ∆V ESR MAX() ∆V ∆I IRMS IL DD 2–= (14) D VOUT VIN IRMS 1.6A=
Table 2. BOM For 1.8V, 3.5A regulator (Figure 1) amounts of energy at high rate and are noise generators. back functions are sensitive to noise. A multi-layer printed circuit board is recommended. into smaller islands of common voltage levels. Interconnect Systems, or micro-vias on these signals. the discretion of the designer. special considerations in PWB design and manufacturing. completely before applying power.
FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 13 Mechanical Dimensions 16-Pin QSOP A .053 .069 1.35 1.75 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .004 .010 0.10 0.25 .012 0.30B .008 0.20 C .007 .010 0.18 0.25 E .150 .157 3.81 3.99 e .228 .244 5.79 6.19 –––– H .025 BSC 0.63 BSC K L .016 .050 0.41 1.27 0° 8° 0° 8°φ D .189 .197 4.80 5.00 16 9 D A1B e L C φ E AK H
PRODUCT SPECIFICATION FAN5234 14 REV. 1.0.10 5/3/04 Mechanical Dimensions 16-Pin TSSOP 6.4 5.0 ± 0.1 4.4 ± 0.1 7.72 TYP4.16 TYP. (1.78 TYP)
0.42 TYP
0.65 TYP
0.25 SEATING PLANE SEE DETAIL A DETAIL A GAGE PLANE LAND PATTERN RECOMMENDATION 0°–8° 0.6 ± 0.1 -A- -B-
0.13 A B CMS S
-C- 3.2 (0.90) 0.10±0.05 TYP
1.1 MAX TYP
PIN #1 IDENT. DIMENSIONS METRIC ONLY 0.2 ALL LEAD TIPS ALL LEAD TIPS CB A 0.1 TYPICAL, SCALE: 40X 816 C
PRODUCT SPECIFICATION FAN5234 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/3/04 0.0m 004 Stock#DS30005234 2004 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
Part Number Temperature Range Package Packing FAN5234QSC -10°C to 85°C QSOP-16 Rails FAN5234QSCX -10°C to 85°C QSOP-16 Tape and Reel FAN5234MTC -10°C to 85°C TSSOP-16 Rails FAN5234MTCX -10°C to 85°C TSSOP-16 Tape and Reel