FAN5182_08 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
Selectable 1-, 2-, or 3-Phase Operation at up to 1MHz per Phase Accuracy: 1% Externally Adjustable 0.8V to 5V Output from a 12V Supply Logic-Level PWM Outputs for Interface to External High-Power Drivers Active Current Balancing Between all Phases Built-in Power-Good / Crowbar Functions Programmable Over-Current Protection with Adjustable Latch-Off Delay
Applications
Auxiliary Supplies DDR Memory Supplies Point-of-Load Supplies
Description
The FAN5182 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12V main supply into a high- current, low-voltage supply for use in point-of-load (POL) applications. It uses a multi-loop PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for regulator size and efficiency. The phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for construction of up to three complementary, interleaved buck switching stages. The FAN5182 provides accurate and reliable over- current protection and adjustable current limiting. The FAN5182 is specified over the commercial temperature range of 0°C to +85°C and is available in a 20-lead Quarter-Size Outline Package (QSOP).
Ordering Information
Part Number Temperature Range Packag e Packing Method Quantity per Reel FAN5182QSCX_NA3E229 0°C to 85°C QSOP-20L Tape and Reel 2500 All packages are lead free per JEDEC: J-STD-020B standard.
Figure 1. Block Diagram
Figure 2. Pin Assignments 1 VCC Supply Voltage for the Device. 2 FBRTN Feedback Return. Voltage error amplifier refe rence for remote sensing of the output voltage. resistor divider between the output and FBRTN connected to this pin sets the output voltage. This pin is also the reference point for the power-good and crowbar comparators. 4 COMP Error Amplifier Output and Compensation Pin.
7 DELAY
current latch-off delay time. sets the oscillator frequency of the device.
10 ILIMIT
high-side and low-side outputs should go low. the current-sense amplifier. Connect this pin to the common point of the output inductors. average inductor currents to measure the total output current. determine the gain of the current sense amplifier. 14 GND Ground. All internal biasing and logic output signals are referenced to this ground. SW pins of unused phases s hould be connected to ground. PWM2 to ground for 1-phase operation.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 4 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Unless otherwise noted, all voltages are referenced to GND. Symbol Parameter Min. Max. Unit VCC -0.3 +15 V FBRTN -0.3 +0.3 V EN, DELAY, ILIMIT, RT, PWM1-PWM3, COMP -0.3 5.5 V SW1-SW3 -5 +25 V VCC All Other Inputs and Outputs -0.3 V CC + 0.3 V TJ Operating Junction Temperature 0 +125 °C TSTG Storage Temperature -65 +150 °C TL Lead Soldering Temperature (10 Seconds) +300 °C TLI Lead Infrared Temperature (15 Seconds) +260 °C ΘJC Thermal Resistance Junction-to-Case 38 °C/W ΘJA Thermal Resistance Junction-to-Ambient (1) 90 °C/W Note: 1. Junction-to-ambient thermal resistance, ΘJA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics. It is measured with t he device mounted on a board of FR-4 material, 0.063inch thickness, no copper plane, and zero air flow. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage Range 10.8 12.0 13.2 V TA Operating Ambient Temperature 0 +85 °C
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 5 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Electrical Characteristics
VCC = 12V, FBRTN = GND, • indicates specifications over operating ambient temperature range. (2) Symbol Parameter Conditions Min. Typ. Max. Units Oscillator fOSC Frequency Range • 0.25 3.00 MHz RT = 332kΩ, 3-phase • 155 200 245 TA = 25°C, RT = 154kΩ, 3-phase • 155 400 245 TPHASE Frequency Variation TA = 25°C, RT = 100kΩ, 3-phase • 155 600 245 kHz VRT Output Voltage R T = 100kΩ to GND • 2.0 V VRAMPADJ RAMPADJ Output Voltage RAMPADJ - FB - 2KΩ x IRAMPADJ (with IRAMPADJ set to 20µA) • -50 +50 mV IRAMPADJ RAMPADJ Input Current Range (3) 0 100 µA Voltage Error Amplifier VOL Output Voltage Low 0.3 V VOH Output Voltage High 3.1 V VFB Accuracy (Referenced to FBRTN) FAN5182_NA3E229 1% • 792 800 808 mV IFB Input Bias Current FB = 800mV • -4 ±1 +4 µA ΔVFB Line Regulation V CC = 10V to 14V 0.05 % IFBRTN FBRTN Current • 100 140 µA IO(ERR) Output Current FB forced to V OUT - 3% 500 µA DC Gain (3) 87 dB GBW(ERR) Gain Bandwidth Product (3) COMP = FB 20 MHz Slew Rate (3) C COMP = 10pF 10 V/ µs Current-Sense Amplifier VOS(CSA) Offset Voltage CSSUM-CSREF (See Figure 3) • -5.5 +5.5 mV IBIAS(CSSUM) Input Bias Current • -50 +50 nA DC Gain (3) 70 dB GBW(CSA) Gain Bandwidth Product (3) 10 MHz Slew Rate (3) C CSCOMP = 10pF 10 V/ µs Input Common-Mode Range C SSUM & CSREF 0 V CC-2.5 V VOL Output Voltage Low 0.1 V VOH Output Voltage High V CC-2.5 V ICSCOMP Output Current 500 µA Current-Balance Circuit VSW(X)CM Common-Mode Range (3) -600 +200 mV Rsw(X) Input Resistance SW(X) = 0V • 20 30 40 k Ω ISW(X) Input Current SW(X) = 0V • 4 7 10 µA ΔISW(X) Input Current Matching SW(X) = 0V • -7 +7 % ΔVOS Match Offset Voltage Matching (Difference between phases) FAN5182_NA3E229 8 mV
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 6 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Electrical Characteristics (Continued) VCC = 12V, FBRTN = GND, • indicates specifications over operating ambient temperature range. (2) Symbol Parameter Conditions Min. Typ. Max. Units Current-Limit Comparator VILIMIT(NM) Output Voltage: Normal Mode EN > 2.0V, R ILIMIT = 250kΩ • 2.9 3.0 3.1 V VILIMIT(SD) Output Voltage: In Shutdown EN < 0.8V, I ILIMIT = -100µA • 400 mV IILIMIT(NM) Output Current: Normal Mode EN > 2.0V, R ILIMIT = 250kΩ 12 µA Maximum Output Current • 60 µA VCL Current Limit Threshold V CSREF - VCSCOMP , RILIMIT = 250kΩ 105 125 145 mV Current Limit Setting Ratio V CL/IILIMIT 10.4 mV/µA VDELAY(NM) Delay Normal Mode Voltage R DELAY = 250kΩ 2.9 3.0 3.1 V VDELAY(OC) Delay Over-Current Threshold R DELAY = 250kΩ 1.7 1.8 1.9 V tDELAY Latch-Off Delay Time (3) R DELAY = 250kΩ, CDELAY = 12nF 1.5 ms Soft-Start IDELAY(SS) Output Current, Soft-Start Mode During Start-up Delay < 2.4V • 15 20 25 µA tDELAY(SS) Soft-Start Delay Time (3) R DELAY = 250kΩ, CDELAY = 12nF 500 µs Enable Input VIL(EN) Input Low Voltage • 0.8 V VIH(EN) Input High Voltage • 2.0 V Input Hysteresis Voltage 100 mV IIN(EN) Input Current • -1 +1 µA Power-Good Comparator VPWRGD(UV) Under-Voltage Threshold Relative to FBRTN • 600 660 720 mV VPWRGD(OV) Over-Voltage Threshold Relative to FBRTN • 880 940 1000 mV VOL(PWRGD) Output Low Voltage I PWRGD(SINK) = 4mA • 225 400 mV Power-Good Delay Time 200 ns VCROWBAR Crowbar Trip Point Relative to FBRTN • 0.970 1.050 1.105 V Crowbar Reset Point Relative to FBRTN • 550 650 750 mV tCROWBAR Crowbar Delay Point (3) Over-voltage to PWM Going Low 400 ns PWM Outputs VOL(PWM) Output Low Voltage I PWM(SINK) = 400µA • 160 500 mV VOH(PWM) Output High Voltage I PWM(SOURCE) = -400µA • 4.0 5 V Supply DC Supply Current • 5 10 mA VUVLO UVLO Threshold Voltage V CC rising • 6.5 6.9 7.3 V UVLO Hysteresis • 0.7 0.9 1.1 V Notes: 2. Limits at operating temperature extr emes are guaranteed by design, characterization, and statistical quality control. 3. Guaranteed by design, not tested in production.
Figure 7. 1.8V, 55A Application Circuit
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 9 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Theory of Operation The FAN5182 combines a multi-loop, fixed-frequency PWM control with multi-phase logic outputs for use in 1-, 2-, and 3-phase synchronous buck point-of-load power supplies. Multi-phase operation is important for producing the high current and low voltage demanded by auxiliary supplies in desktop computers, workstations, and servers. Handling high current in a single-phase converter places high thermal stress on components, such as inductors and MOSFETs, and is not preferred. The multi-loop control of the FAN5182 ensures a stable, high-performance topology for: Balancing current and thermal between/among phases Fast response at the lowest possible switching frequency and output decoupling Reducing switching losses due to low-frequency operation Tight line and load regulation Reducing output ripple due to multiphase cancellation Better noise immunity to facilitate PCB layout Start-up Sequence During start-up, the number of operational phases and their phase relationship are determined by the internal circuitry that monitors the PWM outputs. Normally, the FAN5182 operates as a 3-phase PWM controller. Grounding the PWM3 pin programs the FAN5182 for 1- or 2-phase operation. When the FAN5182 is enabled, the controller outputs a voltage on PWM3, which is approximately 675mV. An internal comparator checks this pin's voltage versus a threshold of 300mV. If the PWM3 pin is grounded, it is below the threshold and the phase 3 is disabled. The output resistance of the PWM pin is approximately 5k Ω during this detection period. Any external pull-down resistance connected to the PWM pin should not be less than 25k Ω to ensure proper operation. PWM1 and PWM2 are disabled during the phase-detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM3 output is not grounded, the 5k Ω resistance is disconnected, and PWM3 switches between 0V and 5V. If the PWM3 output is grounded, the controller operates in 1- and/or 2-phase. The PWM outputs logic-level signals to interface with external gate drivers, such as the FAN5109. Since each phase is able to operate close to 100% duty cycle, more than one PWM output can be on at the same time. Master Clock Frequency The clock frequency is set by an external resistor connected from the RT pin to ground. The frequency / resistor relationship follows the graph in Figure 4. To determine the frequency per phase, divide the clock frequency by the number of phases in use. NOTE: The exception is single-phase operation, in which the clock frequency must be set twice the single- phase frequency required. Output Voltage Differential Sensing The FAN5182 uses a differential low-offset voltage error amplifier to maintain ±2% differential sensing accuracy over temperature. The output voltage is sensed between the FB and FBRTN pins. The power supply output connects to the FB pin through a resistor divider and the FBRTN pin should be connected directly to the remote sense ground. The internal precision reference is referenced to FBRTN, which has a typical current of 100µA to allow accurate remote sensing. The internal error amplifier compares the precision reference to the FB pin to regulate the output voltage. Output Current Sensing The FAN5182 uses a current sense amplifier (CSA) to monitor the total output current for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured according to the objectives of the system design: Output inductor DCR sensing without a thermistor (for lowest cost) Output inductor DCR sensing with a thermistor (for improved accuracy and moderate cost) Discrete resistor sensing (for best accuracy) The positive input of the CSA is connected to the CSREF pin and the CSREF is tied to the power supply output. The inverting input of the CSA, CSSUM, is the summing node of the load current sense through sensing elements (such as the switch node side of the output inductors). The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. The current information is given as the difference between CSREF and CSCOMP. This “difference” signal is used as a differential input for the current limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have low-input offset voltage. The CSA gain is determined by external resistors, so it can be set very accurately.
the internal 20µA soft-start current. clamps the COMP voltage to 2V. the maximum normal mode COMP voltage. response when the input power supply is switched off. Figure 10. Shutdown Waveforms reset threshold of approximately 650mV. output as the reverse current builds up in the inductors. protecting the load from damage. and holds the ILIMIT pin at ground. connected to the OD pins of the FAN5109 drivers. output capacitors through the inductors. minimize any potential spurious noise paths. WARNING: Do not connect PWM2 to ground. a two-phase controller and PWM2 may be switching. Design” does not apply to voltage-mode designs.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 12 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Application Information
Design parameters for a typical high-current DC/DC buck converter, as shown in Figure 7, follow. This is a multiphase, current-mode control implementation. The equations shown are interdependent and must be followed in the sequence shown. For other implementations, adjust the design requirements. NOTE: A complete MathCAD ® control design program is available from Fairchild upon request. Design Requirements: Input voltage (VIN) = 12V Output voltage (VOUT) = 1.8V Duty cycle (D) = 0.15 Output current IO = 55A Maximum output current (ILIM) = 110A Number of phases (n) = 3 Switching frequency per phase (fSW) = 250kHz Setting the Clock Frequency The FAN5182 uses fixed-frequency control architecture. The frequency is set by an external timing resistor (R T). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and the input and output capacitors. With n = 3 for three phases, a clock frequency of 750kHz sets the switching frequency, f SW, of each phase to 250kHz, which represents a practi cal trade-off between the switching losses and the size s of the output filter components. Equation 1 shows that to achieve a 750kHz oscillator frequency, the correct value for R T is 255k Ω. Alternatively, the value for RT can be calculated using: Ω=Ω−××= Ω−××= K256K27pF7.4kHz2503 K27pF7.4fn T SW T (1) where 4.7pF and 27k Ω are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. The closest standard 1% value for this design is 255kΩ. NOTE: For a single-phase application, set the oscillator frequency to two times the required per-phase switching frequency. This can be done buy substituting “2 x f SW” for “fSW” in Equation 1. Soft-Start and Current-Limit Latch-off Delay Time Because the soft-start and curr ent-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set C DLY for the soft-start ramp. This ramp is generated with a 20µA internal current source. The value of R DLY has a second-order impact on the so ft-start time because it sinks part of the current source to ground. As long as RDLY is greater than 200kΩ, this effect is minor. The value for CDLY can be approximated using: REF SS DLY REFDLY V t VA20C ×⎟⎟ ×−= μ (2) where t SS is the desired soft-start time. Assuming an RDLY of 390kΩ and a desired soft-start time of 3ms, CDLY is 71nF. The closest standard value for C DLY is 68nF. Once C DLY is chosen, R DLY can be calculated for the current-limit latch-off time, using: DLY DELAYDLY C t96.1R ×= (3) If the result for R DLY is less than 200k Ω, a smaller soft- start time should be considered, by recalculating the equation for C DLY, or a longer latch-off time should be used. R DLY should never be less than 200k Ω. In this example, a delay time of 9ms results in R DLY = 259k Ω. The closest standard 1% value is 261kΩ. Inductor Selection The inductance determines the ripple current in the inductor. Small inductance l eads to high ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs and vice versa. In any multiphase converter, it's recommended to design the peak-to-peak inductor ripple current to be less than 50% of the maximum inductor DC current. Equation 4 shows the relationship among the inductance, oscillator frequency, and peak-to-peak ripple current: Lf )D1(VI SW OUTR −×= (4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage: RIPPLESW xOUT Vf ))Dn(1(RVL × where RX is the ESR of output bulk capacitors. Solving Equation 5 for a 20mV peak-to-peak output ripple voltage and 3mΩ RX yields: nH277mV10kHz250 If the resulting ripple voltage is too low, the inductance can be reduced until the desired ripple voltage is achieved. In this example, a 600nH inductor is a good starting point that produces a calculated ripple current of 6.6A. The inductor should not saturate at the peak current of 21.6A and should be able to handle the total power dissipation created by the copper and core loss. Another important factor in the inductor design is the Direct Conversion Receiver (DCR), which is used for measuring the phase current. A large DCR can cause excessive power losses, whereas too small DCR can increases measurement error. For this design, a DCR of 1.4mΩ was chosen.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 13 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Designing an Inductor Once the inductance and DCR are known, the next step is to either design an inductor or find a suitable standard inductor if one exists . Inductor design starts with choosing appropriate core material. Some candidate materials that have low core loss at high frequencies are powder cores (e.g. Kool-Mµ® from Magnetics, Inc. or from Micrometals) and gapped soft ferrite cores (e.g. 3F3 or 3F4 from Philips). Powdered iron cores have higher core loss and are used for low- cost applications. The best choice for a core geometry is a closed-loop type, such as a potentiometer core, a PQ/U/E core, or a toroid core. Some useful references for magnetics design are: Magnetic Designer Software Intusoft (www.intusoft.com) Designing Magnetic Components for High- Frequency DC-DC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008. Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high-power applications upon request: BI Technologies, 714-447-2345 www.bitechnologies.com Taiyo Yuden (USA), 408-573-4150 www.taiyo-yuden.com Output Current Sense The output current can be measured by summing the voltage across each inductor and passing the signal through a low-pass filter. The CS amplifier is configured with resistors R PH(X) (for summing the voltage), and R CS and CCS (for the low-pass filter). The output current IO is set by the following equations: L DRP CS )x(PH O R V R R I ×= (7) CSL RR LCcs ×≥ (8) where: RL is the DCR of the output inductors, VDRP is the voltage drop from CSCOMP to CSREF. When load current reaches its limit, V DRP is at its maximum (V DRPMAX). V DRPMAX can be in the range of 100mV to 200mV. In this example, it is 110mV. Designers have the flexibility of choosing either R CS or RPH(X). It is recommended to select R CS equal to 100kΩ, and then solve for R PH(X) by rearranging Equation 7 as: DRPMAX LIM CSL)x(PH V IRRR ××= (9) Ω=×Ω×Ω= k140mV110 A110k100m4.1R )x(PH (10) WARNING: The parallel combination of the all the R ph resistors must be greater than 30k Ω to ensure that the current sense amplifier does not saturate. Next, use Equation 8 to solve for CCS: nF28.2k100m4.1 nH320Ccs ≥Ω×Ω≥ (11) Choose the closest standard value that is greater than the result given by Equation 8. This example uses a C CS value of 5.6nF. Output Voltage FAN5182 has an internal FBRTN referred 800mV reference voltage VREF. The output voltage can be set by using a voltage divider consisting of resistors R and RB2: REF 2B1B OUT VR )RR(V ×+= (12) Rearranging Equation 12 to solve R B2 and assuming a 1%, 1kΩ resistor for RB1 yields Ω=Ω×−= ×−= k25.1k1V8.0 V8.0V8.1R RV VVR FB FBOUT (13) The closest standard 1% resistor value for R B2 is 1.24kΩ. Power MOSFETs For this example, one high-side and one low-side N-channel power MOSFET per phase have been selected. The main selection parameters for power MOSFETs are V GS(TH), QG, CISS, CRSS, and R DS(ON). The minimum gate-drive voltage (the supply voltage to the FAN5109) dictates whether standard threshold or logic- level threshold MOSFETs can be used. With V GATE ~10V, logic-level threshold MOSFETs (V GS(TH) < 2.5V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With good current balance among phases, the current in each low-side MOSFET is the output current divided by the total number of the low-side MOSFETs (n SF). Since conduction loss is dominant in low-side MOSFET, the following expression can represent total power dissipation in each synchronous MOSFET in terms of the ripple current per phase (I R) and the total output current (IO): )SF(DS SF R SF O SF Rn In n I)D1(P ×⎥ ⎛×−= (14)
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 14 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Knowing the maximum output current and the maximum allowed power dissipation, determine the required R DS(ON) for the MOSFET. For example, with D-PAK MOSFETs operating up to ambient temperature of 50°C, a safe limit for PSF is around 1W to 1.5W at 120°C junction temperature. Ther efore, in this example, R DS(SF) (per MOSFET) < 7.5m Ω. This R DS(SF) is typically measured at junction temperature of about 120°C. In this example, select a lower-side MOSFET with 4.8m Ω at 120°C. WARNING: The R DS of the bottom FET is also used to measure the current flowing in the phase. This is used for current balance and for the current-feedback loop. Using a FET with too low an R DS can result in poor current balance and too large a ramp resistor calculation in Equation 18. Another important consideration for choosing the synchronous MOSFET is the input and feedback capacitance. The ratio of feedback to input capacitance must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the non-overlap dead time of the MOSFET driver (40ns typical for the FAN5109). The output impedance of the driver is approximately 2 Ω and the typical MOSFET input gate resistances are about 1Ω to 2 Ω; therefore, the total gate capacitance should be less than 6000pF. In the event there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000pF. The high-side (main) MOSFET power dissipation consists of two elements: conduction and switching losses. The switching loss is related to the main MOSFET’s turn-on and turn-off time and the current and voltage being switched. Based on the main MOSFET’s switching speed (rise and fall time that the gate driver can offer) and MOSFET input capacitance, the following expression provides the approximate switching loss for each main MOSFET: ISS MF G MF OCC SW)MF(S Cn nRn where: nMF is the total number of main MOSFETs; RG is the total gate resistance (2 Ω for the FAN5109 and about 1 Ω for typical logic level N-channel MOSFETs, total RG = 3Ω); CISS is the input capacitance of the main MOSFET. Note that adding more main MOSFETs (n MF) does not help lower the switching loss for each main MOSFET; it can only reduce conduction loss. The most efficient way to reduce switching loss is to use low-gate charge / capacitance devices. The conduction loss of the main MOSFET is given by: )MF(DS MF R MF O )MF(C Rn In n IDP ×⎥ ⎛×= (16) where RDS(MF) is the on resistance of the main MOSFET. Typically, for main MOSFETs, a low gate charge (C ISS) device is preferred, but low gate charge MOSFETs usually have higher on resistance. Select a device that meets total power dissipation around 1.5W for a single D-PAK MOSFET. In this example, a FDD6296 is selected as the main MOSFET (three total; nMF = 3), with a CISS = 1440pF, and RDS(MF) = 9m Ω (at TJ = 120°C). A FDD8896 is selected as the synchronous MOSFET (three total; nSF = 3), with C ISS = 2525pF and R DS(SF) = 5.4m Ω (at T J = 120°C). The synchronous MOSFET C ISS is less than 6000pF. Solving for the power dissipation per MOSFET at I O = 55A and I R = 6.6A yields 1.56W for each synchronous MOSFET and 1.29W for each main MOSFET. These numbers comply with the power dissipation limit of around 1.5W per MOSFET. One more item that needs to be considered is the power dissipation in the driver for each phase. The gate-drive loss is described in terms of the Q G for the MOSFETs and is given by the following equation: CCCCGSFSFGMFMF SW DRV VI)QnQn(n2 fP ×⎥⎦ where: QGMF is the total gate charge for each main MOSFET, QGSF is the total gate charge for each synchronous MOSFET. ICC × VCC in Equation 17 represents the driver's standby power dissipation. For the FAN5109, the maximum dissipation should be less than 400mW. In this example, with I CC = 5mA, Q GMF = 25nC, and Q GSF = 50nC; there is 285mW in each driver, which is below the 400mW dissipation limit. See the Thermal Information table in the FAN5109 datasheet for details. Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of phase-current balance, stability, and transient response. The following expression is used to determine the optimum value: R)SF)(ON(DSD R R CRA3 LAR ××× ×= (18) Ω=×Ω×× ×= k356pF5m4.253 nH3202.0RR (19) where: AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS(ON)(SF) is the equivalent low-side MOSFET on resistance, CR is the internal ramp capacitor value. The closest standard 1% resistor value is 332k Ω.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 15 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller WARNING: The ramp resistor should be less than 1M Ω to ensure that board contaminates don’t affect the ramp. If the calculated value is greater than 1M Ω, verify that the RDS of the bottom FET is not too low. Internal ramp voltage magnitude can be calculated by: SWRR OUTR R fCR V)D1(AV ×× ×−×= (20) mV686kHz250pF5K357 ×−×= (21) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. If the ramp is made smaller, thermal balance improves, but transient response and stability degrade. The factor of three in the denominator of Equation 18 sets a ramp size with optimal balance for good stability, transient response, and thermal balance. Ramp Resistor Selection for Voltage-Mode Control When configured for single-phase voltage-mode control (SW pin grounded), the ramp resistor is selected to produce a fixed-ramp voltage. For example, to create a ramp voltage of 1V, the following equation is used: () 2000dCfV VVV2.0R VrRSWIN OUTREFIN R −××× ×−×= (22) where: RR is the ramp resistor connected between VIN and FAN5182 RAMPADJ pin 9 0.2 is the internal current transfer ratio between RRAMPADJ and the PWM ramp current source(s) VIN is the input voltage (12V) VREF is the internally generated reference (0.8V) VOUT is the output voltage CR is the internal PWM ramp capacitor, 5pF fsw is the switching frequency defined as (Master Osc / 2) for single- and dual-phase operation and (Master Osc / 3) for three-phase operation dVr is the target peak ramp voltage; 1V is a typical target voltage. Current Limit Set Point The current-limit threshold is set with a 3V source V LIM across RLIM with a gain of 10.4mV/µA (ALIM). RLIM can be found using: DRPMAX LIMLIM LIM V VAR = (23) WARNING: Be sure to take into account the peak current ripple current and the increase in inductor DCR at high temperatures if the inductor is not temperature compensated. If R LIM is greater than 500k Ω, the actual current-limit threshold may be lower than the intended value. Some adjustment for R LIM may be needed. Here, I LIM is the average current limit for the output of the supply. In this example, using the V DRPMAX value of 110mV from Equations 7 and 8 and choosing a peak current limit of 110A for I LIM results in RLIM = 284kΩ, for which 287kΩ is chosen as the nearest 1% value. The per-phase current limit is determined by: I RA VVV I R )MAX(DSD BIASR)MAX(COMP PHLIM +× ≅ (24) Closed-Loop Compensation Design NOTE: This section does not apply in a voltage-mode control configuration. Optimum compensation assures the best possible load regulation and transient response of the regulator. The target of the compensation design is to achieve reasonably high control bandwidth with sufficient phase and gain margin. The power stage of the synchronous buck converter consists of two poles and one zero. A two-pole, one- zero compensator of the voltage error amplifier is adequate for proper compensation if the output bulk capacitors are electrolytic types (low ESR zero). Equations 25-27 are able to yield an approximate starting point for the design. To further optimize the design, some bench adjustments may be necessary. () ⎟ ×+⎟⎟ ⎛ × ×××= RDSDL OUT R X XX A ARV V Rn R RCC (25) XSW DSD XOUT R XX A RCRf2 RA Rn L V V RC RR (26) ASW FB Rfn2C ×××= (27) If CX is 6000µF (five 1200µF capacitors in parallel) with an equivalent ESR of 3m Ω, the equations above give the following compensation values: CA = 1.33nF, RA= 6.05kΩ, CFB = 110pF (28) Selecting the nearest standard value for each of these components yields: CA = 1.2nF, RA = 6.04kΩ, and CFB = 100pF (29) As mentioned above, this compensation design scheme is typically good for applicati ons using electrolytic type capacitors, where the capacitor ESR zero can roughly cancel one of the power stage poles. However, for all ceramic capacitor types of applications, since the capacitor ESR zero can be very high, a three-pole, two- zero compensator should be used.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 17 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller PCB Layout Guidelines General Recommendations To achieve the best performance, a PCB with at least four layers is recommended. When designing the layout, keep in mind that each square unit of 1-ounce copper has resistance of ~0.53mΩ at room temperature. Whenever high currents must be routed to a different PCB layers, vias should be used properly to create several parallel current paths so the resistance and inductance introduced by these current paths are minimized and via current rating is not exceeded. If critical signal traces must be routed close to power circuitry, a signal ground plane must be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground island should be used around and under the FAN5182 as a reference for the components associated with the controller. The analog ground should be connected to the power ground at a single point. The components around the FAN5182 should be close to the controller with short traces. The output capacitors should be placed as close as possible to the load. If the load is distributed, the capacitors should also be distributed in proportion to the respective load. Power Circuitry Recommendations The PCB layout starts with high-frequency power component placement. Try to minimize stray inductance of the MOSFET half bridge, which is composed of the input capacitors and top and bottom MOSFETs. A good practice is to use short and wide traces or copper pours to minimize the inductance in the MOSFET half bridge. Failure to do so can lead to severe phase node ringing. A snubber circuit is always recommended to partly kill the phase node switching noise. Whenever using a power dissipating component; for example, a power MOSFET that is soldered to the PCB; the proper use of vias, both directly on the mounting pad and immediately surrounding the mounting pad is recommended. Make a mirror image of the power pad being used on the component side to heat sink the MOSFETs on the opposite side of the PCB. Use large copper pour for high-current traces to lower the electrical impedance and help dissipate heat. Do not make the switching node copper pour unnecessarily large, since it could radiate noise. An undisturbed solid power ground plane should be used as one of the inner layers. Signal Circuitry Recommendations The output voltage is sensed from the FB and the FBRTN pins. To avoid differential mode noise pickup in these differential sensed traces, the loop area between the FB and FBRTN traces should be minimized. In other words, the FB and FBRTN traces should be routed adjacent to each other with minimum spacing on top of the analog / power ground plane back to the controller. The signal traces connecting to the switch nodes should be tied as close as possible to the inductor pins. The CSREF sense trace should be connected to the second nearest inductor pin to the controller. Detailed step-by-step PCB layout instructions are available from Fairchild upon request.
Figure 12. 20-Pin Quarter-Size Outline Package (QSOP) the warranty therein, which covers Fairchild products.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5182 • Rev. 1.1.3 19 FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller