FAN5094

FAN5094 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• Programmable output from 1.100V to 1.850V in 25mV steps using an integrated 5-bit DAC
• Two interleaved synchronous phases per IC for maximum performance
• Up to 4 phase power system
• Built-in current sharing between phases and between ICs
• Frequency and phase synchronization between ICs
• Remote sense and Programmable Active Droop™
• High precision voltage reference
• High speed transient response
• Programmable frequency from 200KHz to 2MHz
• Adaptive delay gate switching
• Integrated high-current gate drivers
• Integrated Power Good, OV , UV , Enable/Soft Start functions
• Drives N-channel MOSFETs
• Operation optimized for 12V operation
• High efficiency mode at light load
• Overcurrent protection using MOSFET sensing
• 28 pin TSSOP package

Applications

• Power supply for Pentium IV
• Power supply for Athlon
• Power supply for Ultrasparc™
• VRM for Pentium IV processor
• Programmable step-down power supply

Description

The FAN5094 is a synchronous multi-phase DC-DC controller IC which provides a highly accurate, programmable output voltage for all high-performance processors. Two interleaved synchronous buck regulator phases with built-in current sharing operate 180 out of phase to provide the fast transient response needed to satisfy high current applications while minimizing external components. FAN5094s can be paralleled while maintaining both frequency and phase synchronization and ensuring current sharing in a high-power system. The FAN5094 features remote voltage sensing, Programmable Active Droop and advanced response for optimal converter transient response with minimum output capacitance. It has integrated high-current gate drivers with adaptive delay gate switching, eliminating the need for external drive devices. These make it possible to create power supplies running at a switching frequency as high as 4MHz, for ultra-high density. The FAN5094 uses a 5-bit D/A converter to program the output voltage from 1.100V to 1.850V in 25mV steps with an accuracy of 0.5%. The FAN5094 uses a high level of integration to deliver load currents in excess of 150A from a 12V source with minimal external circuitry. The FAN5094 also offers integrated functions including Power Good, Output Enable/Soft Start, under-voltage lockout, over- voltage protection, and current limiting with independent current sense on each phase. It is available in a 28-pin TSSOP package. Block Diagram +12V +12V +12V +12V FAN5094 VFB Processor PHASE CLK ISHR FAN5094 VFB PHASE CLK ISHR VFB FAN5094 Multi-Phase Interleaved Buck Converter

FAN5094 PRODUCT SPECIFICATION REV. 1.0.2 5/13/02 Pin Assignments Pin Definitions Pin Number Pin Name Pin Function Description 1-5 VID0-4 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1.

6 CLK

Clock. When PHASE is high, this pin puts out a clock signal synchronized 180 out of phase with the internal master clock. When PHASE is low, this pin is an input for a synchronizing clock signal.

7 BYPASS

5V Rail. Bypass this pin with a 0.1 µ F ceramic capacitor to AGND.

8 AGND

Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops.

9 LDRVB

Low Side FET Driver for B. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5”.

10 GNDB

Ground B. Ground-side current sense pin. Connect directly to low-side MOSFET source, or to sense resistor ground.

11 ISNSB

Current Sense B. Sensor side of current sense. Attach to low-side MOSFET drain, or to source side of sense resistor.

12 SWB

High side driver source and low side driver drain switching node B. Gate drive return for high side MOSFET, and negative input for low-side MOSFET current sense.

13 HDRVB

High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5”.

14 BOOTB

Bootstrap B. Input supply for high-side MOSFET.

15 BOOTA

Bootstrap A. Input supply for high-side MOSFET.

16 HDRVA

High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5”.

17 SWA

High side driver source and low side driver drain switching node A. Gate drive return for high side MOSFET, and negative input for low-side MOSFET current sense.

18 ISNSA

Current Sense A. Sensor side of current sense. Attach to low-side MOSFET drain, or to source side of sense resistor. FAN5094 VID0 VID1 VID2 VID3 VID4 BYPASS AGND CLK LDRVB GNDB ISNSB SWB VFB RT ENABLE/SS DROOP/E* ISHR PHASE PWRGD VCC LDRVA GNDA ISNSA SWA HDRVB BOOTB HDRVA BOOTA

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 Absolute Maximum Ratings

19 GNDA

Ground A. Ground-side current sense pin. Connect directly to low-side MOSFET source, or to sense resistor ground.

20 LDRVA

Low Side FET Driver for A. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5”.

21 VCC

VCC. Internal IC supply. Connect to system 12V supply, and decouple with a 0.1 µ F ceramic capacitor.

22 PWRGD

Power Good Flag. An open collector output that will be logic LOW if the output voltage is not within +/-5% of the nominal output voltage setpoint.

23 PHASE

Phase Control. Connecting this pin to bypass causes a synchronized clock signal to appear on CLK. Connecting this pin to ground allows the CLK pin to accept a clock signal for synchronization.

24 ISHR

Current Share. Connecting this pin to the ISHR pin of another FAN5094 enables current sharing.

25 DROOP/E*

Droop Control/E*-mode Control. A resistor from this pin to ground sets the amount of droop by controlling the gain of the current sense amplifier. Connecting this pin to bypass turns off Phase A.

26 ENABLE/SS

Output Enable. A logic LOW on this pin will disable the output. An internal current source allows for open collector control. This pin also doubles as soft start. 27 RT Frequency Set. A resistor from this pin to ground sets the switching frequency. See Apps section.

28 VFB

Voltage Feedback. Connect to the desired regulation point at the output of the converter. Parameter Min. Typ. Max. Units Supply Voltage VCC 15 V Supply Voltages BOOTA, BOOTB 22 V Voltage Identification Code Inputs, VID0-VID4 6 V VFB, ENABLE/SS, PWRGD, PHASE, CLK 6 V SW, ISNS -3 15 V PGNDA, PGNDB to AGND -0.5 0.5 V Gate Drive Current, peak pulse 3 A Junction Temperature, T J -55 150 C Storage Temperature -65 150 C Lead Soldering Temperature, 10 seconds 300 C Thermal Resistance Junction-to-case, Θ JA C/W Pin Definitions (continued) Pin Number Pin Name Pin Function Description

FAN5094 PRODUCT SPECIFICATION REV. 1.0.2 5/13/02 Recommended Operating Conditions Parameter Conditions Min. Typ. Max. Units Output Driver Supply, Boot See Figure 1 16 17 V VCC 10.8 12 13.2 V Input Logic HIGH 2.0 V Input Logic LOW 0.8 V Ambient Operating Temperature 0 70 C Electrical Specifications CC = 12V, V OUT = 1.500V, and T A = +25°C using circuit in Figure 1, unless otherwise noted.) The denotes specifications which apply over the full operating temperature range. Parameter Conditions Min. Typ. Max. Units Output Voltage See Table I 1.100 1.850 V Output Current 60 A Internal Reference Voltage 1.4925 1.5000 1.5075 V Initial Voltage Setpoint I LOAD = 0.8A 1.488 1.500 1.512 V Output Temperature Drift T A = 0 to 70 C+ 5 m V Line Regulation V IN = 11.4V to 12.6V +130 µ V Droop I LOAD = 0.8A to I max -90 -100 -110 mV Programmable Droop Range R DROOP = TBD to TBD -10 0 %V OUT Total Output Variation, Steady State I LOAD = 0.8A to I max 1.430 1.570 V Total Output Variation, Transient I LOAD = 0.8A to I max 1.430 1.570 V Response Time V OUT = 10mV 100 nsec Gate Drive On-Resistance 1.0 Ω Upper Drive Low Voltage V HDRV – V SW at I sink = 10µA 0.2 V Upper Drive High Voltage V BOOT – V HDRV at I source = 10µA 0.5 V Lower Drive Low Voltage I sink = 10µA 0.2 V Lower Drive High Voltage V CC – V LDRV at I source = 10µA 0.5 V Output Driver Rise & Fall Time See Figure 2 20 nsec Current Mismatch R DS,on (A) = R DS,on (B) 5 % Output Overvoltage Detect 2.1 2.3 V Efficiency I LOAD = I max I LOAD = 2A, E*-mode enabled Oscillator Frequency RT = 41.2K 450 600 750 KHz Oscillator Range RT = 125K Ω to 12.5K Ω 200 2000 KHz Maximum Duty Cycle RT = 125K Ω 90 % Minimum LDRV on-time RT=12.5K Ω 330 nsec Input Low Current, VID pins V VID = 0.4V 50 µA Soft Start Current 10 µA Enable Threshold ON OFF 0.4 1.0 V BYPASS Voltage 4.75 5 5.25 V BYPASS Capacitor 220 1000 nF

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Output Ripple and Output Temperature Drift and is measured at the converter’s VFB sense point. 2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.2m Ω trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s VRM 9.0 specification of +70, -70mV. PWRGD Threshold Logic LOW, minimum Logic LOW, maximum 108 111 115 out PWRGD Hysteresis 20 mV PWRGD Output Voltage I sink = 4mA 0.4 V PWRGD Delay High Low 500 µsec 12V UVLO 8.5 9.5 10.5 V UVLO Hysteresis 1.0 V 12V Supply Current HDRV and LDRV open 20 mA Over Temperature Shutdown 150 °C Over Temperature Hysteresis 25 °C Electrical Specifications (continued) CC = 12V, V OUT = 1.500V, and T A = +25°C using circuit in Figure 1, unless otherwise noted.) The denotes specifications which apply over the full operating temperature range. Parameter Conditions Min. Typ. Max. Units

1. 0 = VID pin is tied to GND.

1 = VID pin is pulled up to 5V. Table 1. Output Voltage Programming Codes

11111 O F F

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 7 Internal Block Diagram 2 3 26 VID0 Master Clock Digital Control Power Good 5-Bit DAC VID1 VID2 VID3 VID4 14 5 +12V PWRGD ENABLE/SS VO AGND ISHR DROOP/E* 217 +12V 5V Reg BYPASS f/2 f/2 PHASE CLK +12V +12V +12V Digital Control

FAN5094 PRODUCT SPECIFICATION 8 REV. 1.0.2 5/13/02 Typical Operating Characteristics (VCC = 12V, and TA = +25°C using circuit in Figure 1 , unless otherwise noted.) EFFICIENCY VS. OUTPUT CURRENT 0 1 02 03 04 05 06 0 OUTPUT CURRENT (A) EFFICIENCY (%) VOUT = 1.550V VOUT = 1.850V VOUT (50mV / DIV) TRANSIENT RESPONSE, 50A to 0.5A 1.590V 1.550V 1.480V TIME (20µs/DIVISION) 10V/DIVISION HIGH-SIDE GATE DRIVES, NORMAL OPERATION TRANSIENT RESPONSE, 0.5A TO 50A 1.590V 1.550V 1.480V VOUT (50mV / div) TIME (20µs/DIVISION) TIME (500ns/DIVISION) 10V/DIVISION HIGH-SIDE GATE DRIVES, E*-MODE TIME (500ns/DIVISION)

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 9 Typical Operating Characteristics (Continued) 10mV/DIVISION OUTPUT RIPPLE VOLTAGE TIME (1µs/DIVISION) 5V/DIVISION GATE DRIVE RISE TIME TIME (50ns/DIVISION) 10V/DIVISION 5V/DIVISION ADAPTIVE GATE DELAY TIME (50ns/DIVISION) 5V/DIVISION 50mV/DIVISION POWER GOOD DURING DYNAMIC VOLTAGE ADJUSTMENT TIME (200µs/DIVISION) 5A/DIVISION CURRENT SHARING BETWEEN INDUCTORS TIME (500ns/DIVISION) 5V/DIVISION GATE DRIVE FALL TIME TIME (10ns/DIVISION)

FAN5094 PRODUCT SPECIFICATION 10 REV. 1.0.2 5/13/02 Typical Operating Characteristics (Continued) 180 160 140 120 100 50 1 01 52 02 53 03 54 04 55 0 R Droop (KΩ) Droop vs. RDroop, RT = 43KΩ Droop (mV) VOUT TEMPERATURE VARIATION TEMPERATURE (°C) 1.501 1.500 1.499 1.498 1.497 1.496 1.495 1.494 0 25 70 100 VOUT (V)

Figure 1. Three-Phase Application Circuit for 65A Willamette Processor

Table 2. FAN5094 Application Bill of Materials for Figure 1

1. Inductor L1 is recommended to isolate the 12V input supply from noise generated by the MOSFET switching. L1 may be
2. For a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.

3 N-Channel MOSFET R DS(ON) = 17mΩ @

3 N-Channel MOSFET with

2 DC/DC Controller

Figure 2. Four-Phase Application Circuit for 81A Northwood Processor

Table 3. FAN5094 Application Bill of Materials for Figure 2

1. Inductor L1 is recommended to isolate the 12V input supply from noise generated by the MOSFET switching. L1 may be
2. For a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.

Figure 3. Output Drive Timing Diagram Optional 1.5µH, 14A Inductor DCR ~ 3m Ω. See Note 1.

4 N-Channel MOSFET R DS(ON) = 17mΩ @

4 N-Channel MOSFET with

1 DC/DC Controller

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 15

Application Information

The FAN5094 is a programmable synchronous multi-phase DC-DC controller IC. When designed around the appropriate external components, the FAN5094 can be configured to deliver more than 100A of output current, as appropriate for the new generation of high-current processors. The FAN5094 functions as a fixed frequency PWM step down regulator, with a high efficiency mode (E*) at light load. Main Control Loop Refer to the FAN5094 Block Diagram on page 7. The FAN5094 consists of two interleaved synchronous buck con- verters, implemented with summing-mode control. Each phase has its own current feedback, and there is a common voltage feedback. The two buck converters controlled by the FAN5094 are interleaved, that is, they run 180° out of phase with each other. This minimizes the RMS input ripple current, mini- mizing the number of input capacitors required. It also doubles the effective switching frequency, improving transient response. The FAN5094 implements “summing mode control”, which is different from both classical voltage-mode and current- mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads and external components. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts inputs from a current sensor and a voltage sensor, with the voltage sensor being common to both phases, and the current sensor separate for each. The voltage sensor amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to each of the two comparators. The current control path for each phase takes the difference between its PGND and SW pins when the low-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to the same input of its summing amplifier, adding its signal to the voltage amplifier’s with a certain gain. These two signals are thus summed together. This sum is then pre- sented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The oscillator ramps are 180° out of phase with each other, so that the two phases are on alternately. The digital control block takes the analog comparator input to provide the appropriate pulses to the HDRV and LDRV output pins for each phase. These outputs control the exter- nal power MOSFETs. Remote Voltage Sense The FAN5094 has true remote voltage sense capability, elim- inating errors due to trace resistance. To utilize remote sense, the VFB and AGND pins should be connected as a Kelvin trace pair to the point of regulation, such as the processor pins. The converter will maintain the voltage in regulation at that point. Care is required in layout of these grounds; see the layout guidelines in this datasheet. High Current Output Drivers The FAN5094 contains four high current output drivers that utilize MOSFETs in a push-pull configuration. The drivers for the high-side MOSFETs use the BOOT pin for input power and the SW pin for return. The drivers for the low-side MOSFETs use the VCC pin for input power and the PGND pin for return. Typically, the BOOT pin will use a charge pump as shown in Figures 1–2. Note that the BOOT and VCC pins are separated from the chip’s internal power and ground, BYPASS and AGND, for switching noise immunity. Adaptive Delay Gate Drive The FAN5094 embodies an advanced design that ensures minimum MOSFET transition times while eliminating shoot-through current. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure that they are never on simultaneously. When the high-side MOSFET turns off, the voltage on its source begins to fall. When the voltage there reaches approximately 2.5V , the low-side MOSFETs gate drive is applied with approximately 50nsec delay. When the low-side MOSFET turns off, the voltage at the LDRV pin is sensed. When it drops below approximately 2V , the high- side MOSFET’s gate drive is applied. Maximum Duty Cycle In order to ensure that the current-sensing and charge- pumping work, the FAN5094 guarantees that the low-side MOSFET will be on a certain portion of each period. For low frequencies, this occurs as a maximum duty cycle of approxi- mately 90%. Thus at 500KHz, with a period of 2µsec, the low-side will be on at least 2µsec • 10% = 200nsec. At higher frequencies, this time might fall so low as to be ineffective. The FAN5094 guarantees a minimum low-side on-time of approximately 330nsec, regardless of what duty cycle this corresponds to. Current Sensing The FAN5094 has two independent current sensors, one for each phase. Current sensing is accomplished by measuring the source-to-drain voltage of the low-side MOSFET during its on-time. Each phase has its own power ground pin, to per- mit the phases to be placed in different locations without affecting measurement accuracy. For best results, it is impor- tant to connect the PGND and SW pins for each phase as a Kelvin trace pair directly to the source and drain, respec-

the two phases each deliver half of the total output current. DS,on of the low-side MOSFETs. In normal usage, two FAN5094s will be operated in parallel. technique substantially enhances light load efficiency. **Figure 4. Implementing E*-mode Control** trimmed to provide a near zero temperature coefficient (TC). linear regulator, whose output is present on the BYPASS pin. to avoid false codes generating undesired output voltages. and provides a continuous voltage monitor on the VFB pin. control functions to the FAN5094.

10 R• DS on,

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 17 Output Enable/Soft Start (ENABLE/SS) The FAN5094 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to soft- start the switching. A softstart capacitor may be approxi- mately chosen by the formula: However, C must be ≥ 100nF. Oscillator The FAN5094 oscillator section runs at a frequency deter- mined by a resistor from the RT pin to ground according to the formula The oscillator generates two square waves, 180° out of phase with each other. One is used internally, the other is sent to a second FAN5094 on the CLK pin. The square wave generates two internal sawtooth ramps, each at one-half the square wave frequency, and running 180° out of phase with each other. These ramps cause the turn-on time of the two phases to be phased apart and the four phases to be 90° apart each. The oscillator frequency of the FAN5094 can be programmed from 400KHz to 4MHz with each phase running at 100KHz to 1MHz, respectively. Selection of a frequency will depend on various system performance criteria, with higher frequency resulting in smaller components but lower efficiency. Programmable Active Droop™ The FAN5094 features Programmable Active Droop™: as the output current increases, the output voltage drops propor- tionately an amount that can be programmed with an exter- nal resistor. This feature is offered in order to allow maximum headroom for transient response of the converter. The current is sensed losslessly by measuring the voltage across the low-side MOSFET during its on time. Consult the section on current sensing for details. Note that this method makes the droop dependent on the temperature and initial tolerance of the MOSFET, and the droop must be calculated taking account of these tolerances. Given a maximum load current, the amount of droop can be programmed with a resistor to ground on the droop pin, according to the formula with V Droop the desired droop voltage, RT the oscillator resistor, Imax the load current at which the droop is desired, n the number of phases, and RDS, on the on-state resistance of one phase’s low-side MOSFET. Typical response time of the FAN5094 to an output voltage change is 100nsec. Important Note! The oscillator frequency must be selected before selecting the droop resistor, because the value of RT is used in the calculation of R Droop. Over-Voltage Protection The FAN5094 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds 2.2V , an over-voltage condition is assumed and the FAN5094 latches on the external low-side MOSFET and latches off the high-side MOSFET. The DC-DC converter returns to normal operation only after V CC has been recycled. Thermal Design Considerations Because of the very large gate capacitances that the FAN5094 may be driving, the IC may dissipate substantial power. It is important to provide a path for the IC’s heat to be removed, to avoid overheating. In practice, this means that each of the pins should be connected to as large a trace as possible. Use of the heavier weights of copper on the PCB is also desirable. Since the MOSFETs also generate a lot of heat, efforts should be made to thermally isolate them from the IC. Over Temperature Protection If the FAN5094 die temperature exceeds approximately 150°C, the IC shuts itself off. It remains off until the temper- ature has dropped approximately 25°C, at which time it resumes normal operation. Component Selection MOSFET Selection This application requires N-channel Enhancement Mode Field Effect Transistors. Desired characteristics are as follows:

• Low Drain-Source On-Resistance, DS,ON < 10mΩ (lower is better);
• Power package with low Thermal Resistance;
• Drain-Source voltage rating > 15V;
• Low gate charge, especially for higher frequency operation. For the low-side MOSFET, the on-resistance (R DS,ON) is the primary parameter for selection. Because of the small duty cycle of the high-side, the on-resistance determines the power dissipation in the low-side MOSFET and therefore significantly affects the efficiency of the DC-DC converter. For high current applications, it may be necessary to use two MOSFETs in parallel for the low-side for each phase. C t1 0 µA• RT Ω() 50 10• 9 RDroop Ω() 2n• V• Droop RT•

as close to the MOSFET gate as possible. Figure 1. The FDB7045L has a maximum gate charge of worst case power dissipation. only the charge pump voltage of 5V .

not a criterion for this device, as its dissipation is very small. required is already very large. comparable electrolytics, but also much smaller capacitance. the processor; 0.1µF and 0.01µF are recommended values. itors during power up. A value of 1.3µH is recommended. refer to Applications Bulletin AB-16. Figure 5. Input Filter may be found in Fairchild’s Application Note 59.

FAN5094 PRODUCT SPECIFICATION 20 REV. 1.0.2 5/13/02 PCB Layout Guidelines

• Placement of the MOSFETs relative to the FAN5094 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5094 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress.
• In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5094. That is, traces that connect to pins 9-20 (LDRV , HDRV , GND and BOOT) should be kept far away from the traces that connect to pins 1 through 8, and pins 21-28.
• Place the 0.1µF decoupling capacitors as close to the FAN5094 pins as possible. Extra lead length on these reduces their ability to suppress noise.
• Each power and ground pin should have its own via to the appropriate plane. This helps provide isolation between pins.
• Place the MOSFETs, inductor, and Schottky of a given phase as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter.
• Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5.
• A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. PC Motherboard Sample Layout and Gerber File A reference design for motherboard implementation of the FAN5094 along with the PCAD layout Gerber file and silk screen can be obtained through your local Fairchild represen- tative. FAN5094 Evaluation Board Fairchild provides an evaluation board to verify the system level performance of the FAN5094. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please contact your local Fairchild representative for an evaluation board. Additional Information For additional information contact your local Fairchild representative.

PRODUCT SPECIFICATION FAN5094 REV. 1.0.2 5/13/02 21 Mechanical Dimension

28 Lead TSSOP

A — .047 — 1.20 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .002 .006 0.05 0.15 .012 0.30B .007 0.19 C .008 .013 0.09 0.20 E .172 .180 4.30 4.50 .018 .030 0.45 0.75 .026 BSC 0.65 BSCe .252 BSC 6.40 BSCH L 0° 8° 0° 8° N2 8 2 8 α ccc .004 0.10—— D .378 .386 9.60 9.80 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). "L" is the length of terminal for soldering to a substrate. Terminal numbers are shown for reference only. Symbol "N" is the maximum number of terminals. HE A D e B – C – ccc C LEAD COPLANARITY SEATING PLANE α L C

FAN5094 PRODUCT SPECIFICATION 5/13/02 0.0m 001 Stock#DS30005094  200 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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