FAN5069

FAN5069_08 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

■ General Purpose PWM Regulator and LDO Controller ■ Input Voltage Range: 3V to 24V ■ Output Voltage Range: 0.8V to 15V – VCC – 5V ■ Shunt Regulator for 12V Operation ■ Support for Ceramic Cap on PWM Output ■ Programmable Current Limit for PWM Output ■ Programmable Switching Frequency (200KHz to 600KHz) ■ RDS(ON) Current Sensing ■ Internal Synchronous Boot Diode ■ Soft-Start for both PWM and LDO ■ Multi-Fault Protection with Optional Auto-restart ■ 16-pin TSSOP Package

Applications

■ PC/Server Motherboard Peripherals – VCC_MCH (1.5V), VDDQ (1.5V) and VTT_GTL (1.25V) ■ Power Supply for – FPGA, DSP, Embedded Controllers, Graphic Card Processor, and Communication Processors ■ Industrial Power Supplies ■ High-Power DC-to-DC Converters

Description

The FAN5069 combines a high-efficiency Pulse-Width- Modulated (PWM) controller and an LDO (Low DropOut) linear regulator controller. Synchronous rectification pro- vides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET’s R DS(ON) to sense current. Both the linear and PWM regulator soft-start are con- trolled by a single external capacitor, to limit in-rush cur- rent from the supply when the regulators are first enabled. Current limit for PWM is also programmable. The PWM regulator employs a summing-current-mode control with external compensation to achieve fast load transient response and provide design optimization. FAN5069 is offered in both industrial temperature grade (-40°C to +85°C) as well as commercial temperature grade (-10°C to +85°C).

Ordering Information

Note: Contact Fairchild sales for availability of other package options. Part Number Operating Temp. Range Pb-Free Package Packing Method Qty./Reel FAN5069MTCX -10°C to +85°C Yes 16-Lead TSSOP Tape and Reel 2500 FAN5069EMTCX -40°C to +85°C Yes 16-Lead TSSOP Tape and Reel 2500

Figure 1. Typical Application Diagram

3 TO 24V

14 R(RAMP)

Figure 2. Pin Assignment 1F B L D O LDO Feedback. This node is regulated to VREF. ing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased. 3I L I M Current Limit. A resistor from this pin to GND sets the current limit. is enabled when SS reaches 2.2V. 5C O M P COMP. The output of the error amplifier drives this pin. nation with the COMP pin, to compensate the feedback loop of the converter. needs to be properly biased at all times. 8A G N D Analog Ground. The signal ground for IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. to source of high-side MOSFET and drain of low-side MOSFET. high-side MOSFET is turned off. 11 BOOT Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor as shown in Figure 1. when the input voltage is above 5.6V. 16 GLDO Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 4 Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi- tions for actual device operation. (1) Notes: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to AGND. 2. Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model). Thermal Information Notes: 3. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat sink characteristics. Recommended Operating Conditions Parameter Min. Max. Unit VCC to PGND 6.0 V BOOT to PGND 33.0 V SW to PGND Continuous -0.5 33.0 V Transient (t < 50nS, F < 500kHz) -3.0 33.0 V HDRV (VBOOT- – VSW) 6.0 V LDRV -0.5 6.0 V All Other Pins -0.3 V CC + 0.3 V Maximum Shunt Current for VCC 150 mA Electrostatic Discharge Protection (ESD) Level(2) HBM 3.5 kV CDM 1.8 Symbol Parameter Min. Typ. Max. Unit TSTG Storage Temperature -65 150 °C TL Lead Soldering Temperature, 10 Seconds 300 °C Vapor Phase, 60 Seconds 215 °C Infrared, 15 Seconds 220 °C P D Power Dissipation, TA = 25°C 715 mW θJC Thermal Resistance, Junction-to-Case 37 °C/W θJA Thermal Resistance, Junction-to-Ambient(3) 100 °C/W Symbol Parameter Conditions Min. Typ. Max. Unit VCC Supply Voltage V CC to GND 4.5 5.0 5.5 V TA Ambient Temperature Commercial -10 85 °C Industrial -40 85 °C TJ Junction Temperature 125 °C

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 5

Electrical Characteristics

Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1. The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5. Symbol Parameter Conditions Min. Typ. Max. Unit Supply Current IVCC VCC Current (Quiescent) HDRV, LDRV Open • 2.6 3.2 3.8 mA IVCC(SD) VCC Current (Shutdown) EN = 0V, V CC = 5.5V • 200 400 μA IVCC(OP) VCC Current (Operating) EN = 5V, V CC = 5.0V, QFET = 20nC, FSW = 200kHz 10 15 mA VSHUNT VCC Voltage(6) Sinking 1mA to 100mA at VCC Pin 5.5 5.9 V Under-Voltage Lockout (UVLO) UVLO(H) Rising V CC UVLO Threshold • 4.00 4.25 4.50 V UVLO(L) Falling V CC UVLO Threshold • 3.60 3.75 4.00 V VCC UVLO Threshold Hysteresis 0.50 V Soft-Start ISS Current 10 μA VLDOSTART LDO Start Threshold 2.2 V VSSOK PWM Protection Enable Threshold 1.2 V Oscillator FOSC Frequency R(T) = 56K Ω ± 1% 240 300 360 KHz R(T) = Open 160 200 240 KHz Frequency Range 160 600 KHz ΔVRAMP Ramp Amplitude (Peak-to-Peak) R(RAMP) = 330KΩ 0.4 V Minimum ON Time F = 200kHz 200 nS. Reference VREF Reference Voltage (Measured at FB Pin) TA = 0°C to 70°C • 790 800 810 mV TA = -40°C to 85°C • 788 800 812 mV Current Amplifier Reference (at SW node) 160 mV Error Amplifier DC Gain 80 dB GBWP Gain-BW Product 25 MHz S/R Slew Rate 10pF across COMP to GND 8 V/ μS. Output Voltage Swing No Load • 0.5 4.0 V IFB FB Pin Source Current 1 μA Gate Drive RHUP HDRV Pull-up Resistor Sourcing • 1.8 3.0 Ω RHDN HDRV Pull-down Resistor Sinking • 1.8 3.0 Ω RLUP LDRV Pull-up Resistor Sourcing • 1.8 3.0 Ω RLDN LDRV Pull-down Resistor Sinking • 1.2 2.0 Ω

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 6 Electrical Characteristics (Continued) Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1. The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5. Notes: 4. All limits at operating temperatur e extremes are guaranteed by design, ch aracterization, and statistical quality control. 5. AC specifications guaran teed by design/characterization (not production tested). 6. For a case when V CC is higher than the typical 5V V CC; voltage observed at VCC pin when the internal shunt regulator is sinking current to keep voltage on VCC pin constant. 7. Test Conditions: V LDO_IN = 1.5V and VLDO_OUT = 1.2V Symbol Parameter Conditions Min. Typ. Max. Unit Protection/Disable ILIM ILIMIT Source Current 9 10 11 μA ISWPD SW Pull-down Current SW = 1V, EN = 0V 2 mA VUV Under-Voltage Threshold As % of set point; 2 μS noise fil- ter

• 6 57 58 0 % VOV Over-Voltage Threshold As % of set point; 2 μS noise fil- ter
• 110 115 120 % TSD Thermal Shutdown 160 °C Enable Threshold Voltage Enable Condition • 2.0 V Enable Threshold Voltage Disable Condition • 0.8 V Enable Source Current V CC = 5V 50 μA LDO(7) VLDOREF Reference Voltage (mea- sured at FBLDO pin) TA = 0°C to 70°C • 775 800 825 mV TA = -40°C to 85°C • 770 800 830 mV Regulation 0A ≤ ILOAD ≤ 5A • 1.17 1.2 1.23 V VLDO_DO Drop out Voltage I LOAD ≤ 5A and RDS-ON < 50mΩ 0.3 V External Gate Drive V CC = 4.75V • 4.5 V VCC = 5.6V • 5.3 V Gate Drive Source Current 1.2 mA Gate Drive Sink Current 400 μA

Figure 20. Block Diagram operation from either a 5V or 12V power source. ■ It is rated to handle the power dissipation. prevent IC temperature rise. lower MOSFET R DS_ON to generate the PWM signals.

external compensation for enhanced flexibility. enabled, this internal MOSFET remains OFF. the circuit releases SS and enables the PWM regulator. this voltage exceeds 2.2V, the LDO output is enabled. Figure 18. The minimum clock frequency is 200KHz, For example, for FOSC = 300kHz, R(T) = 50KΩ. circuit, thereby increasing the chances for shoot-through. threshold voltage for the output of the summing amplifier.

the SS capacitor crosses 1.2V. ing die temperature below 125°C. terminal of the bottom MOSFET and PGND. IMAX is the maximum load current. MOSFET RDS(ON) (typically 1.6). not leave the EN pin open without any capacitor. age on the SS capacitor reaches 1.2V. as soon as the voltage on the EN pin becomes high. fuse, protecting the system, which is very critical. Figure 21. Over-Voltage Protection

2 Clks

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 13 LDO Section The LDO controller is designed to provide ultra low volt- ages, as low as 0.8V for GTL-type loads. The regulating loop employs a very fast response feedback loop and small capacitors can be used to keep track of the chang- ing output voltage during transients. For stable opera- tion, the minimum capacitance on the output needs to be 100µF and the typical ESR needs to be around 100mΩ. The maximum voltage at the gate drive for the MOSFET can reach close to 0.5V below the V CC of the controller. For example, for a 1.2V out put, the minimum enhance- ment voltage required with 4.75V on V CC is 3.05V LDO is dependent on the load current and the MOSFET chosen. It is recommended to use low enhancement voltage MOSFETs for the LDO. In applications where LDO is not needed, pull up the FBLDO pin (Pin #1) higher than 1V to disable the LDO. The soft-start on the LDO output (ramp) is controlled by the capacitor on the SS pin to GND. The LDO output is enabled only when the voltage on the SS pin reaches 2.2V. Refer to Figure 9 for start-up waveform. Design Section General Design Guidelines Establishing the input voltage range and maximum cur- rent loading on the converter before choosing the switch- ing frequency and the inductor ripple current is highly recommended. There are design trade-offs in choosing an optimum switching frequency and the ripple current. The input voltage range should accommodate the worst- case input voltage with which the converter may ever operate. This voltage needs to account for the cable drop encountered from the source to the converter. Typically, the converter efficiency tends to be higher at lower input voltage conditions. When selecting maximum loading conditions, consider the transient and steady-state (continuous) loading sep- arately. The transient loading affects the selection of the inductor and the output capacitors. Steady state loading affects the selection of MOSF ETs, input capacitors, and other critical heat-generating components. The selection of switching frequency is challenging. While higher switching frequency results in smaller com- ponents, it also results in lower efficiency. Ideal selection of switching frequency takes into account the maximum operating voltage. The MOSFET switching losses are directly proportional to F SW and the square function of the input voltage. When selecting the inductor, consider the minimum and maximum load conditions. Lower inductor values pro- duce better transient response, but result in higher ripple and lower efficiency due to high RMS currents. Optimum minimum inductance value enables the converter to operate at the boundary of continuous and discontinuous conduction modes. Setting the Output Voltage (PWM) The internal reference for th e PWM controller is at 0.8V. The output voltage of the PWM regulator can be set in the range of 0.8V to 90% of its power input by an exter- nal resistor divider. The output is divided down by an external voltage divider to the FB pin (for example, R1 and RBIAS as in Figure 24). The output voltage is given by the following equation: (EQ. 6) To minimize noise pickup on this node, keep the resistor to GND (RBIAS) below 10KΩ. Inductor Selection (PWM) When the ripple current, switching frequency of the con- verter, and the input-output voltages are established, select the inductor using the following equation: (EQ. 7) where IRipple is the ripple current. This number typically varies between 20% to 50% of the maximum steady-state load on the converter. When selecting an inductor fr om the vendors, select the inductance value which is close to the value calculated at the rated current (including half the ripple current). Input Capacitor Selection (PWM) The input capacitors must have an adequate RMS cur- rent rating to withstand the temperature rise caused by the internal power dissipation. The combined RMS cur- rent rating for the input capacitor should be greater than the value calculated using the following equation: (EQ. 8) Common capacitor types us ed for such application include aluminum, ceramic, POS CAP, and OSCON. Output Capacitor Selection (PWM) The output capacitors chosen must have low enough ESR to meet the output ripple and load transient require- ments. The ESR of the output capacitor should be lower than both of the values calc ulated below to satisfy both the transient loading and steady-state ripple conditions as given by the following equation: (EQ. 9) VOUT 0.8V 1 R1 RBIAS ⎛⎞×= LMIN VOUT VOUT VIN –⎝⎠ IINPUT RMS() ILOAD MAX()= VOUT VIN VOUT VIN ⎛⎞× ESR VSTEP ΔILOAD MAX() VRipple IRipple

important role in the stability of the converter. be at least 25% higher than worst-case input voltage. ■ The MOSFETs should have low QG, QGD, and QGS. ■ The RDS_ON of the MOSFETs should be as low as possible. losses also affect the temperature rise on the controller. AN-6005 and the associated spreadsheet. FET gate drive equivalent circuit is shown in Figure 23. Figure 22. Switching Losses and QG Figure 23. Drive Equivalent Circuit Source Voltage (VDS) and Drain Current (ID) waveforms. the lower graph from the MOSFET datasheets. voltage across it and current through it. fall time) and equals t2+t3 (Figure 22.). period is controlled by the driver's impedance and QGD. charge required to reach the MOSFET threshold (VTH).

2 RDS ON()××=

where QG is the total gate charge to reach VCC. negligible and Q2 is selected based on RDS(ON) alone. is the minimum duty cycle for the converter. duces a conservative result, simplifying the calculation. low capacitance scope probe. so that it reduces this ringing by half. c) Place a resistor (R SNUB) in series with this capacitor. is the converter switching frequency.

2 FSW××=

Figure 24. Closed-Loop System with Type-3 Network

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 16 FAN5069 has a high gain error amplifier around which the loop is closed. Figure 24 shows a Type-3 compensa- tion network. For Type-2 compensation, R3 and C3 are not used. Since the FAN5069 architecture employs sum- ming current mode, Type-2 compensation can be used for most applications. For further information about Type-2 compensation networks, refer to: ■ Venable, H. Dean, "The K factor: A new mathematical tool for stability analysis and synthesis,” Proceedings of Powercon, March 1983. Note: For critical applications requiring wide loop bandwidth using very low ESR output capacitors, use Type-3 compensation. Type 3 Feedback Component Calculations Use the following steps to calculate feedback components: Notation: Equations: Effective current sense resistance = (EQ. 19) Current modulator DC gain = (EQ. 20) Effective ramp amplitude = (EQ. 21) Voltage modulator DC gain = (EQ. 22) Plant DC gain = (EQ. 23) Sampling gain natural frequency = (EQ. 24) Sampling gain quality factor (damping) = (EQ. 25) Effective inductance = (EQ. 26) (EQ. 27) C0 Net Output Filter capacitance= Gp s() Net Gain of Plant = control-to-output transfer function= L Inductor Value= RDSON ON-state Drain-to Source Resistance of Low-side MOSFET= Res Net ESR of the Output Filter Capacitors= RL Load Resistance= Ts Switching Period= VIN Input Voltage= FSW Switching Frequency= Ri 7R DSON×= Mi RL Ri Vm 3.33 10 10 VIN 1.8–() Ts× Rramp Mv VIN Vm Mo Mv Mi|| Mv Mi× ωn π Ts Qz Le MO Mv Mv Ri× ⎛⎞×= Rp Mv Ri RL××

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 17 Poles and Zeros of Plant Transfer Function: Plant zero frequency = (EQ. 28) Plant 1st pole frequency = (EQ. 29) Plant 2nd pole frequency = (EQ. 30) Plant 3rd pole frequency = (EQ. 31) Plant gain (magnitude) response: (EQ. 32) Plant phase response: (EQ. 33) Choose R1, R BIAS to set the output voltage using EQ.6. Choose the zero crossover frequency F cross of the overall loop. Typically Fcross should be less than fifth of Fsw. Choose the desired phase margin; typically between 60° to 90°. Calculate plant gain at Fcross using EQ.34 by substituting Fcross in place of f. The gain that the amplifier needs to pro- vide to get the required crossover is given by: (EQ. 34) The phase boost required is calculated as given in (EQ. 35) (EQ. 35) where M is the desired phase margin in degrees. The feedback component values are calculated as given in equations below: (EQ. 36) (EQ. 37) (EQ. 38) (EQ. 39) (EQ. 40) (EQ. 41) fz fp1 2 π Co Rp Le RL ⎛⎞×× fp2 Rp Le ⎛⎞×= fp3 ωn

2 Le×

Gp (f) 20 M 0log 10 1 f fz ----⎝⎠ ⎛⎞ 2 1 f fp1 ⎛⎞ 2 + 1 f fp2 ⎛⎞ 2 + 1 f fp3 ⎛⎞ 2 +×× GP(f)∠ tan 1– f fz ----⎝⎠ ⎛⎞ tan 1– f fp1 ⎛⎞– tan 1– f fp2 ⎛⎞– tan 1– f fp3 ⎛⎞––= GAMP Phase Boost M G P(Fcross )∠– 90°–= KT a n Boost ⎛⎞ 45+ C2 1 C1 C2 K 1 –()×= C3 1 2 π Fcross K××× R3× R2 K R3 R1

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 18 Design Tools Fairchild application note AN-6010 provides a PSPICE model and spreadsheet calculator for the PWM regula- tor, simplifying external component selections and verify- ing loop stability. The topics covered provide an understanding of the calculations in the spreadsheet. The spreadsheet calculator, which is part of AN-6010, can be used to calculate all external component values for designing around FAN5069. The spreadsheet pro- vides optimized compensation components and gener- ates a Bode Plot to ensure loop stability. Based on the input values entered, AN-6010’s PSPICE model can be used to simulate Bode Plots (for loop sta- bility) as well as transient analysis to help customize the design for a wide range of applications. Use Fairchild Application Note AN-6005 for prediction of the losses and die temperatures for the power semicon- ductors used in the circuit. AN-6010 and AN-6005 can be downloaded from www.fairchildsemi.com/apnotes/ Layout Considerations The switching power converter layout needs careful attention and is critical to achieving low losses and clean and stable operation. Below are specific recommenda- tions for good board layout: ■ Keep the high-current traces and load connections as short as possible. ■ Use thick copper boards whenever possible to achieve higher efficiency. ■ Keep the loop area between the SW node, low-side MOSFET, inductor, and the output capacitor as small as possible. ■ Route high dV/dt signals, such as SW node, away from the error amplifier input/output pins. Keep com- ponents connected to these pins close to the pins. ■ Place ceramic de-coupling capacitors very close to the VCC pin. ■ All input signals are referenced with respect to AGND pin. Dedicate one layer of the PCB for a GND plane. Use at least four layers for the PCB. ■ Minimize GND loops in the layout to avoid EMI-related issues. ■ Use wide traces for the lower gate drive to keep the drive impedances low. ■ Connect PGND directly to the lower MOSFET source pin. ■ Use wide land areas with appropriate thermal vias to effectively remove heat from the MOSFETs. ■ Use snubber circuits to minimize high-frequency ring- ing at the SW nodes. ■ Place the output capacitor for the LDO close to the source of the LDO MOSFET.

Figure 25. Application Board Schematic

Dimensions are in millimeters unless otherwise noted. Figure 31. 16-Lead TSSOP

FAN5069 PWM and LDO Controller Combo © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5069 Rev. 1.1.5 22