FAN5059MX

FAN5059MX FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

rogrammable output for Vcore from 1.3V to 3.5V using an integrated 5-bit DAC

• Controls adjustable linears for Vagp (selectable 1.5V/3.3V), Vclock (2.5V), and Vtt (1.5V) or Vnorthbridge (1.8V)
• Meets VRM specification with as few as 5 capacitors
• Meets 1.550V +40/-70mV over initial tolerance, temperature and transients
• Remote sense
• Programmable Active Droop™ (V oltage Positioning)
• Drives N-Channel MOSFETs
• O vercurrent protection using MOSFET sensing
• 85% efficiency typical at full load
• Integrated Power Good and Enable/Soft Start functions
• 24 pin SOIC package

Applications

• P ower supply for Pentium III Camino Platform
• P ower supply for Pentium III Whitney Platform
• VRM for Pentium III processor
• Programmable multi-output power supply

Description

The FAN5059 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Camino, and provides a complete solution for the Intel Whitney and other high-performance processors. The FAN5059 features remote voltage sensing, independently adjustable current limit, and a proprietary Programmable Active Droop for optimal converter transient response. The FAN5059 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V . The FAN5059 uses a high level of integration to deliver load Block Diagram VID3 VID2 VID1 VID0 GNDP OSC 1.24V Reference Digital Control Power Good 5-Bit DAC VID4 87654 +5V +12V PWRGD ENABLE/SS VCC GNDA LODRV HIDRV VCCP 21VCCA +5V REF REF PWRGD, OCL PWRGD, OCL +3.3V +1.5V +2.5V OCL VCCP PWRGD, OCL V 3.3/1.5V RD RS FAN5059 High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms

FAN5059 PRODUCT SPECIFICATION REV. 1.0.4 8/14/03 currents in excess of 16A from a 5V source with minimal external circuitry. Synchronous-mode operation offers opti- mum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight toler- ance voltage regulation without expensive external compo- nents, while Programmable Active Droop permits exact tailoring of voltage for the most demanding load transients. The FAN5059 includes linear regulator controllers for Vtt termina- tion (1.5V), Vclock (2.5V), and Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), each adjustable with an external divider. The FAN5059 also offers integrated functions including Power Good, Output Enable/Soft Start and current limiting, and is available in a 24 pin SOIC package. Pin Assignments FAN5059 HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VTTGATE VTTFB VCKGATE VCKFB VCCP LODRV GNDP VCCA VFB DROOP ILIM PWRGD SS/ENABLE TYPEDET VAGPGATE VAGPFB Pin Definitions Pin Number Pin Name Pin Function Description

1 HIDRV

High Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". 2S W High side Driver Source and Low side Driver Drain Switching Node. Together with DROOP and ILIM pins allows FET sensing for Vcc current.

3 GNDA

Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. 4-8 VID0-4 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller.

9 VTTGATE

Gate Driver for VTT Transistor. For 1.5V output.

10 VTTFB

Voltage Feedback for VTT.

11 VCKGATE

Gate Driver for VCK Transistor. For 2.5V output.

12 VCKFB

Voltage Feedback for VCK.

13 VAGPFB

Voltage Feedback for VAGP.

14 VAGPGATE

Gate Driver for VAGP Transistor. For 3.3/1.5V output.

15 TYPEDET

Type Detect. Sets 3.3V or 1.5V for AGP.

16 ENABLE/SS

Output Enable. A logic LOW on this pin will disable all outputs. An internal current source allows for open collector control. This pin also doubles as soft start for all outputs.

17 PWRGD

Power Good Flag. An open collector output that will be logic LOW if any output voltage is more than ±12% outside of the nominal output voltage setpoint.

18 ILIM

Vcc Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the Vcc current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details.

19 DROOP

Droop set. Use this pin to set magnitude of active droop.

20 VFB

Vcc Voltage Feedback. Pin 20 is used as the input for the Vcc voltage feedback control loop. See Application Information for details regarding correct layout.

21 VCCA

Analog VCC. Connect to system 5V supply and decouple with a 0.1µF ceramic capacitor.

22 GNDP

Power Ground. Return pin for high currents flowing in pin 24 (VCCP).

23 LODRV

Vcc Low Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5".

24 VCCP

Power VCC. For all FET drivers. Connect to system 12V supply through a 33 Ω , and decouple with a 1µF ceramic capacitor.

PRODUCT SPECIFICATION FAN5059 REV. 1.0.4 8/14/03 Absolute Maximum Ratings Note: 1. Component mounted on demo board in free air. Recommended Operating Conditions Supply Voltage VCCA to GND 13.5V Supply Voltage VCCP to GND 15V Voltage Identification Code Inputs, VID0-VID4 VCCA All Other Pins 13.5V Junction Temperature, T J 150°C Storage Temperature -65 to 150°C Lead Soldering Temperature, 10 seconds 300°C Thermal Resistance Junction-to-ambient, Θ JA 75°C/W Parameter Conditions Min. Typ. Max. Units Supply Voltage VCCA 4.5 5 5.25 V Input Logic HIGH 2.0 V Input Logic LOW 0.8 V Ambient Operating Temperature 0 70 °C Output Driver Supply, VCCP 10.8 12 13.2 V Electrical Specifications CCA = 5V, V CCP = 12V, V OUT = 2.0V, and T A = +25°C using circuit in Figure 1 unless otherwise noted.) The • denotes specifications which apply over the full operating temperature range. Parameter Conditions Min. Typ. Max. Units VCC Regulator Output Voltage See Table 1 • 1.3 3.5 V Output Current 18 A Initial Voltage Setpoint I LOAD = 0.8A,V OUT = 2.400V V OUT = 2.000V V OUT = 1.550V 2.397 2.000 1.550 2.424 2.020 1.565 2.454 2.040 1.580 V V V Output Temperature Drift T A = 0 to 70°C,V OUT = 2.000V V OUT = 1.550V mV mV Line Regulation V IN = 4.75V to 5.25V • -4 mV/V Internal Droop Impedance I LOAD Ω Maximum Droop 60 mV Output Ripple 20MHz BW, I LOAD = 18A 11 mVpk Total Output Variation, Steady State V OUT = 2.000V V OUT = 1.550V 1.940 1.480 2.070 1.590 V Total Output Variation, Transient I LOAD = 0.8A to 18A, V OUT = 2.000V V OUT = 1.550V 1.900 1.480 2.100 1.590 V Short Circuit Detect Current • 45 50 60 µA Efficiency I LOAD = 18A, V OUT = 2.0V 85 % Output Driver Rise & Fall Time See Figure 3 50 nsec Output Driver Deadtime See Figure 3 50 nsec

FAN5059 PRODUCT SPECIFICATION REV. 1.0.4 8/14/03 Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter’s VFB sense point. 2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m Ω trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s VRM 8.4 specification of +50, –80mV. If Intel specifications on maximum plane resistance from the converter’s output capacitors to the CPU are met, the specification of +40, –70mV at the capacitors will also be met. 4. Actual output voltage (V nom ) at 0A load is 1% higher than specified in the “Typical” column. Duty Cycle 0 100 % 5V UVLO • 3.74 4 4.26 V 12V UVLO • 7.65 8.5 9.35 V Soft Start Current • 5 10 17 µA VTT Linear Regulator Output Voltage I LOAD 2A • 1.455 1.5 1.545 V Under Voltage Trip Level Over Current 80 %V O VCLK Linear Regulator Output Voltage I LOAD 2A • 2.425 2.5 2.575 V Under Voltage Trip Level Over Current 80 %V O VAGP Linear Regulator Output Voltage I LOAD 2A, TYPEDET=0V • 1.455 1.5 1.545 V Output Voltage I LOAD 2A, TYPEDET=OPEN • 3.135 3.3 3.465 V Under Voltage Trip Level Over Current 80 %V O Common Functions Oscillator Frequency • 255 310 345 kHz PWRGD Threshold Logic HIGH, All Outputs Logic LOW, Any Output 112 116 OUT Linear Regulator Under Voltage Delay Time Over Current 30 µsec Electrical Specifications (Continued) CCA = 5V, V CCP = 12V, V OUT = 2.0V, and T A = +25°C using circuit in Figure 1 unless otherwise noted.) The • denotes specifications which apply over the full operating temperature range. Parameter Conditions Min. Typ. Max. Units

1. 0 = processor pin is tied to GND.

Table 1. Output Voltage Programming Codes

FAN5059 PRODUCT SPECIFICATION REV. 1.0.4 8/14/03 Typical Operating Characteristics CCA = 5V, V CCP = 12V, and T A = +25°C using circuits in Figure 1, unless otherwise noted.) Droop, VCPU = 2.0V, RD = 8K Ω VOUT (V) VOUT (V) VCPU(V) VCPU(V) 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 1.94 0 3 6 9 12 15 18 Output Current (A) Output Programming, VID4 = 1 3.5 3.0 2.5 2.0 1.5 1.0 DAC Setpoint VCPU Efficiency vs. Output Current Output Current (A) 0 3 6 9 12 15 18 VOUT = 1.550V VOUT = 2.000V Efficiency (%) Output Programming, VID4 = 0 2.1 1.9 1.7 1.5 1.3 1.1 DAC Setpoint 0 5 10 15 20 25 3.5 3.0 2.5 2.0 1.5 1.0 0.5 CPU Output Voltage vs. Output Current Output Current (A)

PRODUCT SPECIFICATION FAN5059 REV. 1.0.4 8/14/03 7 Typical Operating Characteristics (continued) Output Ripple, 2.0V @ 18A Time (1µs/div) Time (1µs/div) VCPU (20mV/div) VCPU (50mV/div) VCPU (50mV/div) VCPU (1V/div) VIN (2V/div) HIDRV pin LODRV pin 5V/div 5V/div Output Startup, System Power-up Transient Response, 12.5A to 0.5A 1.590V 1.550V 1.480V 1.590V 1.550V 1.480V Time (100µs/div) Time (100µs/div) Time (10ms/div) Switching Waveforms, 18A Load Output Startup from Enable VCPU (1V/div) ENABLE (2V/div) Time (10ms/div) Transient Response, 0.5A to 12.5A

Figure 1. Typical Application Circuit † Adjustable with an external divider.

Table 2. FAN5059 Application Bill of Materials

1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply

with Intel dI/dt requirements. L1 may be omitted if desired.

1. For 17.4A designs using the TO-220 MOSFETs, heatsinks with thermal resistance ΘSA < 20°C/W should be used. For designs

refer to Applications Bulletins AB-8 and AB-15. *Refer to Appendix for values.

1 N-Channel MOSFET R DS(ON) = 20mΩ @

1 N-Channel MOSFET R DS(ON) = 10mΩ @

3 N-Channel MOSFET

1 DC/DC Controller

Figure 2. Application Circuit for Coppermine/Camino Motherboards *Refer to Table 4 for values of COUT and CIN. † Adjustable with an external divider.

Table 3. FAN5059 Application Bill of Materials for Intel Coppermine/Camino Motherboards

1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply

with Intel dI/dt requirements. L1 may be omitted if desired.

1. For 12.5A designs using the TO-220 MOSFETs, heatsinks with thermal resistance ΘSA < 20°C/W should be used. For

selections, refer to Applications Bulletins AB-8 and AB-15.

FAN5059 PRODUCT SPECIFICATION 12 REV. 1.0.4 8/14/03 Test Parameters Figure 3. Ouput Drive Timing Diagram

Application Information

The FAN5059 is a programmable synchronous DC-DC con- troller IC. When designed around the appropriate external components, the FAN5059 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The FAN5059 functions as a fixed frequency PWM step down regulator. Main Control Loop Refer to the FAN5059 Block Diagram on page 1. The FAN5059 implements “summing mode control”, which is dif- ferent from both classical voltage-mode and current-mode control. It provides superior performance to either by allow- ing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the FAN5059 cur- rent limit comparator disables the output drive signals to the external power MOSFETs. High Current Output Drivers The FAN5059 contains two identical high current output driv- ers that utilize high speed bipolar transistors in a push-pull configuration. The drivers’ power and ground are separated from the chip’s power and ground for switching noise immu- nity. The power supply pin, VCCP, is supplied from an exter- nal 12V source through a series 33Ω resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low R DS,ON. Internal Voltage Reference The reference included in the FAN5059 is a precision band- gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V . Power Good (PWRGD) The FAN5059 Power Good function is designed in accor- dance with the Pentium II and III DC-DC converter specifi- cations and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than ±16% of its nominal setpoint. Power Good outputs an open collector high when the output voltage is within ±12% of its nominal setpoint. The Power Good flag provides no other control function to the FAN5059. Output Enable/Soft Start (ENABLE/SS) The FAN5059 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. The softstart pin (ENABLE/SS) ramp can be divided into three time periods. The first part is represented by t 1, the second is represented by t2 and the third is represented by t3. The voltage on the pin is: tR tDT tDT tF HIDRV to SW LODRV2V 2V VSS CSS ISS  T()×= t1 2.25 CSS ISS ×= t2 2.75 CSS ISS × t1–= t3 5 CSS ISS × t1 t2+()–=

PRODUCT SPECIFICATION FAN5059 REV. 1.0.4 8/14/03 13 The softstart ramp begins at T(0) where UVLO is released. During the period of t1 the softstart pin ramps but the PWM switching is not enabled and thus the duty cycle is zero (D=0) and the output voltage is zero. During t 2 the duty cycle increased progressively from 0 to 1. This period is where the output voltage ramps, dependent on output capaci- tance and output load. If the duration of t 2 is long enough the output voltage will fully ramp to the point of regulation. During t 3 the softstart pin continues to ramp but without effect on the output voltage. NOTE: If a very large output capacitor bank is used it may be required to use a larger CSS to ensure a full output voltage ramp within t2. Over-Voltage Protection The FAN5059 constantly monitors the output voltage for pro- tection against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-volt- age condition is assumed and the FAN5059 disables the out- put drive signal to the external high-side MOSFET. The DC- DC converter returns to normal operation after the output voltage returns to normal levels. Oscillator The FAN5059 oscillator section uses a fixed frequency of operation of 300KHz. Design Considerations and Component Selection Additional information on design and component selection may be found in Fairchild’s Application Note 57. MOSFET Selection This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows:

• L ow Static Drain-Source On-Resistance, R DS,ON < 20mΩ (lower is better)
• L ow gate drive voltage, VGS = 4.5V rated
• P ower package with low Thermal Resistance
• Drain-Source voltage rating > 15V . The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applica- tions Bulletin AB-8. Inductor Selection Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: where: V in = Input Power Supply Vout = Output V oltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel V ripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient D m = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for CO, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The FAN5059 provides significant cost savings for the newer CPU systems that typically run at high supply current. FAN5059 Short Circuit Current Characteristics The FAN5059 protects against output short circuit on the core supply by turning off both the high-side and low-side MOSFETs and resetting softstart. The short circuit limit is set with the R S resistor, as given by the formula Note: RS cannot exceed 10.8K. If a higher current is required than 10.8K allows, a FET with lower RDSon must be used. 2.75V 2.25V t1 t2 t3 VSS TT(0) Lmin (Vin – Vout) f x Vout Vin x ESR Vripple Lmax (Vin – Vout) Dm Vtb Ipp2 = 2CO RS ISC *RDS, on IDetect

ing its on time, as shown in Figure 1. minimize the output capacitor requirements of the converter. may be found in Applications Bulletin AB-24. Figure 6. Adjusting the Output Voltage of the Linear Note: See Note 4 in Electrical Specifications Table. bridge = 1.0V , Vagp = 1.8V , meeting the Intel requirement.

• Placement of the MOSFETs relative to the FAN5059 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5059 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress.
• In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5059. That is, traces that connect to pins 1, 2, 23, and 24 (HIDRV , SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 20 and 21.
• Place the 0.1µF decoupling capacitors as close to the FAN5059 pins as possible. Extra lead length on these reduces their ability to suppress noise.
• Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins.
• Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter.
• Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5.
• A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. Additional Information For additional information contact Fairchild Semiconductor at http://www.fairchildsemi.com/cf/tsg.htm or contact an autho- rized representative in your area. RD 14.4KΩ *Imax *Rsense VDroop *18 VFB VGATE VOUT 10KΩ R R 10KΩ*– 1 Vout Vnom

FAN5059 PRODUCT SPECIFICATION 16 REV. 1.0.4 8/14/03 Appendix Worst-Case Formulae for the Calculation of Cin, Cout , R5, R7 and Roffset (Circuits similar to Figure 1 only) The following formulae design the FAN5059 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: V S+, the value of the positive static voltage limit; |VS-|, the absolute value of the negative static voltage limit; VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); Irms, the ripple current rating of the input capacitors, per cap (2A for the Sanyo parts shown in this datasheet); RD, the resistance of the current sensor (usually the MOSFET); ∆RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature); and ESR, the ESR of the output capacitors, per cap (44mΩ for the Sanyo parts shown in this datasheet). The value of R7 must be ≤ 8.3KΩ. If a greater value is calcu- lated, RD must be reduced. Number of capacitors needed for Cout = the greater of: Example: Suppose that the static limits are +89mV/-79mV , transient limits are ±134mV , current I is 14.2A, and the nominal voltage is 2.000V , using MOSFET current sensing. We have V = 14.2, Vnom = 2.000, and ∆RD = 1.67. We calculate: Since Y > X, we choose Y , and round up to find we need 7 capacitors for COUT. A detailed explanation of this calculation may be found in Applications Bulletin AB-24. Irms 1.01 * Vnom Vin Vnom Vin Vnom *IO Cin 45 * 10-6 IO* RD * (1 + ∆RD) R7 * 1KΩ VS+ – .024 * Vnom Roffset = 18 * (VS+ + VS- – .024 * Vnom) R5 = VT- + VS+ – .024 * Vnom ESR * IO ESR * IO 18 * R5 * 1.1 14400 * IO * RD Y or VT+ – VS+ + 2.000 2.000 *14.2 Cin 3.47 ⇒ 4 caps= == 3.48KΩ == 5.25KΩ 45 * 10-6 == 20.3Ω*1000 1.01 * 2.000 0.089 – .024 * 2.000 Roffset 3.57 0.044 * 14.2X == 6.14 18 * 3640 * 1.1 14400 * 14.2 * 0.0200.134 – 0.089 0.044 * 14.2 Y =

PRODUCT SPECIFICATION FAN5059 REV. 1.0.4 8/14/03 17 Mechanical Dimensions

24 Lead SOIC

A .093 .104 2.35 2.65 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .004 .012 0.10 0.30 .020 0.51B .013 0.33 C .009 .013 0.23 0.32 E .290 .299 7.36 7.60 e .394 .419 10.00 10.65 .010 .020 0.25 0.51 H .050 BSC 1.27 BSC h L .016 .050 0.40 1.27 0° 8° 0° 8° N2 4 2 4 α ccc .004 0.10—— D .599 .614 15.20 15.60 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). "L" is the length of terminal for soldering to a substrate. Terminal numbers are shown for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is the maximum number of terminals. HE A D e B – C – ccc C LEAD COPLANARITY SEATING PLANE α h x 45° L C

FAN5059 PRODUCT SPECIFICATION 8/14/03 0.0m 012 Stock#DS30005059  2000 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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