FAN4800A FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
Pin-to-Pin Compatible with ML4800 and FAN4800 and CM6800 and CM6800A PWM Configurable for Current-mode or Feed-forward Voltage-Mode Operation Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM in one IC Low Operating Current Innovative Switching-Charge Multiplier Divider Average-Current-Mode for Input-Current Shaping PFC Over-Voltage and Under-Voltage Protections PFC Feedback Open-Loop Protection Cycle-by-Cycle Current Limiting for PFC/PWM Power-on Sequence Control and Soft-Start Brownout Protection Interleaved PFC/PWM Switching FAN4801/1S/2/2L Improve Efficiency at Light Load fRTCT=4•fPFC=4•fPWM for FAN4800A and FAN4801/1S fRTCT=4•fPFC=2•fPWM for FAN4800C and FAN4802/2L
Applications
Desktop PC Power Supply Internet Server Power Supply LCD TV, Monitor Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power
Description
The highly integrated FAN4800A/C and FAN4801/1S/2/2L are specially designed for power supplies that consist of boost PFC and PWM. They require very few external components to achieve versatile protections / compensation. They are available in 16-pin DIP and SOP packages. The PWM can be used in either current or voltage mode. In voltage mode, feed-forward from the PFC output bus can reduce the secondary output ripple. Compared with older productions, ML4800 and FAN4800, FAN4800A/C and FAN4801/1S/2/2L have lower operation current that save power consumption in external devices. FAN4800A/C and FAN4801/1S/2/2L have accurate 49.9% maximum duty of PWM that makes the hold-up time longer. Specifically, the brownout protection and PFC soft-start functions are not in ML4800 and FAN4800. To start evaluating FAN4800A/C, FAN4801/1S/2/2L for replacing existing FAN4800 and ML4800 boards, five things must be done before the fine-tuning procedure: 1. Change R AC resister from the old value to a higher resister: between 6MΩ to 8MΩ. 2. Change RT/CT pin from the existing values to RT=6.8KΩ and C T=1000pF to have f PFC=64KHz, fPWM=64KHz. 3. VRMS pin needs to be 1.224V at V IN=85 V AC for universal input application from line input from 85V AC to 270 V AC. Both poles for the V rms of FAN4801/1S/2/2L don’t need to substantially slower than FAN4800; about 5 to 10 times. 4. At full load, the average V EA needs to ~4.5V and the ripple on the VEA needs to be less than 400mV. 5. Soft-Start pin, the soft-start current has been reduced to half from the FAN4800 capacitor. Related Resources Complete design instructions are detailed in application note AN-6078SC (available in Chinese only).
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 2 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination
Ordering Information
FAN4800ANY -40°C to +105°C Green 16-pi n Dual In-Line Package (DIP) Tube FAN4800CNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube FAN4800AMY -40°C to +105°C Green 16-pin Sm all Out-Line Package (SOP) Tape & Reel FAN4800CMY -40°C to +105°C Green 16-pin Sm all Out-Line Package (SOP) Tape & Reel FAN4801NY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube FAN4801SNY -40°C to +105°C Green 16-pi n Dual In-Line Package (DIP) Tube FAN4802NY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP)) Tube FAN4802LNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP)) Tube FAN4801MY -40°C to +105°C Green 16-pin Sma ll Out-Line Package (SOP) Tape & Reel FAN4801SMY -40°C to +105°C Green 16-pin Sm all Out-Line Package (SOP) Tape & Reel FAN4802MY -40°C to +105°C Green 16-pin Sma ll Out-Line Package (SOP) Tape & Reel FAN4802LMY -40°C to +105°C Green 16-pin Sma ll Out-Line Package (SOP) Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Part Number PFC:PWM Frequency Ratio Brown Out / In Range In / Out FAN4800ANY 1:1 1.05V / 1.90V N.A FAN4800AMY 1:1 1.05V / 1.90V N.A FAN4800CNY 1:2 1.05V / 1.90V N.A FAN4800CMY 1:2 1.05V / 1.90V N.A FAN4801NY 1:1 1.05V / 1.90V 1.95V / 2.45V FAN4801SNY 1:1 1.05V / 1.90V 2.80V / 3.35V FAN4802NY 1:2 1.05V / 1.90V 1.95V / 2.45V FAN4802LNY 1:2 0.90V / 1.65V 1.95V / 2.45V FAN4801MY 1:1 1.05V / 1.90V 1.95V / 2.45V FAN4801SMY 1:1 1.05V / 1.90V 2.80V / 3.35V FAN4802MY 1:2 1.05V / 1.90V 1.95V / 2.45V FAN4802LMY 1:2 0.90V / 1.65V 1.95V / 2.45V
Figure 1. Typical Application Current Mode
Figure 2. Typical Application Voltage Mode
Figure 5. Top Mark
Figure 6. Pin Configuration (Top View ) sawtooth to determine the pulse width for PFC gate drive. 2 IAC Input AC Current. For normal operation, this input provides current reference for the multiplier. The suggested maximum IAC is 100µA. multiplier and PFC ILIMIT comparator. 4 VRMS Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier. of a protection condition occurring and/or PWM disabled, the SS pin is quickly discharged. 6 FBPWM PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. 7 RT/CT Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp). 9 ILIMIT Peak Current Limit Setting for PWM. The peak current limits setting for PWM. clamped under 15V to protect the MOSFET. under 15V to protect the MOSFET. 9.3V, respectively. The operating current is lower than 10mA. 14 VREF Reference Voltage. Buffered output for the internal 7.5V reference. input of PFC error amplifier. This pin is connec ted to the PFC output through a divider network. 16 VEA Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 8 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VH SS, FBPWM, RAMP, OPWM, OPFC -0.3 30.0 V VL IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA -0.3 7.0 V VVREF VREF 7.5 V VIEA IEA 0 V VREF+0.3 V VN ISENSE -5.0 0.7 V IAC Input AC Current 1 mA IREF VREF Output Current 5 mA IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A IPWM-OUT Peak PWM OUT Current, Source or Sink 0.5 A PD Power Dissipation T A < 50°C 800 mW DIP 80.80 °C/W RΘ j-a Thermal Resistance (Junction to Air) SOP 104.10 °C/W TJ Operating Junction Temperature -40 +125 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Soldering) +260 °C Human Body Model 4.5 kV ESD Electrostatic Discharge Capability Charged Device Model 1000 V Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage to the device. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit TA Operating Ambient Temperature -40 +105 °C
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 9 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination
Electrical Characteristics
VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section IDD ST Startup Current V DD=VTH-ON-0.1V; OPFC OPWM Open 30 80 µA IDD-OP Operating Current V DD=13V; OPFC OPWM Open 2.0 2.6 5.0 mA VTH-ON Turn-on Threshold Voltage 10 11 12 V ΔVTH Hysteresis 1.5 1.9 V VDD-OVP VDD OVP 27 28 29 V ΔVDD-OVP VDD OVP Hysteresis 1 V Oscillator fOSC-RT/CT RT/CT Frequency R T=6.8kΩ, CT=1000pF 240 256 268 kHz PFC & PWM Frequency 60 64 67 fOSC FAN4800C,FAN4802/02L PWM Frequency RT=6.8kΩ, CT=1000pF 120 128 134 kHz fDV Voltage Stability 11V ≦ VDD ≦ 22V 2 % fDT Temperature Stability -40°C ~ +105°C 2 % fTV Total Variation (PFC & PWM)(1) Line, Temperature 58 70 kHz fRV Ramp Voltage (1) Valley to Peak 2.8 V IDischarge Discharge Current V RAMP=0V, VRT/CT=2.5V 6.5 15.0 mA fRANGE Frequency Range (1) 50 75 kHz tPFCD PFC Dead Time R T=6.8kΩ, CT=1000pF 400 600 800 ns VREF VVREF Reference Voltage I REF=0mA, CREF=0.1µF 7.4 7.5 7.6 V ΔVVREF1 Load Regulation of Reference Voltage CREF=0.1µF, IREF=0mA to 3.5mA VVDD=14V, Rise/Fall Time > 20µs 30 50 mV ΔVVREF2 Line Regulation of Reference Voltage CREF=0.1µF, VVDD=11V to 22V 25 mV ΔVVREF-DT (1) Temperature Stability -40°C ~ +105°C 0.4 0.5 % ΔVVREF-TV (1) Total Variation Line, Load, Temp 7.35 7.65 V ΔVVREF-LS (1) Long-Term Stability T J=125°C, 0 ~ 1000HRs 5 25 mV IREF-MAX. Maximum Current V VREF > 7.35V 5 mA IOS (1) Output Short Circuit 25 mA PFC OVP Comparator VPFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V ΔVPFC-OVP PFC OVP Hysteresis 200 250 300 mV Low-Power Detect Comparator VEAOFF VEA Voltage OFF OPFC 0.2 0.3 0.4 V VIN OK Comparator VRD-FBPFC Voltage Level on FBPFC to Enable OPWM During Startup 2.3 2.4 2.5 V ΔVRD-FBPFC Hysteresis 1.15 1.25 1.35 V
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 10 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics (Continued) VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units Voltage Error Amplifier FBPFC Input Voltage Range (1) 0 6 V Vref Reference Voltage at T=25°C 2.45 2.50 2.55 V AV Open-Loop Gain (1) 35 42 dB Gmv Transconductance V NONINV=VINV, VVEA=3.75V at T=25°C 50 70 90 µmho IFBPFC-L Maximum Source Current V FBPFC=2V, VVEA=1.5V 40 50 µA IFBPFC-H Maximum Sink Current V FBPFC=3V, VVEA=6V -50 -40 µA IBS Input Bias Current -1 1 µA VVEA-H Output High Voltage on VVEA 5.8 6 V VVEA-L Output Low Voltage on VVEA 0.1 0.4 V Current Error Amplifier VISENSE Input Voltage Range (ISENSE pin)(1) -1.5 0.7 V GmI Transconductance VNONINV=VINV, VIEA=3.75V 78 88 100 µmho VOFFSET Input Offset Voltage V VEA=0V, IAC Open -10 10 mV VIEA-H Output High Voltage 6.8 7.4 8.0 V VIEA-L Output Low Voltage 0.1 0.4 V IL Source Current V ISENSE=-0.6V, VIEA=1.5V 35 50 µA IH Sink Current V ISENSE=+0.6V, VIEA=4.0V -50 -35 µA AI Open-Loop Gain (1) 40 50 dB Tri-Fault Detect tFBPFC_OPEN Time to FBPFC Open (1) VFBPFC=VPFC-UVP to FBPFC OPEN, 470pF from FBPFC to GND 2 4 ms VPFC-UVP PFC Feedback Under- Voltage Protection 0.4 0.5 0.6 V Gain Modulator IAC Input for AC Current (1) Multiplier Linear Range 0 100 µA IAC=17.67µA, VRMS=1.080V VFBPFC=2.25V, at T=25°C 7.50 9.00 10.50 IAC=20µA, VRMS=1.224V VFBPFC=2.25V, at T=25°C 6.30 7.00 7.70 IAC=25.69µA, VRMS=1.585V VFBPFC=2.25V, at T=25°C 3.80 4.20 4.60 IAC=51.62µA, VRMS=3.169V VFBPFC=2.25V, at T=25°C 0.95 1.05 1.16 GAIN GAIN Modulator (2) IAC=62.23µA, VRMS=3.803V VFBPFC=2.25V, at T=25°C 0.66 0.73 0.80 BW Bandwidth (1) I AC=40µA 2 kHz Vo(gm) Output Voltage=5.7kΩ × (ISENSE-IOFFSET)(1) IAC=20µA, VRMS=1.224V VFBPFC=2.25V, at T=25°C 0.74 0.82 0.90 V
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 11 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics (Continued) VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units PFC ILIMIT Comparator VPFC-ILIMIT Peak Current Limit Threshold Voltage, Cycle-by-Cycle Limit ΔVpk PFC ILIMIT-Gain Modulator Output IAC=17.67µA, VRMS=1.08V VFBPFC=2.25V, at T=25°C 200 mV PFC Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 13 15 17 V VGATE-L Gate Low Voltage V DD=15V; IO=100mA 1.5 V VGATE-H Gate High Voltage V DD=13V; IO=100mA 8 V tr Gate Rising Time V DD=15V; CL=4.7nF; O/P=2V to 9V 40 70 120 ns tf Gate Falling Time V DD=15V; CL=4.7nF; O/P=9V to 2V 40 60 110 ns DPFC-MAX Maximum Duty Cycle V IEA<1.2V 94 97 % DPFC-MIN Minimum Duty Cycle V IEA>4.5V 0 % Brown Out FAN4800A/C, FAN4801/1S/2 1.00 1.05 1.10 V VRMS-UVP VRMS Threshold Low FAN4802L 0.85 0.90 0.95 V FAN4800A/C, FAN4801/1S/2 1.85 1.90 1.95 V VRMS-UVP VRMS Threshold High FAN4802L 1.60 1.65 1.70 V FAN4800A/C, FAN4801/1S/2 750 850 950 mV ΔVRMS-UVP Hysteresis FAN4802L 650 750 850 mV tUVP Under-Voltage Protection Delay Time 340 410 480 ms Soft Start VSS-MAX Maximum Voltage V DD=15V 9.5 10.0 10.5 V ISS Soft-Start Current 10 µA PWM ILIMIT Comparator VPWM-ILIMIT Threshold Voltage 0.95 1.00 1.05 V tPD Delay to Output 250 ns tPWM-Bnk Leading-Edge Blanking Time 170 250 350 ns Range (FAN4801/1S/2/2L) VRMS-L RMS AC Voltage Low When V RMS=1.95V at132Vrms 1.90 1.95 2.00 V VRMS-H RMS AC Voltage High When V RMS=2.45V at150Vrms 2.40 2.45 2.50 V VEA Low 1.90 1.95 2.00 VEA-L VEA Low (FAN4801S) When VVEA=1.95V at 30% Loading, When VVEA=2.80V at 60% Loading 2.75 2.80 2.85 V VEA High 2.40 2.45 2.50 VEA-H VEA High (FAN4801S) When VVEA=2.45V at 40% Loading, When VVEA=3.35V at 70% Loading 3.30 3.35 3.40 V Itc Two-Level Current FBPFC Two-Level Current 18 20 22 µA
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 12 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics (Continued) VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units PWM Output Driver VGATE-CLAMP Gate Output Clamping Voltage V DD=22V 13 15 17 V VGATE-L Gate Low Voltage V DD=15V; IO=100mA 1.5 V VGATE-H Gate High Voltage V DD=13V; IO=100mA 8 V tr Gate Rising Time V DD=15V; CL=4.7nF 30 60 120 ns tf Gate Falling Time V DD=15V; CL=4.7nF 30 50 110 ns DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 % VPWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V Notes: 3. This parameter, although guaranteed by design, is not 100% production tested.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 18 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Functional Description The FAN4800A/C and FAN4801/1S/2/2L consist of an average current controlled, continuous boost Power Factor Correction (PFC) front-end and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the line regulation of PWM. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This patented leading/trailing edge modulation results in a higher usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800A, FAN4801/1S operates at the same frequency as the PFC; and FAN4800C, FAN4802/2L operates at double with PFC. In addition to power factor correction, a number of protection features are built into this series. They include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout (UVLO). Gain Modulator The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, required in high-power, switching-power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS (except at unusually low values of V RMS, where special gain contouring takes over to limit power dissipation of the circuit components under brownout conditions). 3. The output of the voltage error amplifier, VEA. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is: (0 . 7 ) GAINMOD IAC VEAIK VRMS ×−= × (1) Note that the output current of the gain modulator is limited around 159 μA and the maximum output voltage of the gain modulator is limited to 159 μA x 5.7K=0.906V. This 0.906V also determines the maximum input power. However, I GAINMOD cannot be measured directly from ISENSE. ISENSE =IGAINMOD – I OFFSET and I OFFSET can only be measured when VEA is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 31μA ~ 48μA. Selecting RAC for IAC Pin The IAC pin is the input of the gain modulator and also a current mirror input and requires current input. Selecting a proper resistor R AC provides a good sine wave current derived from the line voltage and helps program the maximum input power and minimum input line voltage. R AC=VIN peak x 56K Ω. For example, if the minimum line voltage is 75V AC, the R AC=75 x 1.414 x 56KΩ=6MΩ. Current Amplifier Error, IEA The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current, which results in a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin. PFC Cycle-By-Cycle Current Limiter As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is less than -1.15V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.
for certain PFC fault conditions. senses the error and terminates the PFC output drive. no external components to serve its protective function. sense equals IGAINMOD x 5.7KΩ. ripple on the VEA needs to be less than 400mV. where 5.6 is VEA maximum output. 90VAC, the PFC soft-start time is 90ms. than FAN4801/1S/2 that the VRMS is less than 0.9V. referred in application note AN-6078SC.
- Protection: During startup or inrush current
- To reduce L, the boost inductor: The ISENSE filter
FILTER, is approximately 100nF. Figure 45. Compensation Network Connection for the
FAN4801/1S/2/2L can be programmable. Figure 46. Two-Level PFC Scheme at VREF=7.5V and tRT/CT=CT x RT x 0.56. but there are several points that should be noted. a voltage ramp against which FBPWM is compared. input is used for output stage over-current protection. input voltages below typical 1.5V. startup of the PWM begins at 1.5V.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 21 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination PWM Control (RAMP) When the PWM section is used in current mode, RAMP is generally used as the sampling point for a voltage, representing the current in the primary of the PWM’s output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP is the input for a ramp voltage generated by a second set of timing components RAMP, CRAMP) that have a minimum value of 0V and a peak value of approximately 6V. In voltage mode, feed forward from the PFC output bus is an excellent way to derive the timing ramp for the PWM stage. Generating VDD After turning on the FAN4800A/C, FAN4801/1S/2/2L at 11V, the operating voltage can vary from 9.3V to 28V. The threshold voltage of the V DD OVP comparator is 28V and its hysteresis is 1V. When V DD reaches 28V, OPFC is LOW, and the PWM section is not disturbed. There are two ways to generate V DD: use auxiliary power supply around 15V or use bootstrap winding to self-bias the FAN4800A/C, FAN4801/1S/2/2L system. The bootstrap winding can be taped from the PFC boost choke or the transformer of the DC-to-DC stage. Leading/Trailing Modulation Conventional PWM techniques employ trailing-edge modulation, in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. In the case of leading-edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off-time of the switch.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
5.33 MAX
Figure 47. 16-pin Dual In-Line Package (DIP) the warranty therein, which covers Fairchild products.
Figure 48. 16-Pin Small Outline Package (SOIC) the warranty therein, which covers Fairchild products.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 24 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination