FAN4800CU ONSEMI | Alldatasheet

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© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.4 FAN4800AU/CU — PFC/ PWM Controller Combination FAN4800AU / FAN4800CU PFC/ PWM Controller Combination

Features

 Pin-to-Pin Compatible with ML4800, FAN4800, CM6800, and CM6800A  PWM Configurable for Current-Mode or Feed-Forward Voltage-Mode Operation  Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM in One IC  Low Operating Current  Innovative Switching-Charge Multiplier Divider  Average-Current-Mode for Input-Current Shaping  PFC Over-Voltage and Under-Voltage Protections  PFC Feedback Open-Loop Protection  Cycle-by-Cycle Current Limiting for PFC/PWM  Power-on Sequence Control and Soft-Start  Line Sagging Protection  fRTCT=4•fPFC=4•fPWM for FAN4800AU  fRTCT=4•fPFC=2•fPWM for FAN4800CU

Applications

 Desktop PC Power Supply  Internet Server Power Supply  LCD TV/ Monitor Power Supply  UPS  Battery Charger  DC Motor Power Supply  Monitor Power Supply  Telecom System Power Supply  Distributed Power Related Resources  AN-8027 — FAN480X PFC+PWM Combination Controller Application

Description

The highly in tegrated FAN4800AU/CU parts are specially designed for power supplies that consist of boost PFC and PWM. They require very few external components to achieve versatile protections and compensation. They are available in 16 -pin DIP and SOP packages. The PWM can be used in current or Voltage Mode. In Voltage Mode, feed -forward from the PFC output bus can reduce secondary output ripple. To evaluate FAN4800AU/CU for replacing existing FAN4800A/C, FAN4800AS/CS, old version FAN4800 and ML4800 board s, six things must be completed before the fine-tuning procedure: 1. Change RAC resistor from the old value to a higher resistor value: 6 M to 8 M. 2. Change RT/CT pin from the exi sting value s to RT=6.8 k and C T=1000 pF to have fPFC=64 kHz and fPWM=64 kHz. 3. The VRMS pin needs to be 1.224 V at V IN=85 VAC for universal input application with line input from 85 VAC to 270 VAC. 4. Change ISENSE pin filter from the exiting values to RFilter=51  and CFilter=0.01 µF for higher bandwidth. 5. At full load, the average V VEA must be ~4.5 V and ripple on VVEA needs to be less than 400 mV. 6. For the SS pin, the soft -start current has been reduced to half the FAN4800 capacitor. There are two differences from FAN4800AS/CS to FAN4800AU/CU:  Add Line Sagging Protection  Fix Inductance Current Instability during AC Cycle Drop Test

FAN4800AU/CU — PFC/ PWM Controller Combination © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.4

Ordering Information

PFC:PWM Frequency Ratio Package Packing Method FAN4800AUN -40°C to +105°C 1:1 16-Pin Dual Inline Package (DIP) Tube FAN4800CUN 1:2 FAN4800AUM 1:1 16-Pin Small Outline Package (SOP) Tape & Reel FAN4800CUM 1:2 Block Diagram VDD 15 12 OPFC

11 OPWM

2.5V/2.75V 0.5V -1.3V ISENSE 0.3V VEA VDD 27V/28V 1mA ZERO POWER PFC OVP VDD OVP S R Q Q S R Q Q 300µA Gain Modulator k 5.7KΩ PFC SAW Dead-Time 2.5V VRMS 1.9V 1.05V Debounce 1ms S R Q Q Debounce 30ms 0.85V VRMS VIN OFFBOP BI BOP 10µA 10V 300Ω UVLOVIN OFF Level Shift 1.5V S R Q Q FBPFC 2.4V 1.3V BI VIN OFF VIN OK S R Q Q1V Blanking PWM Max. Duty VDD VDD 7.5V REFERENCE UVLO 11V/9V PFC UVP PFC ILIMIT PWM ILIMIT VIN UVLO ILIMIT IAC FBPFC VEA ISENSE IEA FBPWM SS AC UVLO GMi GMv

10 GND

10µA 4VRMS PWM Max. Duty Dead-Time PFC SAWRT/CT 300Ω PWM Max. Duty

14 VREF

33µA VDD Figure 1. Function Block Diagram

Figure 6. Pin Configuration (Top View) sawtooth to determine the pulse width for the PFC gate drive. multiplier. The suggested maximum IAC is 65 µA. multiplier and PFC ILIMIT comparator. 4 VRMS Line-Voltage Detection. The pin is used for the PFC multiplier. protection condition occurs and/or PWM is disabled, the SS pin is quickly discharged. 6 FBPWM PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. 7 RT/CT Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. Mode, it is the feed-forward sense input from PFC output 380 V (feed-forward ramp). 9 ILIMIT Peak Current Limit Setting for PWM. The peak current limit setting for PWM.

10 GND Ground

clamped under 19 V to protect the MOSFET. under 15 V to protect the MOSFET. 9.3 V, respectively. The operating current is lower than 10 mA. 14 VREF Reference Voltage. Buffered output for the internal 7.5 V reference. of PFC error amplifier. This pin is connected to the PFC output through a divider network. 16 VEA Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.4 6 FAN4800AU/CU — PFC/ PWM Controller Combination Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VH Voltage on SS, FBPWM, RAMP, VREF Pins -0.3 30.0 V VPFC-OUT Voltage on OPFC Pin VDD +0.3V V VPWM-OUT Voltage on OPWM Pin VDD +0.3V V VL Voltage on IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA Pins -0.3 7.0 V VIEA Voltage on IEA Pin 0 VVREF+0.3 V VN Voltage on ISENSE Pin -5.0 0.7 V IAC Input AC Current 1 mA IREF VREF Output Current 5 mA IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A IPWM-OUT Peak PWM OUT Current, Source or Sink 0.5 A PD Power Dissipation TA < 50°C 800 mW ΘJA Thermal Resistance (Junction to Air) DIP 80.80 °C/W SOP 104.10 ΘJC Thermal Resistance (Junction to Case) DIP 35.38 °C/W SOP 40.41 TJ Operating Junction Temperature -40 +125 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature(Soldering) +260 °C ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 6.0 kV Charged Device Model, JESD22-C101 2.0 Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairch ild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit TA Operating Ambient Temperature -40 +105 °C

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.4 7 FAN4800AU/CU — PFC/ PWM Controller Combination

Electrical Characteristics

Unless otherwise noted, VDD=15 V, TA= 25°C, TA=TJ, RT=6.8 kΩ, and CT=1000 pF. Symbol Parameter Condition Min. Typ. Max. Unit VDD Section IDD-ST Startup Current VDD=VTH-ON-0.1V, OPFC OPWM Open 30 80 µA IDD-OP Operating Current VDD=13 V, OPFC OPWM Open 2.0 2.6 5.0 mA VTH-ON Turn-on Threshold Voltage 10 11 12 V △VTH Hysteresis 1.3 1.9 V VDD-OVP VDD OVP 27 28 29 V △VDD-OVP VDD OVP Hysteresis 1 V Oscillator fOSC-RT/CT RT/CT Frequency RT=6.8 kΩ, CT=1000 pF 240 256 268 kHz fOSC PFC & PWM Frequency 60 64 67 kHz FAN4800CU PWM Frequency 120 128 134 fDV Voltage Stability(3) 11 V ≦ VDD ≦ 22 V 2 % fDT Temperature Stability(3) -40°C ~ +105°C 2 % fTV Total Variation (PFC & PWM)(3) Line, Temperature 58 70 kHz fRV Ramp Voltage Valley to Peak 2.8 V IOSC-DIS Discharge Current VRAMP=0 V, VRT/CT=2.5 V 6.5 15.0 mA fRANGE Frequency Range 50 75 kHz tPFC-DEAD PFC Dead Time RT=6.8 kΩ, CT=1000 pF 400 600 800 ns VVREF VVREF Reference Voltage IVREF=0 mA, CVREF=0.1 µF 7.4 7.5 7.6 V △VVREF1 Load Regulation of Reference Voltage CVREF=0.1 µF, IVREF=0 mA to 3.5 mA VDD=14 V, Rise/Fall Time > 20 µs 30 50 mV △VVREF2 Line Regulation of Reference Voltage CVREF=0.1 µF, VDD=11V to 22 V 25 mV △VVREF-DT Temperature Stability(3) -40°C ~ +105°C 0.4 0.5 % △VVREF-TV Total Variation(3) Line, Load, Temperature 7.35 7.65 V △VVREF-LS Long-Term Stability(3) TJ=125°C, 0 ~ 1000 Hours 5 25 mV IVREF-MAX. Maximum Current VVREF > 7.35 V 5 mA PFC OVP Comparator VPFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V △VPFC-OVP PFC OVP Hysteresis 200 250 300 mV Low-Power Detect Comparator VVEAOFF VEA Voltage OFF OPFC 0.2 0.3 0.4 V VIN OK Comparator VRD-FBPFC Voltage Level on FBPFC to Enable OPWM During Startup 2.3 2.4 2.5 V △VRD-FBPFC Hysteresis 1.0 1.1 1.2 V Continued on the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.4 8 FAN4800AU/CU — PFC/ PWM Controller Combination Electrical Characteristics (Continued) Unless otherwise noted, VDD=15 V, TA= 25°C, TA=TJ, RT=6.8 kΩ, and CT=1000 pF. Symbol Parameter Condition Min. Typ. Max. Unit Voltage Error Amplifier VREF Reference Voltage 2.45 2.50 2.55 V AV Open-Loop Gain(3) 35 42 dB Gmv Transconductance VNONINV=VINV, VVEA=3.75 V 50 70 90 µmho IFBPFC-L Maximum Source Current VFBPFC=2 V, VVEA=1.5 V 40 50 µA IFBPFC-H Maximum Sink Current VFBPFC=3 V, VVEA=6 V -50 -40 µA IBS Input Bias Current -1 1 µA VVEA-H Output High Voltage on VVEA 5.8 6.0 V VVEA-L Output Low Voltage on VVEA 0.1 0.4 V Current Error Amplifier GmI Transconductance VNONINV=VINV, VIEA=3.75 V 70 88 105 µmho VOFFSET Input Offset Voltage VVEA=0 V, IAC Open -10 10 mV VIEA-H Output High Voltage 6.8 7.4 7.8 V VIEA-L Output Low Voltage 0.1 0.4 V IL Source Current VISENSE= -0.6 V, VIEA=1.5 V 35 50 µA IH Sink Current VISENSE= +0.6 V, VIEA=4.0 V -50 -35 µA AI Open-Loop Gain(3) 40 50 dB TriFault Detect™ tFBPFC-OPEN Time to FBPFC Open VFBPFC=VPFC-UVP to FBPFC OPEN, 470 pF from FBPFC to GND 2 4 ms VPFC-UVP PFC Feedback Under-Voltage Protection 0.4 0.5 0.6 V Gain Modulator IAC Input for AC Current(3) Multiplier Linear Range 0 65 µA GAIN Gain Modulator(4) IAC=17.67 µA, VRMS=1.080 V VFBPFC=2.25 V 7.94 IAC=20 µA, VRMS=1.224 V VFBPFC=2.25 V 7.02 IAC=25.69 µA, VRMS=1.585 V VFBPFC=2.25 V 4.18 IAC=51.62 µA, VRMS=3.169 V VFBPFC=2.25 V 1.05 IAC=62.23 µA, VRMS=3.803 V VFBPFC=2.25 V 0.73 BW Bandwidth(3) IAC=40 µA 2 kHz VO(gm) Output Voltage=5.7 kΩ × (ISENSE-IOFFSET) IAC=50 µA, VRMS=1.224 V VFBPFC=2.25 V 0.76 0.80 0.84 V PFC ILIMIT Comparator VPFC-ILIMIT Peak Current Limit Threshold Voltage, Cycle-by-Cycle Limit -1.2 -1.3 -1.4 V △VPK PFC ILIMIT-Gain Modulator Output IAC=17.67 µA, VRMS=1.08 V VFBPFC=2.25 V 400 mV Continued on the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.4 9 FAN4800AU/CU — PFC/ PWM Controller Combination Electrical Characteristics (Continued) Unless otherwise noted, VDD=15 V, TA= 25°C, TA=TJ, RT=6.8 kΩ, and CT=1000 pF. Symbol Parameter Condition Min. Typ. Max. Unit PFC Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22 V 13 15 17 V VGATE-L Gate Low Voltage VDD=15 V, IO=100 mA 1.5 V VGATE-H Gate High Voltage VDD=13 V, IO=100 mA 8 V tR Gate Rising Time VDD=15 V, CL=4.7 nF, O/P= 2 V to 9 V 40 70 120 ns tF Gate Falling Time VDD=15 V, CL=4.7 nF, O/P=9 V to 2 V 40 60 110 ns DPFC-MAX Maximum Duty Cycle VIEA<1.2 V 94 97 % DPFC-MIN Minimum Duty Cycle VIEA>4.5 V 0 % PWM ILIMIT Comparator VPWM-ILIMIT Threshold Voltage 0.95 1.00 1.05 V tPD Propagation Delay to Output 250 ns tPWM-BNK Leading-Edge Blanking Time 170 250 350 ns PWM Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22 V 18 19 20 V VGATE-L Gate Low Voltage VDD=15 V, IO=100 mA 1.5 V VGATE-H Gate High Voltage VDD=13 V, IO=100 mA 8 V tR Gate Rising Time VDD=15 V, CL=4.7 nF, O/P=2 V to 9 V 30 60 120 ns tF Gate Falling Time VDD=15 V, CL=4.7 nF, O/P=9 V to 2 V 30 50 110 ns DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 % VPWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V Soft-Start VSS-MAX Maximum Voltage VDD=15 V 9.5 10.0 10.5 V ISS Soft-Start Current 10 µA Brownout VRMS-UVL VRMS Threshold LOW 1.00 1.05 1.10 V VRMS-UVH VRMS Threshold HIGH 1.85 1.90 1.95 V △VRMS-UVP Hysteresis 750 850 950 mV tUVP Under- Voltage Protection Delay 750 1000 1250 ms Sagging Protection VRMS-SAG VRMS Threshold SAG LOW 0.80 0.85 0.90 V tSAG SAG Protection Delay 28 33 38 ms Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This gain is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH.

line is recovered from dropout, as shown in Figure 36. Figure 36. AC Cycle Drop

1.3 V, the downstream DC -DC converter can stop

sag, FAN4800AU/CU has line sag protection. Figure 37. The second condition is when V RMS is lower operation until V RMS increases above 1.9 V. Figure 37. The First Condition of Sag Protection Figure 38. The Second condition of Sag Protection

5.33 MAX

0.38 MIN

4.95 2.92 3.81 2.92 1.78 1.14 0.56 0.36 2.54 FRONT VIEW C 19.69 18.67 7.11 6.10 (0.40) TOP VIEW A B 0.28 0.20 10.92 8.25 7.62 SIDE VIEW NOTES: A. CONFORMS TO JEDEC MS-001, VARIATION BB B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-2009 E. DRAWING FILENAME: MKT-N16Erev3 1 8 916

0.25 M C

PIN #1 FRONT VIEW TOP VIEW SEE DETAIL A SEATING PLANE C GAGE PLANE[ƒ DETAIL ASCALE: 2:1 BA 6.008.894.003.80 10.009.80 (0.30)1.27 0.25CBA LAND PATTERN RECOMMENDATION1 0.510.31 1.501.25 3.857.351.270.65 1.758.89

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