FAN4149

FAN4149 ONSEMI | Alldatasheet

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© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4149 • Rev. 1.0.0 FAN4149 — Ground Fault Interrupter FAN4149 Ground Fault Interrupter

Features

 M eets 2015 UL943 Self-Test R equirements (in combination with FAN41501)  Precision Sense Amplifier and Bandgap R eference  Low-VOS Offset for Direct DC C oupling of Sense C oil  Built-in N oise Filter  High-Current SCR Gate Driver  Adjustable Sensitivity  500 µA Quiescent C urrent  Minimum External C omponents  Ideal for 120 V or 220 V Systems  Space-Saving, SOT23 , 6-Pin Package

Applications

 GFCI O utput R eceptacle  GFCI C ircuit Breakers  Portable GFCI C ords  Residual-Current Devices (RCD)

Description

The FAN4149 is a low-power controller for detecting hazardous current paths to ground and ground-to- neutral faults. The FAN4149 application circuit opens the load contacts before a harmful shock occurs. The FAN4149 , in combination with the FAN41501 auto- monitoring digital controller, meets the 2015 UL943 self- test requirements for permanently connected GFCI products. The FAN4149 detects and protects against a hot-wire-to-ground fault and a neutral-to-line/load short. The FAN41501 periodically monitors the FAN4149 and critical GFI components to comply with the 2015 UL943 requirements. The minimum number of components and the small 6-pin package allow for a dense, flexible, application solution. The FAN4149 contains a precision bandgap 14 V shunt regulator, precision low-VOS sense amplifier, time-delay noise filter, window-detection comparators, and an SCR driver. The shunt regulator operates with a low quiescent current, which allows for a high value, low- wattage series supply resistor. The internal temperature compensated shunt regulator, sense amplifier, and bias circuitry provide for precision ground-fault detection. This enables the use of larger component variations so that binning or trimming external components is not required. The typical ±50 µV VOS sense amplifier offset allows for direct DC coupling of the sense coil. This eliminates the large AC-coupling capacitor. The internal delay filter rejects high-frequency noise spikes comm on with inductive loads. This decreases false nuisance tripping. The SCR driver provides increased current and temperature compensation to allow for a wider selection of external SCRs. The minimum number of external components and the 6-pin SOT23 package allow a low-cost, compact design and layout.

Ordering Information

Temperature Range Package Packing Method FAN4149M6X - 35°C to +85°C 6- Lead, SOT23, JEDEC M0-178, 1.6 mm Tape and Reel

Figure 3. Pin Configuration

1 SCR Gate drive for external SCR

2 GND Supply input for FAN4149 circuitry

3 VS Supply input for FAN4149 circuitry

4 VREF Non -inverting input for current sense amplifier

5 VFB Inverting input for current sense amplifier

6 Amp Out An external resistor connected to VFB sets the IFAULT sensitivity threshold

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4149 • Rev. 1.0.0 4 FAN4149 — Ground Fault Interrupter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parame ter Condition Min. Max. Unit ICC Supply Current Continuous Current, VS to GND 15 mA VCC Supply Voltage Continuous Voltage to GND, All Pins - 0.8 16.0 V TSTG Storage Temperature Range -65 +150 °C ESD Electrostatic Discharge Capability Human Body Model, ANSI/ESDA/JEDEC JS -001-2012 2.5 kV Charged Device Model, JESD22-C101 1 .0 Unless otherwise specified, TA=25°C, Ishunt=1 mA, and referencing Figure 2. Symbol Parameter Conditions Min. Typ. Max. Unit VREG Power Supply Shunt Regulator Voltage VS to GND 13.7 14.0 14.3 V IQ Quiescent Current Line to GND=10 V 425 500 575 µA VREF Reference Voltage V REF to GND 6.85 7.00 7.15 V VTH Trip Threshold Amp Out to VREF 4.35 4.50 4.65 V VOS Amplifier Offset Gain=1000 - 175 ±50 175 µV Amplifier Offset Drift(4) Gain=1000 - 100 100 µV IOS Amplifier Input Offset(5) Design Value - 50 0 50 nA G Amplifier DC Gain(5) Design Value 100 dB fGBW Amplifier Gain Bandwidth(5) Design Value 3 MHz VSW+ Amplifier Positive Voltage Swing Amp Out to VREF, IFAULT =10 µA 5.5 V VSW - Amplifier Negative Voltage Swing VREF to Amp Out, IFAULT =-10 µA 5.5 V ISINK Amplifier Current Sink Amp Out=V REF + 3 V VFB =V REF + 100 mV 400 µA ISRL Amplifier Current Source Amp Out=V REF – 3 V,VFB =V REF -100 mV 400 µA td Delay Filter Delay from C1 Trip to SCR L->H 0.65 1.00 1.35 ms R OUT SCR Output Resistance SCR to GND=250 mV, Amp Out=V REF 0.5 1 .0 kΩ VOUT SCR Output Voltage SCR to GND, Amp Out=VREF 1 10 mV SCR Output Voltage SCR to GND, AMP Out=VREF +4 V 3.0 V IOUT SCR Output Current SCR to GND=1 V Amp Out=VREF + 4 V, ISHUNT =2 mA 650 725 µA Notes: 4. Maximum V OS offset temperature cycling drift from initial value (JEDEC JESD22 -A104). 5. Guaranteed by design, not tested in production.

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4149 • Rev. 1.0.0 5 FAN4149 — Ground Fault Interrupter Functional Description Refer to Figure 2. The FAN4149 is a GFCI controller for AC ground-fault circuit interrupters. The low-VOS offset for the sense amplifier allows for direct DC coupling of the sense coil when the FAN4149 is biased with a full-wave diode bridge. This allows for the FAN4149 to be used with the FAN4150 1 digital auto-monitoring controller to provide for a low-BOM-cost, complete, GFI solution with self testing for the critical GFCI components. The internal shunt regulator rectifier circuit is supplied from the full-wave rectifier bridge and 75 kΩ series resistor. A typical 220 nF VS bypass capacitor is used to filter the VAC ripple voltage. The internal 14 V shunt regulator uses a precision temperature-compensated bandgap reference. The combination of precision reference circuitry and precision sense amplifier provides for an accurate ground-fault tolerance. This allows for selection of external components with wider and lower-cost parameter variations. Due to the low quiescent current, a high-value external series resistor (R1) can be used to reduce the maximum power wattage required for this resistor. The 14 V shunt regulator generates the VREF reference voltage for the sense amplifier’s (A1) non -inverting input (AC ground reference). It also supplies the bias for the delay timer (t1), comparators (C1 & C2), and the SCR driver. The secondary winding of the sense transformer is connected to pin 4 (VREF) and to a resistor, RIN, which is directly DC connected to the inverting input of the sense amplifier at pin 5 (VFB). The feedback resistor (RSET ) converts the sense transformer’s secondary current to a voltage at pin 6 (Amp Out). This voltage is compared to the internal window comparator (C1 & C2). W hen the Amp Out voltage exceeds the ±VTH threshold voltage, the window comparator triggers the internal delay timer. The output of the window comparator must stay HIGH for the duration of the t1 timer. If the window comparator’s output goes LOW , the internal delay timer starts a reset cycle. If the window comparator’s output is still HIGH at the end of the t1 pulse, the SCR driver enables current source I1 and disables Q1 . Current source I1 then enables the external SCR; which energizes the solenoid, opens the contact switches to the load, and removes the hazardous ground fault. The window comparator allows for detection of a positive or negative IFAULT signal, independent from the phase of the line voltage. Ca lculation of R SET Resistor The Amp Out signal must exceed the window comparator’s VTH threshold voltage for longer than the delay timer and calculated by: VTH = IFAULT x 1.22 x RSET x COS(2π x (t/2P)) / N (1) R SET = (VTH x N) / (1.22 x IFAULT x COS(π x t/P)) (2) where: VTH = 4.5 V IFAULT = 5 mARMS (UL943) T = 1 ms (timer delay) P = Period of the AC Line (1/60 Hz) P = Period of the AC Line (1/60 Hz) N= Ratio of secondary-to-primary turns (1000:1) R SET = 750 kΩ (standard 1% value) In practice, the transformer is non-ideal, so RSET may need to be adjusted by up to 30% to obtain the desired IFAULT trip threshold. Calculation of VOS Trip Threshold Error Since the sense coil is directly connected to the feedback of the sense amplifier, the VOS offset introduces an IFAULT threshold error. This error can be calculated as follows: %Error =100 x (VOS x RSET ) / (RIN + RLDC ) / VTH (3) where: VOS = ±175 µV (worst case) ±50 µV (typical) R SET = 750 kΩ R IN = 470 Ω (typical value) R LDC = 75 Ω (sense coil secondary DC resistance) VTH = 4.5 V %Error = ± 5.4% (worst case) ± 1.5% (typical) The VOS ±100 µV maximum drift specification is based on temperature cycling per JEDEC JESD22-A104, Condition B, 850 temperature cycles at -55°C to +125°C. Grounded Neutral Detection If the neutral load terminal side is incorrectly connected to the earth ground, the sense coil does not correctly detect the hazardous ground fault current from “load hot” to earth ground due to the partial IFAULT current flowing from the grounded neutral fault (load neutral) to earth ground. To detect a grounded neutral fault, a grounded neutral coil is required. When a low resistive path occurs from the line neutral and load neutral terminals, the sense and neutral coils are mutually coupled. The mutual coupling produces a positive feedback path around the sense amplifier, which causes the sense amplifier to oscillate. When the peak oscillation voltage exceeds the SCR trigger threshold, the internal delay timer is enabled. Since the amplifier’s output signal is crossing the window comparator’s trip threshold typically at 6 kHz, the delay timer alternates between detection of a fault/no-fault. The ratio of the fault/no-fault detection time interval determines if the SCR driver is enabled. The sensitivity of the grounded neutral detection can be changed by the neutral coil turns and the value of C2 and C3.

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4149 • Rev. 1.0.0 6 FAN4149 — Ground Fault Interrupter GFCI Self Test Requirement Starting in June of 2015, UL943 require s all permanently connected GFCI products to perform a self-test function. By adding Fairchild’s FAN41501 product to the FAN4149 application (see Figure 2), a fully compliant 2015 UL943 self-test function can be achieved with two, small, independent, 6-pin, 1.6 mm- wide devices and a minimum number of external components. The 2015 UL code requires that, at power up, the GFCI self test the critical GFCI components -- FAN4149, SCR, sense coil, and solenoid -- within five seconds and thereafter within every three hours. The self-test cycle cannot open the load contacts. If a component failure is detected, the load power must be denied. Refer to the FAN41501 datasheet for more details about the UL943 self-test features.

Unless otherwise specified, TA=25°C and according to Figure 1 with SCR disconnected. Figure 8. Typical W aveform for G rounded N eutral

NOTES: A. THIS PACKAGE CONFORMS TO JEDEC MO-178, VARIATION AB. B. ALL DIMENSIONS ARE IN MILLIMETERS. C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. D. DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. E. DIMENSIONS AND TOLERANCING AS PER ASME Y14.5M-1994 F. DRAWING FILE NAME: MA06EREV2 1.30 0.90 0.15 0.058° SEATING PLANE

0.60 REF

0.60 0.30 FORMERLY: SCALE: 2:1 DETAIL A APPROVALS

5 JULY 07

SHEET :N/A OF1 1 1.6MM WIDE MO-178 VARIATION AB, 6LD,SOT23,JEDEC SEE DETAIL A GAGE PLANE 0.25

1.45 MAX

0.08 0.22 LAND PATTERN RECOMMENDATION RELEASE TO DOCUMENT CONTROL A CL REVISIONS E.C.N. DATE BY/APP'D C C0.10 1:1 NA/

0.15 C A-B

0.15 C 2X 3 TIPS 2.9 1.6 1.9 A 2.8 1.4

0.15 C D

0.95 B 2X 0.3-0.5

0.20 C A-B D

D PIN 1 INDEX AREA (0.95) (0.95) (1.00MIN) (1.90) (2.60) (0.70MIN) R0.10MIN R0.10MIN C D DC 11/4/2006 H.ALLEN 2 DWG UPDATED TO CONFORM TO MO178 5 JULY 07 L.HUEBENER L.HUEBENER H.ALLEN 17 JULY 07

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