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Technical content
Features
Industry-Standard Pinouts 4.5 to 18V Operating Range 5A Peak Sink/Source at VDD = 12V 4.3A Sink / 2.8A Source at VOUT = 6V TTL Input Thresholds Two Versions of Dual Independent Drivers: - Dual Inverting (FAN3213) - Dual Non-Inverting (FAN3214) Internal Resistors Turn Driver Off If No Inputs MillerDrive™ Technology 12ns / 9ns Typical Rise/Fall Times with 2.2nF Load Typical Propagation Delay Under 20ns Matched within 1ns to the Other Channel Double Current Capability by Paralleling Channels Standard SOIC-8 Package Rated from –40°C to +125°C Ambient
Applications
Switch-Mode Power Supplies High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control
Description
The FAN3213 and FAN3214 dual 4A gate drivers are designed to drive N- channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. They are both available with TTL input thresholds. Internal circuitry provides an under- voltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers f eature matched internal propagation delays between A and B channels for applications requiring dual gat e drives with critical timing, such as synchronous rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET. The FAN3213/14 drivers incorporate MillerDrive™ architecture for the final output stage. This bipolar- MOSFET combination provi des high current during the Miller plateau stage of the MO SFET turn-on / turn-off process to minimize switching loss, while providing rail- to-rail voltage swing and reverse current capability. The FAN3213 offers two inverting drivers and the FAN3214 offers two non-inverting drivers. Both are offered in a standard 8-pin SOIC package. FAN3213 FAN3214 Figure 1. Pin Configurations
Ordering Information
FAN3213TMX Dual Inverting Channels TTL SOIC-8 Tape & Reel 2,500 FAN3214TMX Dual Non-Inverting Channels TTL SOIC-8 Tape & Reel 2,500
Figure 2. SOIC-8 (Top View)
- Estimates derived from thermal simulati on; actual values depend on the application.
- Theta_JL ( JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
- Theta_JT ( JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
- Theta_JA ( ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
JESD51-5, and JESD51-7, as appropriate.
- Psi_JB ( JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
reference is defined as the PCB copper adjacent to pin 6.
- Psi_JT ( JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
Figure 3. Pin Configurations (Repeated) 1 NC No Connect. This pin can be grounded or left floating. 3 GND Ground. Common ground reference for input and output circuits.
7 OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above
present and VDD is above UVLO threshold. 6 VDD Supply Voltage. Provides power to the IC. present and VDD is above UVLO threshold. 8 NC No Connect. This pin can be grounded or left floating.
- Default input signal if no external connection is made.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.0.2 5 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD VDD to PGND -0.3 20.0 V VIN INA, INA+, INA–, INB, INB+ and INB– to GND GND - 0.3 V DD + 0.3 V VOUT OUTA and OUTB to GND GND - 0.3 V DD + 0.3 V TL Lead Soldering Temperature (10 Seconds) +260 ºC TJ Junction Temperature -55 +150 ºC TSTG Storage Temperature -65 +150 ºC ESD Electrostatic Discharge Protection Level Human Body Model, JEDEC JESD22-A114 4 kV Charged Device Model, JEDEC JESD22-C101 1 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device oper ation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDD Supply Voltage Range 4.5 18.0 V VIN Input Voltage INA, INA+, INA–, INB, INB+ and INB– 0 V DD V TA Operating Ambient Te mperature -40 +125 ºC
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.0.2 6 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V IDD Supply Current, Inputs Not Connected 0.70 0.95 mA VON Turn-On Voltage INA = V DD, INB = 0V 3.5 3.9 4.3 V VOFF Turn-Off Voltage INA = V DD, INB = 0V 3.3 3.7 4.1 V Inputs VIL_T INx Logic Low Threshold 0.8 1.2 V VIH_T INx Logic High Threshold 1.6 2.0 V IIN+ Non-Inverting Input IN from 0 to V DD -1.5 175.0 µA IIN- Inverting Input IN from 0 to V DD -175.0 1.5 µA VHYS_T TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V Output ISINK OUT Current, Mid-Voltage, Sinking (8) OUTx at VDD/2, CLOAD=0.22µF, f=1kHz 4.3 A ISOURCE OUT Current, Mid-Voltage, Sourcing (8) OUTx at VDD/2, CLOAD=0.22µF, f=1kHz -2.8 A IPK_SINK OUT Current, Peak, Sinking (8) C LOAD=0.22µF, f=1kHz 5 A IPK_SOURCE OUT Current, Peak, Sourcing (8) C LOAD=0.22µF, f=1kHz -5 A tRISE Output Rise Time (9) C LOAD=2200pF 12 20 ns tFALL Output Fall Time (9) C LOAD=2200pF 9 17 ns tD1, tD2 Output Propagation Delay, TTL Inputs (9) 0 - 5V IN, 1V/ns Slew Rate 9 17 29 ns Propagation Matching Between Channels INA=INB, OUTA and OUTB at 50% Point 2 4 ns IRVS Output Reverse Current Withstand (8) 500 mA Notes: 8. Not tested in production. 9. See Timing Diagrams of Figure 6 and Figure 7. Figure 6. Non-Inverting Timing Diagram Figure 7. Inverting Timing Diagram
individual current capacity. the curves plus this additional current. at the MOSFET gate is needed. Figure 28. MillerDrive™ Output Architecture commonly found on driver and controller bias circuits. load capacitance C EQV, defined here as Q GATE/VDD. a single channel is switching.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.0.2 14 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting j unction temperature in the application to ensure that t he part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gat e current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MO SFET at a specified gate- source voltage, V GS, with gate charge, Q G, at switching frequency, fSW, is determined by: PGATE = QG • VGS • fSW • n (2) where n is the number of driver channels in use (1 or 2). Dynamic Pre-Drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the graphs in Typical Performance Characteristics to determine the current I DYNAMIC drawn from V DD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD • n (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the fo llowing thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ = P TOTAL • JB + TB (4) where: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and T B = board temperature in location as defined in the Thermal Characteristics table. To give a numerical example, if the synchronous rectifier switches in the forward converter of Figure 33 are FDMS8660S, the datasheet gives a total gate charge of 60nC at VGS = 7V, so two devices in parallel would have 120nC gate charge. At a switching frequency of 300kHz, the total power dissipation is: PGATE = 120nC • 7V • 300kHz • 2 = 0.504W (5) PDYNAMIC = 7.5mA • 7V • 2 = 0.011W (6) PTOTAL = 0.515W ≈ 0.52W (7) The SOIC-8 has a junction-to-board thermal characterization parameter of JB = 42°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prev ented from exceeding the maximum rating of 150°C; with 80% derating, T J would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB,MAX = TJ - PTOTAL • JB (8)
Table 1. Related Products
- Typical currents with OUTx at 6V and V DD=12V.
- Thresholds proportional to an exte rnally supplied reference voltage.
B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
1.75 MAX
Figure 36. 8-Lead Small Outline Integrated Circuit (SOIC) specifically the warranty therein, which covers Fairchild products.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.0.2 18 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers