FAN3121 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

ƒ Industry-Standard Pin-out with Enable Input ƒ 4.5 to 18V Operating Range ƒ 11.4A Peak Sink at VDD = 12V ƒ 9.7A Sink / 7.1A Source at VOUT = 6V ƒ Inverting Configuration (FAN3121) and Non-Inverting Configuration (FAN3122) ƒ Internal Resistors Turn Driver Off If No Inputs ƒ 23ns/19ns Typical Rise/Fall Times with 10nF Load ƒ 20ns Typical Propagation Delay Time ƒ Choice of TTL or CMOS Input Thresholds ƒ MillerDrive™ Technology ƒ Available in Thermally Enhanced 3x3mm 8-Lead MLP or 8-Lead SOIC Package (Pb-Free Finish) ƒ Rated from –40°C to +125°C

Applications

ƒ Synchronous Rectifier Circuits ƒ High-Efficiency MOSFET Switching ƒ Switch-Mode Power Supplies ƒ DC-to-DC Converters ƒ Motor Control

Description

The FAN3121 and FAN3122 MOSFET drivers are designed to drive N-channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses. The drivers ar e available with either TTL (FAN312xT) or CMOS (FAN312xC) input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range. FAN312x drivers incorporate the MillerDrive™ architecture for the final output stage. This bipolar / MOSFET combination provides the highest peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process. The FAN3121 and FAN3122 drivers implement an enable function on pin 3 (EN), previously unused in the industry-standard pin-out. The pin is internally pulled up to V DD for active HIGH logic and can be left open for standard operation. The FAN3121/22 is available in a 3x3mm 8-lead thermally- enhanced MLP package or an 8-lead SOIC package. 3 6 4 5 VDD GND EN IN VDD OUT GND OUT 3 6 4 5 EN IN VDD GND VDD GND OUT OUT Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.0 2 FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

Ordering Information

FAN3121CMPX 3x3mm MLP-8 RoHS Tape & Reel 3,000 FAN3121CMX CMOS SOIC-8 RoHS Tape & Reel 2,500 FAN3121TMPX 3x3mm MLP-8 RoHS Tape & Reel 3,000 FAN3121TMX Inverting Channels + Enable TTL SOIC-8 RoHS Tape & Reel 2,500 FAN3122CMPX 3x3mm MLP-8 RoHS Tape & Reel 3,000 FAN3122CMX CMOS SOIC-8 RoHS Tape & Reel 2,500 FAN3122TMPX 3x3mm MLP-8 RoHS Tape & Reel 3,000 FAN3122TMX Non-Inverting Channels + Enable TTL SOIC-8 RoHS Tape & Reel 2,500 For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package Outlines Figure 3. 3x3mm MLP-8 (Top View) Figure 4. SOIC-8 (Top View)

  1. Estimates derived from thermal simulati on; actual values depend on the application.
  2. Theta_JL ( ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads

(including any thermal pad) that are typically soldered to a PCB.

  1. Theta_JT ( ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package,

assuming it is held at a uniform temperature by a top-side heatsink.

  1. Theta_JA ( ΘJA): Thermal resistance between junction and ambi ent, dependent on the PCB design, heat sinking,

JESD51-2, JESD51-5, and JESD51-7, as appropriate.

  1. Psi_JB ( ΨJB): Thermal characterization parameter providing correlation between semiconductor junction
  2. Psi_JT ( ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction

temperature and the center of the top of the pack age for the thermal environment defined in Note 4.

Figure 5. FAN3121 Pin Assignments (Repeated) Figure 6. FAN3122 Pin Assignments (Repeated) 4, 5 4, 5 GND Ground. Common ground reference for input and output circuits. is present and VDD is above the UVLO threshold. 1, 8 1, 8 V DD Supply Voltage. Provides power to the IC. be left floating or connected to GND; NOT suitable for carrying current.

  1. Default input signal if no external connection is made.

8 VDD

5 GND

Figure 7. Block Diagram

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.0 5 FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD V DD to GND -0.3 20.0 V VEN EN to GND GND - 0.3 V DD + 0.3 V VIN IN to GND GND - 0.3 V DD + 0.3 V VOUT OUT to GND GND - 0.3 V DD + 0.3 V TL Lead Soldering Temperature (10 Seconds) +260 ºC TJ Junction Temperature -55 +150 ºC TSTG Storage Temperature -65 +150 ºC Human Body Model, JEDEC JESD22-A114 2 ESD Electrostatic Discharge Protection Level Charged Device Model, JEDEC JESD22-C101 1 kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDD Supply Voltage Range 4.5 18.0 V VEN Enable Voltage EN 0 V DD V VIN Input Voltage IN 0 V DD V TA Operating Ambient Temperature -40 +125 ºC

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.0 6 FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

Electrical Characteristics

Unless otherwise noted, V DD=12V and T J=-40°C to +125°C. Currents are defi ned as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V TTL 0.65 0.90 IDD Supply Current, Inputs / EN Not Connected CMOS(8) 0.58 0.85 mA VON Turn-On Voltage 3.5 4.0 4.3 V VOFF Turn-Off Voltage 3.30 3.75 4.10 V Inputs (FAN312xT)(9) VIL_T INx Logic Low Threshold 0.8 1.0 V VIH_T INx Logic High Threshold 1.7 2.0 V IIN+ Non-Inverting Input Current IN from 0 to V DD -1 175 µA IIN- Inverting Input Current IN from 0 to V DD -175 1 µA VHYS_T TTL Logic Hysteresis Voltage 0.40 0.70 0.85 V Inputs (FAN312xC)(9) VIL_C INx Logic Low Threshold 30 38 %V DD VIH_C INx Logic High Threshold 55 70 %V DD IIN+ Non-Inverting Input Current IN from 0 to V DD -1 175 µA IIN- Inverting Input Current IN from 0 to V DD -175 1 µA VHYS_C CMOS Logic Hysteresis Voltage 12 17 24 %V DD ENABLE (FAN3121, FAN3122) VENL Enable Logic Low Threshold EN from 5V to 0V 1.2 1.6 2.0 V VENH Enable Logic High Threshold EN from 0V to 5V 1.8 2.2 2.6 V VHYS_T TTL Logic Hysteresis Voltage 0.2 0.6 0.8 V RPU Enable Pull-up Resistance 68 100 134 k Ω tD1, tD2 Propagation Delay, EN Rising (10) 8 17 27 ns tD1, tD2 Propagation Delay, EN Falling (10) 14 21 33 ns Output ISINK OUT Current, Mid-Voltage, Sinking (11) OUT at VDD/2, CLOAD=1.0µF, f=1kHz 9.7 A ISOURCE OUT Current, Mid-Voltage, Sourcing (11) OUT at VDD/2, CLOAD=1.0µF, f=1kHz 7.1 A IPK_SINK OUT Current, Peak, Sinking (11) C LOAD=1.0µF, f=1kHz 11.4 A IPK_SOURCE OUT Current, Peak, Sourcing (11) C LOAD=1.0µF, f=1kHz 10.6 A tRISE Output Rise Time (10) C LOAD=10nF 18 23 29 ns tFALL Output Fall Time (10) C LOAD=10nF 11 19 27 ns tD1, tD2 Output Propagation Delay, CMOS Inputs (10) 0 – 12VIN, 1V/ns Slew Rate 9 18 28 ns tD1, tD2 Output Propagation Delay, TTL Inputs (10) 0 – 5V IN, 1V/ns Slew Rate 9 23 35 ns IRVS Output Reverse Current Withstand (11) 1500 mA Notes: 8. Lower supply current due to inactive TTL circuitry. 9. EN inputs have modified TTL thres holds; refer to the ENABLE section. 10. See Timing Diagrams of Figure 8 and Figure 9. 11. Not tested in production.

Figure 8. Non-Inverting Figure 9. Inverting

the rise time from 0 to 3.3V should be 550ns or less. and the OUT pin of the driver. the turn-on / turn-off process. time at the MOSFET gate is needed. Figure 46. Miller Drive™ Output Architecture connected together on the PCB. temperature and / or voltage application ranges.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.0 16 FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, P GATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gate- source voltage, V GS, with gate charge, Q G, at switching frequency, fSW, is determined by: PGATE = QG • VGS • fSW (2) Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No-Load) vs. Frequency” graphs in Typical Performance Characteristics to determine the current I DYNAMIC drawn from V DD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming ψJB was determined for a similar thermal design (heat sinking and air flow): TJ = P TOTAL • ψJB + TB (4) where: TJ = driver junction temperature; ψJB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. In a full-bridge synchronous rectifier application, shown in Figure 53, each FAN3122 drives a parallel combination of two high-current MOSFETs, (such as FDMS8660S). The typical gate charge for each SR MOSFET is 70nC with V GS = V DD = 9V. At a switching frequency of 300kHz, the total power dissipation is: PGATE = 2 • 70nC • 9V • 300kHz = 0.378W (5) PDYNAMIC = 2mA • 9V = 18mW (6) PTOTAL = 0.396W (7) The SOIC-8 has a junction-to-board thermal characterization parameter of ψJB = 42°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the devic e must be prevented from exceeding the maximum rating of 150°C; with 80% derating, T J would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB,MAX = TJ - PTOTAL • ψJB (8) For comparison, replace the SOIC-8 used in the previous example with the 3x3mm MLP package with ψJB = 2.8°C/W. The 3x3mm MLP package can operate at a PCB temperature of 118°C, while maintaining the junction temperature below 120°C. This illustrates that the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from the driver. Consider tradeo ffs between reducing overall circuit size with junction temperature reduction for increased reliability.

Table 1. Related Products

  1. Typical currents with OUT at 6V and V DD = 12V.

B. DIMENSIONS ARE IN MILLIMETERS.

0.8 MAX

Figure 55. 3x3mm, 8-Lead Molded Leadless Package (MLP) specifically the warranty therein, which covers Fairchild products.

B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

1.75 MAX

Figure 56. 8-Lead SOIC specifically the warranty therein, which covers Fairchild products.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.0 21 FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver