DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 21

Technical content

Features

 Industry-Standard Pin-out with Enable Input  4.5-V to 18-V Operating Range  11.4 A Peak Sink at VDD = 12 V  9.7-A Sink / 7.1-A Source at VOUT = 6 V  Inverting Configuration (FAN3121) and Non-Inverting Configuration (FAN3122)  Internal Resistors Turn Driver Off If No Inputs  23-ns / 19-ns Typical Rise/Fall Times (10 nF Load)  20-ns Typical Propagation Delay Time  Choice of TTL or CMOS Input Thresholds  MillerDrive™ Technology  Available in Thermally Enhanced 3x3 mm 8-Lead MLP or 8-Lead SOIC Package (Pb-Free Finish)  Rated from –40°C to +125°C  Automotive Qualified to AEC-Q100 (F085 Versions)

Applications

 Synchronous Rectifier Circuits  High-Efficiency MOSFET Switching  Switch-Mode Power Supplies  DC-to-DC Converters  Motor Control  Automotive-Qualified Systems (F085 Versions)

Description

The FAN3121 and FAN3122 MOSFET drivers are designed to drive N-channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses. The drivers are available with either TTL input thresholds (FAN312xT) or V DD-proportional CMOS input thresholds (FAN312xC). Internal circuitry provides an under-voltage lockout functi on by holding the output low until the supply voltage is within the operating range. FAN312x drivers incorporate the MillerDrive™ architecture for the final output stage. This bipolar / MOSFET combination provides the highest peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process. The FAN3121 and FAN3122 drivers implement an enable function on pin 3 (EN), previously unused in the industry-standard pin-out. The pin is internally pulled up to V DD for active HIGH logic and can be left open for standard operation. The commercial FAN3121/22 is available in a 3x3 mm 8-lead thermally-enhanced MLP package or an 8-lead SOIC package. The AEC-Q 100 automotive-qualified versions are available in the 8-lead SOIC package. 3 6 4 5 VDD GND EN IN VDD OUT GND OUT 3 6 4 5 EN IN VDD GND VDD GND OUT OUT Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.2 2 FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver

Ordering Information

3x3 mm MLP-8 Tape & Reel 3,000 FAN3121CMX SOIC-8 Tape & Reel 2,500 FAN3121CMX_F085(1) SOIC-8 Tape & Reel 2,500 FAN3121TMPX TTL 3x3 mm MLP-8 Tape & Reel 3,000 FAN3121TMX SOIC-8 Tape & Reel 2,500 FAN3121TMX_F085 (1) SOIC-8 Tape & Reel 2,500 FAN3122CMPX Non-Inverting Channels + Enable CMOS 3x3 mm MLP-8 Tape & Reel 3,000 FAN3122CMX SOIC-8 Tape & Reel 2,500 FAN3122CMX_F085(1) SOIC-8 Tape & Reel 2,500 FAN3122TMPX TTL 3x3 mm MLP-8 Tape & Reel 3,000 FAN3122TMX SOIC-8 Tape & Reel 2,500 FAN3122TMX_F085(1) SOIC-8 Tape & Reel 2,500 All standard Fairchild Semiconductor products are RoHS compliant and many are also “Green” or going green. Green means the products are RoHS compliant AND they have limits on additional substances of Chlorine, Bromine and Antimony. For additional information on Fairchild’s “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Note: 1. Qualified to AEC-Q100. Package Outlines Figure 3. 3x3 mm MLP-8 (Top View) Figure 4. SOIC-8 (Top View)

  1. Estimates derived from thermal simulati on; actual values depend on the application.
  2. Theta_JL ( JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads

(including any thermal pad) that are typically soldered to a PCB.

  1. Theta_JT ( JT): Thermal resistance between the semiconductor junction and the top surface of the package,

assuming it is held at a uniform temperature by a top-side heatsink.

  1. Theta_JA ( ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,

JESD51-2, JESD51-5, and JESD51-7, as appropriate.

  1. Psi_JB ( JB): Thermal characterization parameter providing correlation between semiconductor junction
  2. Psi_JT ( JT): Thermal characterization parameter providing correlation between the semiconductor junction

temperature and the center of the top of the package for the thermal environment defined in Note 5.

4, 5 4, 5 GND Ground. Common ground reference for input and output circuits. input is present and VDD is above the UVLO threshold. 1, 8 1, 8 V DD Supply Voltage. Provides power to the IC. may be left floating or connected to GND; NOT suitable for carrying current. Figure 5. FAN3121 Pin Assignments (Repeated) Figure 6. FAN3122 Pin Assignments (Repeated)

  1. Default input signal if no external connection is made.

8 VDD

5 GND

Figure 7. Block Diagram

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.2 5 FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD V DD to GND -0.3 20.0 V VEN EN to GND GND - 0.3 V DD + 0.3 V VIN IN to GND GND - 0.3 V DD + 0.3 V VOUT OUT to GND GND - 0.3 V DD + 0.3 V TL Lead Soldering Temperature (10 Seconds) +260 °C TJ Junction Temperature -55 +150 °C TSTG Storage Temperature -65 +150 °C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device oper ation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDD Supply Voltage Range 4.5 18.0 V VEN Enable Voltage EN 0 V DD V VIN Input Voltage IN 0 V DD V TA Operating Ambient Te mperature -40 +125 ºC

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.2 6 FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver

Electrical Characteristics

Unless otherwise noted, V DD=12 V and T J=-40°C to +125°C. Currents are defi ned as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V IDD Supply Current, Inputs / EN Not Connected TTL 0.65 0.90 mA CMOS(9) 0.58 0.85 VON Turn-On Voltage 3.5 4.0 4.3 V VOFF Turn-Off Voltage 3.30 3.75 4.10 V FAN3121TMX_F085, FAN3122TMX_F085 (Automotive-Qualified Versions) VOFF Turn-Off Voltage (13) 3.25 3.75 4.15 V Inputs (TTL, FAN312xT)(10) VIL_T INx Logic Low Threshold 0.8 1.0 V VIH_T INx Logic High Threshold 1.7 2.0 V VHYS_T TTL Logic Hysteresis Voltage 0.40 0.70 0.85 V FAN3121TMX, FAN3122TMX IIN+ Non-Inverting Input Current IN from 0 to V DD -1 175 µA IIN- Inverting Input Current IN from 0 to V DD -175 1 µA FAN3121TMX_F085, FAN3122TMX_F085 (Automotive-Qualified Versions) IINx_T Non-inverting Input Current (13) IN=0 V -1.5 1.5 µA IINx_T Non-inverting Input Current (13) IN=V DD 90 120 175.0 µA IINx_T Inverting Input Current (13) IN=0 V -175 -120 -90 µA IINx_T Inverting Input Current (13) IN=V DD -1.5 1.5 µA Inputs (CMOS, FAN312xC)(10) VIL_C INx Logic Low Threshold 30 38 %V DD VIH_C INx Logic High Threshold 55 70 %V DD VHYS_C CMOS Logic Hysteresis Voltage 12 17 24 %V DD FAN3121CMX, FAN3122CMX IIN+ Non-Inverting Input Current IN from 0 to V DD -1 175 µA IIN- Inverting Input Current IN from 0 to V DD -175 1 µA FAN3121CMX_F085, FAN3122CMX_F085 (Automotive-Qualified Versions) IINx_C Non-Inverting Input Current (13) IN=0 V -1.5 1.5 µA IINx_C Non-Inverting Input Current (13) IN=V DD 90 120 175 µA IINx_C Inverting Input Current (13) IN=0 V -175 -120 -90 µA IINx_C Inverting Input Current (13) IN=V DD -1.5 1.5 µA ENABLE (FAN3121, FAN3122) VENL Enable Logic Low Threshold EN from 5 V to 0 V 1.2 1.6 2.0 V VENH Enable Logic High Threshold EN from 0 V to 5 V 1.8 2.2 2.6 V VHYS_T TTL Logic Hysteresis Voltage 0.2 0.6 0.8 V RPU Enable Pull-up Resistance 68 100 134 k Ω tD1, tD2 Propagation Delay, CMOS EN (11) 8 17 27 ns tD1, tD2 Propagation Delay, TTL EN (11) 14 21 33 ns Continued on the following page…

  1. Lower supply current due to inactive TTL circuitry.
  2. EN inputs have modified TTL thres holds; refer to the ENABLE section.
  3. See Timing Diagrams of Figure 8 and Figure 9.
  4. Not tested in production.
  5. Automotive-qualified F 085 version specifications.

Figure 8. Non-Inverting Figure 9. Inverting

the rise time from 0 to 3.3 V should be 550 ns or less. and the OUT pin of the driver. the turn-on / turn-off process. at the MOSFET gate is needed. Figure 46. Miller Drive™ Output Architecture

4.0 V operational level, this circuit holds the output low,

connected together on the PCB. temperature and / or voltage application ranges.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.2 16 FAN3121 / FAN3122 — Single 9-A High-Speed Low-Side Gate Driver Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting j unction temperature in the application to ensure that t he part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gat e current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MO SFET at a specified gate- source voltage, V GS, with gate charge, Q G, at switching frequency, fSW, is determined by: PGATE = QG • VGS • fSW (2) Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No-Load) vs. Frequency” graphs in Typical Performance Characteristics to determine the current I DYNAMIC drawn from V DD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the fo llowing thermal equation, assuming  JB was determined for a similar thermal design (heat sinking and air flow): TJ = P TOTAL • JB + TB (4) where: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. In a full-bridge synchronous re ctifier application, shown in Figure 53, each FAN3122 drives a parallel combination of two high-cu rrent MOSFETs, (such as FDMS8660S). The typical gate charge for each SR MOSFET is 70 nC with V GS = V DD = 9V. At a switching frequency of 300 kHz, the total power dissipation is: PGATE = 2 • 70 nC • 9V • 300 kHz = 0.378 W (5) PDYNAMIC = 2 mA • 9 V = 18 mW (6) PTOTAL = 0.396 W (7) The SOIC-8 has a junction-to-board thermal characterization parameter of JB = 42°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prev ented from exceeding the maximum rating of 150°C; with 80% derating, T J would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB,MAX = TJ - PTOTAL • JB (8) For comparison, replace the SOIC-8 used in the previous example with the 3x3 mm MLP package with JB = 2.8°C/W. The 3x3 mm MLP package can operate at a PCB temperature of 118° C, while maintaining the junction temperature below 120° C. This illustrates that the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from the driver. Consider tradeo ffs between reducing overall circuit size with junction temperature reduction for increased reliability.

Table 1. Related Products

  1. Typical currents with OUT at 6 V and V DD = 12 V.
  2. Thresholds proportional to an exte rnally supplied reference voltage.
  3. Automotive-qualified F085 versions are only offered in SOIC8 packages.

B. DIMENSIONS ARE IN MILLIMETERS.

0.8 MAX

Figure 55. 3x3 mm, 8-Lead Molded Leadless Package (MLP) specifically the warranty therein, which covers Fairchild products.

B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

1.75 MAX

0.25 CBA

Figure 56. 8-Lead Small Outline Integrated Circuit (SOIC) specifically the warranty therein, which covers Fairchild products.

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.2 21 FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver