FAN3223_V01 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Industry−Standard Pinouts
- 4.5 V to 18 V Operating Range
- 5 A Peak Sink/Source at VDD = 12 V
- 4.3 A Sink / 2.8 A Source at VOUT = 6 V
- Choice of TTL or CMOS Input Thresholds
- Three Versions of Dual Independent Drivers: ♦ Dual Inverting + Enable (FAN3223) ♦ Dual Non−Inverting + Enable (FAN3224) ♦ Dual−Inputs (FAN3225)
- Internal Resistors Turn Driver Off If No Inputs
- MillerDrive Technology
- 12 ns / 9 ns Typical Rise/Fall Times (2.2 nF Load)
- Under 20 ns Typical Propagation Delay Matched within 1 ns to the Other Channel
- Double Current Capability by Paralleling Channels
- 8−Lead SOIC and 8−Lead SOIC Exposed Pad Package
- Rated from –40°C to +125°C Ambient
- Automotive Qualified to AEC-Q100
- These are Pb−Free Devices www.onsemi.com MARKING DIAGRAMS SOIC−8 EP CASE 751AC See detailed ordering and shipping information on page 21 of this data sheet.
ORDERING INFORMATION
SOIC−8 EP
Applications
- Switch−Mode Power Supplies
- High-Efficiency MOSFET Switching
- Synchronous Rectifier Circuits
- DC-to-DC Converters
- Motor Control
- Automotive-Qualified Systems Related Resources
- AN−6069 — Application Review and Comparative Evaluation of Low−Side Gate Drivers (Note: Microdot may be in either location) XXXXX AYWW/C0071 /C0071 XXX = Specific Device Code A = Assembly Lot Code Y = Year WW = Work Week /C0071= Pb−Free Package $Y = ON Semiconductor Logo Graphic &Z = Assembly Plant Code &2 = 2 −Digit Date Code (Year and Week) &K = 2 −Digit Lot Run Traceability Code SOIC8 $Y&Z&2&K FAN XXXXX
Figure 1. SOIC−8 (Top View) Figure 2. SOIC −8−EP
- Estimates derived from thermal simulation; actual values depend on the application.
- Theta_JL ( /C0081JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
that are typically soldered to a PCB.
- Theta_JT ( /C0081JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
temperature by a top−side heatsink.
- Theta_JA ( /C0081JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
- Psi_JB ( /C0089JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
is defined as the PCB copper adjacent to pin 6.
- Psi_JT ( /C0089JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
the top of the package for the thermal environment defined in Note 4.
Figure 3. Pin Assignment
1 ENB
1 INA+
- Default input signal if no external connection is made .
Figure 4. FAN3223 Block Diagram
6 VDD
8 ENB
Figure 5. FAN3224 Block Diagram
7 OUTA
Figure 6. FAN3225 Block Diagram
5 OUTB
should not be assumed, damage may occur and reliability may be affected. the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the device.) Symbol Parameter Characteristic Min Typ Max Unit SUPPLY [FAN322XT(MX/M1X)−F085, FAN322XCMX−F085] VDD Operating Range 4.5 18.0 V IDD Supply Current, Inputs / EN Not Connected All Except FAN3225C 0.70 1.20 mA FAN3225C (Note 8) 0.21 0.35 mA VON Turn−On Voltage INA = ENA = VDD, INB = ENB = 0 V 3.4 3.9 4.5 V VOFF Turn−Off Voltage INA = ENA = VDD, INB = ENB = 0 V 3.2 3.7 4.3 V SUPPLY [FAN3224TU(MX/M1X)−F085 (MODIFIED UVLO VERSION)] VDD Operating Range 9.5 18.0 V IDD Supply Current, Inputs / EN Not Connected 0.70 1.20 mA VON Turn−On Voltage INA = ENA = VDD, INB = ENB = 0 V 8.0 9.1 10.2 V VOFF Turn−Off Voltage INA = ENA = VDD, INB = ENB = 0 V 7.0 8.2 9.3 V INPUTS [FAN322XT(MX/M1X)−F085, FAN3224TU(MX/M1X)−F085] VINL_T INx Logic LOW Threshold 0.8 1.2 V VINH_T INx Logic HIGH Threshold 1.6 2.0 V VHYS_T TTL Logic Hysteresis Voltage 0.1 0.4 0.9 V IINx_T Non−inverting Input Current IN = 0 V −1.5 1.5 /C0109A IINx_T Non−inverting Input Current IN = VDD 80 120 175 /C0109A IINx_T Inverting Input Current IN = 0 V −175 −120 −90 /C0109A IINx_T Inverting Input Current IN = VDD −1.5 1.5 /C0109A INPUTS [FAN322XCMX−F085] VINL_C INx Logic Low Threshold 30 38 %VDD VINH_C INx Logic High Threshold 55 70 %VDD VHYS_C CMOS Logic Hysteresis Voltage 17 %VDD IINx_T Non−Inverting Input Current IN = 0 V −1.5 1.5 /C0109A IINx_T Non−Inverting Input Current IN = VDD 90 120 175 /C0109A IINx_T Inverting Input Current IN = 0 V −175 −120 −90 /C0109A IINx_T Inverting Input Current IN = VDD −1.5 1.5 /C0109A ENABLE [FAN3223(C/T)MX−F085, FAN3224(C/T/TU)(MX/M1X)−F085] VENL Enable Logic Low Threshold EN from 5 V to 0 V 0.8 1.2 V VENH Enable Logic High Threshold EN from 0 V to 5 V 1.6 2.0 V VHYS_T TTL Logic Hysteresis Voltage (Note 10) 0.4 V RPU Enable Pull−Up Resistance (Note 10) 100 k/C0087 tD3 EN to Output Propagation Delay (Note 11)
0 V to 5 V EN, 1 V/ns Slew Rate 6 17 34 ns
tD4 5 V to 0 V EN, 1 V/ns Slew Rate 6 19 31 ns
www.onsemi.com (Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the device.) Symbol UnitMaxTypMinCharacteristicParameter OUTPUTS [ALL EXCEPT FOR FAN3225(C/T)MX−F085] tRISE Output Rise Time (Note 12) CLOAD = 2200 pF 12 20 ns tFALL Output Fall Time (Note 12) CLOAD = 2200 pF 9 17 ns tDEL.MATCH Propagation Matching Between Channels INA = INB, OUTA and OUTB at 50% Point 2 4 ns IRVS Output Reverse Current Withstand (Note 10) 500 mA tD1, tD2 Output Propagation Delay, CMOS Inputs (Note 12) 0 – 12 VIN, 1 V/ns Slew Rate 9 18 34 ns tD1, tD2 Output Propagation Delay, TTL Inputs (Note 12) 0 – 5 VIN, 1 V/ns Slew Rate 6 16 30 ns VOH High Level Output Voltage VOH = VDD–VOUT, IOUT = –1 mA 15 35 mV VOL Low Level Output Voltage IOUT = 1 mA 10 25 mV [FAN3225(C/T)MX−F085] tRISE Output Rise Time (Note 12) CLOAD = 2200 pF 12 28 ns tFALL Output Fall Time (Note 12) CLOAD = 2200 pF 9 26 ns VOH High Level Output Voltage VOH = VDD–VOUT, IOUT = –1 mA 15 37 mV VOL Low Level Output Voltage IOUT = 1 mA 10 25 mV tDEL.MATCH Propagation Matching Between Channels INA = INB, OUTA and OUTB at 50% Point 2 4 ns 8. Lower supply current due to inactive TTL circuitry. 9. EN inputs have TTL thresholds; refer to the ENABLE section . 10.Not tested in production. 11. See Timing Diagrams of Figure 9 and Figure 10. 12.See Timing Diagrams of Figure 7 and Figure 8.
MOS devices pull the output to the HIGH or LOW rail. generally conducting before the MOSFET is switched ON. Figure 47. MillerDrive Output Architecture DD supply voltages have noise from the power switching. found on the driver and controller bias circuits. single channel is switching.
- Keep high−current output and power ground paths separate logic and enable input signals and signal ground paths. This is especially critical when dealing with TTL−level logic thresholds at driver inputs and enable pins
- Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve high-speed switching, while reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry
- If the inputs to a channel are not externally connected, the internal 100 kΩ resistors indicated on block diagrams command a low output. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching
www.onsemi.com Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming /C0089JB was determined for a similar thermal design (heat sinking and air flow): TJ /C0043PTOTAL /C0032/C0121JB /C0041TB (eq. 4) where: TJ = driver junction temperature; /C0089JB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and T B = board temperature in location as defined in the Thermal Characteristics table. To give a numerical example, assume for a 12 V V DD (VBIAS) system, the synchronous rectifier switches of Figure 56 have a total gate charge of 60 nC at V GS = 7 V . Therefore, two devices in parallel would have 120 nC gate charge. At a switching frequency of 300 kHz, the total power dissipation is: PGATE /C0043120nC /C00327V /C0032300 kHz /C00322 /C00430.504 W (eq. 5) PDYNAMIC /C00433.0 mA /C003212 V /C00321 /C00430.036 W (eq. 6) PTOTAL /C00430.540 W (eq. 7) The SOIC −8 has a junction −to−board thermal characterization parameter of /C0089JB = 42°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; with 80% derating, T J would be limited to 120 °C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB, MAX /C0043TJ /C0042PTOTAL /C0032/C0121JB (eq. 8) TB, MAX /C0043120°C /C00420.54 W /C003242°C/C0324W /C004397°C (eq. 9)
www.onsemi.com Part Number Logic Input Threshold Package Packing Method Quantity per Reel FAN3223CMX-F085 Dual Inverting Channels + Dual Enable CMOS SOIC−8 Tape & Reel 2,500 FAN3223TMX-F085 TTL SOIC−8 Tape & Reel 2,500 FAN3224CMX-F085 Dual Non−Invert- ing Channels + Dual Enable CMOS SOIC−8 Tape & Reel 2,500 FAN3224TMX-F085 TTL SOIC−8 Tape & Reel 2,500 FAN3224TM1X−F085 SOIC−8−EP Tape & Reel 2,500 FAN3224TUMX−F085 (Note 15) SOIC−8 Tape & Reel 2,500 FAN3224TUM1X−F085 (Note 15) SOIC−8−EP Tape & Reel 2,500 FAN3225CMX-F085 Dual Channels of Two−Input / One −Output Drivers CMOS SOIC−8 Tape & Reel 2,500 FAN3225TMX-F085 TTL SOIC−8 Tape & Reel 2,500 15.Modified UVLO thresholds.
RELATED PRODUCTS
(Note 17) (Sink/Src) Input Threshold Logic Package Dual 2 A FAN3216T +2.4 A / −1.6 A TTL Dual Inverting Channels SOIC8 Dual 2 A FAN3217T +2.4 A / −1.6 A TTL Dual Non−Inverting Channels SOIC8 Dual 2 A FAN3226C +2.4 A / −1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8 Dual 2 A FAN3226T +2.4 A / −1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8 Dual 2 A FAN3227C +2.4 A / −1.6 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8 Dual 2 A FAN3227T +2.4 A / −1.6 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8 Dual 2 A FAN3228C +2.4 A / −1.6 A CMOS Dual Channels of Two−Input/One−Output, Pin Config.1 SOIC8 Dual 2 A FAN3228T +2.4 A / −1.6 A TTL Dual Channels of Two−Input/One−Output, Pin Config.1 SOIC8 Dual 2 A FAN3229C +2.4 A / −1.6 A CMOS Dual Channels of Two−Input/One−Output, Pin Config.2 SOIC8 Dual 2 A FAN3229T +2.4 A / −1.6 A TTL Dual Channels of Two−Input/One−Output, Pin Config.2 SOIC8 Dual 2 A FAN3268T +2.4 A / −1.6 A TTL 20 V Non−Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables SOIC8 Dual 4 A FAN3213T +4.3 A / −2.8 A TTL Dual Inverting Channels SOIC8 Dual 4 A FAN3214T +4.3 A / −2.8 A TTL Dual Non−Inverting Channels SOIC8 Dual 4 A FAN3223C +4.3 A / −2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8 Dual 4 A FAN3223T +4.3 A / −2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8 Dual 4 A FAN3224C +4.3 A / −2.8 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8 Dual 4 A FAN3224T +4.3 A / −2.8 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, SOIC8−EP Dual 4 A FAN3225C +4.3 A / −2.8 A CMOS Dual Channels of Two−Input/One−Output SOIC8 Dual 4 A FAN3225T +4.3 A / −2.8 A TTL Dual Channels of Two−Input/One−Output SOIC8 Single 9 A FAN3121C +9.7 A / −7.1 A CMOS Single Inverting Channel + Enable SOIC8 Single 9 A FAN3121T +9.7 A / −7.1 A TTL Single Inverting Channel + Enable SOIC8 Single 9 A FAN3122T +9.7 A / −7.1 A TTL Single Non−Inverting Channel + Enable SOIC8, SOIC8−EP Single 9 A FAN3122C +9.7 A / −7.1 A CMOS Single Non−Inverting Channel + Enable SOIC8 16.Typical currents with OUTx at 6 V and VDD = 12 V. 17.Thresholds proportional to an externally supplied reference voltage. MillerDrive is trademarkof Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SOIC−8 EP CASE 751AC ISSUE D DATE 02 APR 2019 GENERIC MARKING DIAGRAM* XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week /C0071 = Pb−Free Package SCALE 1:1 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present and may be in either location. Some products may not follow the Generic Marking. XXXXX AYWW/C0071 /C0071 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON14029DDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1SOIC−8 EP © Semiconductor Components Industries, LLC, 2018 www.onsemi.com
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON13735GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1SOIC8 © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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