FAN3121 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
! Industry-Standard Pin-out with Enable Input ! 4.5-V to 18-V Operating Range ! 11.4 A Peak Sink at VDD = 12 V ! 9.7-A Sink / 7.1-A Source at VOUT = 6 V ! Inverting Configuration (FAN3121) and Non-Inverting Configuration (FAN3122) ! Internal Resistors Turn Driver Off If No Inputs ! 23-ns / 19-ns Typical Rise/Fall Times (10 nF Load) ! 18 ns to 23 ns Typical Propagation Delay Time ! Choice of TTL or CMOS Input Thresholds ! MillerDrive™ Technology ! Available in Thermally Enhanced 3x3 mm 8-Lead MLP or 8-Lead SOIC Package (Pb-Free Finish) ! Rated from –40°C to +125°C ! Automotive Qualified to AEC-Q100 (F085 Versions)
Applications
! Synchronous Rectifier Circuits ! High-Efficiency MOSFET Switching ! Switch-Mode Power Supplies ! DC-to-DC Converters ! Motor Control ! Automotive-Qualified Systems (F085 Versions)
Description
The FAN3121 and FAN3122 MOSFET drivers are designed to drive N -channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses. The drivers are available with either TTL input thresholds (FAN312xT) or VDD-proportional CMOS input thresholds (FAN312xC). Internal circuitry provides an under -voltage lockout function by holding the output low until the supply voltage is within the operating range. FAN312x drivers incorporate the MillerDrive™ architecture for the final output stage. This bipolar / MOSFET combination provides the highest peak current during the Miller plateau stage of the MOSFET turn -on / turn-off process. The FAN3121 and FAN3122 drivers implement an enable function on pin 3 (EN), previously unused in the industry-standard pin- out. The pin is internally pulled up to V DD for active HIGH logic and can be left open for standard operation. The commercial FAN3121/22 is available in a 3x3 mm 8-lead thermally -enhanced MLP package or an 8 -lead SOIC package. The AEC -Q100 automotive -qualified versions are available in the 8 -lead SOIC package. Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration
www.onsemi.com FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Ordering Information
3x3 mm MLP-8 Tape & Reel 3,000 FAN3121CMX SOIC-8 Tape & Reel 2,500 FAN3121CMX-F085(1) SOIC-8 Tape & Reel 2,500 FAN3121TMPX TTL 3x3 mm MLP-8 Tape & Reel 3,000 FAN3121TMX SOIC-8 Tape & Reel 2,500 FAN3121TMX-F085 (1) SOIC-8 Tape & Reel 2,500 FAN3122CMPX Non-Inverting Channels + Enable CMOS 3x3 mm MLP-8 Tape & Reel 3,000 FAN3122CMX SOIC-8 Tape & Reel 2,500 FAN3122CMX-F085(1) SOIC-8 Tape & Reel 2,500 FAN3122TMPX TTL 3x3 mm MLP-8 Tape & Reel 3,000 FAN3122TMX SOIC-8 Tape & Reel 2,500 FAN3122TMX-F085(1) SOIC-8 Tape & Reel 2,500 Note: 1. Qualified to AEC-Q100. Package Outlines 1 8 4 5 Figure 3. 3x3 mm MLP-8 (Top View) Figure 4. SOIC-8 (Top View)
- Estimates derived from thermal simulation; actual values depend on the application.
- Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
- Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top -side heatsink.
- Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
JESD51-2, JESD51-5, and JESD51-7, as appropriate.
- Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction
- Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 5.
4, 5 4, 5 GND Ground. Common ground reference for input and output circuits. input is present and VDD is above the UVLO threshold. 1, 8 1, 8 VDD Supply Voltage. Provides power to the IC. may be left floating or connected to GND; NOT suitable for carrying current. Figure 5. FAN3121 Pin Assignments (Repeated) Figure 6. FAN3122 Pin Assignments (Repeated)
- Default input signal if no external connection is made .
Figure 7. Block Diagram operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect devic e reliability. The absolute maximum ratings are stress ratings only.
8 VDD
5 GND
www.onsemi.com FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDD Supply Voltage Range 4.5 18.0 V VEN Enable Voltage EN 0 VDD V VIN Input Voltage IN 0 VDD V TA Operating Ambient Temperature -40 +125 ºC
Electrical Characteristics
Unless otherwise noted, V DD=12 V and TJ=-40°C to + 125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V IDD Supply Current, Inputs / EN Not Connected TTL 0.65 0.90 mA CMOS(9) 0.58 0.85 VON Device Turn-On Voltage (UVLO) 3.5 4.0 4.3 V VOFF Device Turn-Off Voltage (UVLO) 3.30 3.75 4.10 V FAN3121-F085, FAN3122-F085 (Automotive-Q ualified Versions) VDD Operating Range 4.5 18.0 V IDD Supply Current, Inputs / EN Not Connected TTL 0.65 1.00 mA CMOS(9) 0.58 0.85 VON Device Turn-On Voltage (UVLO) 3.5 4.0 4.3 V VOFF Device Turn-Off Voltage (UVLO)(13) 3.25 3.75 4.15 V Inputs (TTL, FAN312xT) (10) VIL_T INx Logic Low Threshold 0.8 1.0 V VIH_T INx Logic High Threshold 1.7 2.0 V VHYS_T TTL Logic Hysteresis Voltage 0.40 0.70 0.85 V FAN3121TMX, FAN3122TMX IIN+ Non-Inverting Input Current IN from 0 to VDD -1 175 µA IIN- Inverting Input Current IN from 0 to VDD -175 1 µA FAN3121TMX-F085, FAN3122TMX-F085 (Autom otive-Qualified Versions) IINx_T Non-inverting Input Current(13) IN=0 V -1.5 1.5 µA IINx_T Non-inverting Input Current(13) IN=VDD 90 120 175 µA IINx_T Inverting Input Current(13) IN=0 V -175 -120 -90 µA IINx_T Inverting Input Current(13) IN=VDD -1.5 1.5 µA
www.onsemi.com FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver Symbol Parameter Conditions Min. Typ. Max. Unit Inputs (CMOS, FAN312xC) (10) VIL_C INx Logic Low Threshold 30 38 %VDD VIH_C INx Logic High Threshold 55 70 %VDD VHYS_C CMOS Logic Hysteresis Voltage 12 17 24 %VDD FAN3121CMX, FAN3122CMX IIN+ Non-Inverting Input Current IN from 0 to VDD -1 175 µA IIN- Inverting Input Current IN from 0 to VDD -175 1 µA FAN3121CMX-F085, FAN3122CMX-F085 (Automotive-Q ualified Versions) IINx_C Non-Inverting Input Current(13) IN=0 V -1.5 1.5 µA IINx_C Non-Inverting Input Current(13) IN=VDD 90 120 175 µA IINx_C Inverting Input Current(13) IN=0 V -175 -120 -90 µA IINx_C Inverting Input Current(13) IN=VDD -1.5 1.5 µA Electrical Characteristics (Continued) Unless otherwise noted, V DD=12 V and TJ=-40°C to + 125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit ENABLE (FAN3121, FAN3122) VENL Enable Logic Low Threshold EN from 5 V to 0 V 1.2 1.6 2.0 V VENH Enable Logic High Threshold EN from 0 V to 5 V 1.8 2.2 2.6 V VHYS_T TTL Logic Hysteresis Voltage 0.2 0.6 0.8 V RPU Enable Pull-up Resistance 68 100 134 k tD1, tD2 Propagation Delay, CMOS EN(11) 8 17 27 ns tD1, tD2 Propagation Delay, TTL EN(11) 14 21 33 ns ENABLE (FAN3121-F085, FAN3122-F085) (Automotive-Qualified Versions) VENL Enable Logic Low Threshold EN from 5 V to 0 V 1.2 1.6 2.0 V VENH Enable Logic High Threshold EN from 0 V to 5 V 1.8 2.2 2.6 V VHYS_T TTL Logic Hysteresis Voltage 0.20 0.60 0.85 V RPU Enable Pull-up Resistance 68 100 134 k tD1, tD2 Propagation Delay, CMOS EN (11) 6 17 35 ns tD1, tD2 Propagation Delay, TTL EN(11) 8 22 34 ns Outputs ISINK OUT Current, Mid-Voltage, Sinking(12) OUT at VDD/2, CLOAD=1.0 µF, f=1 kHz 9.7 A ISOURCE OUT Current, Mid-Voltage, Sourcing(12) OUT at VDD/2, CLOAD=1.0 µF, f=1 kHz 7.1 A IPK_SINK OUT Current, Peak, Sinking (12) CLOAD=1.0 µF, f=1 kHz 11.4 A IPK_SOURCE OUT Current, Peak, Sourcing (12) CLOAD=1.0 µF, f=1 kHz 10.6 A tRISE Output Rise Time(11) CLOAD=10 nF 18 23 29 ns tFALL Output Fall Time(11) CLOAD=10 nF 11 19 27 ns tD1, tD2 Output Propagation Delay, CMOS Inputs (11) 0 – 12 VIN, 1 V/ns Slew Rate 9 18 28 ns tD1, tD2 Output Propagation Delay, TTL Inputs (11) 0 – 5 VIN, 1 V/ns Slew Rate 9 23 35 ns IRVS Output Reverse Current Withstand (12) 1500 mA
- Lower supply current due to inactive TTL circuitry.
- EN inputs have modified TTL thresholds; refer to the ENABLE section.
- See Timing Diagrams of Figure 8 and Figure 9.
- Not tested in production.
- Automotive-qualified F085 version specifications.
Figure 8. Non-Inverting Figure 9. Inverting
For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching, even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed.
www.onsemi.com 16 FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gate-source voltage, VGS, with gate charge, QG, at switching frequency, fSW, is determined by: PGATE = QG • VGS • fSW (2) Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No-Load) vs. Frequency” graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming ψJB was determined for a similar thermal design (heat sinking and air flow): TJ = PTOTAL • ψJB + TB (4) where: TJ = driver junction temperature; ψJB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and
Figure 55. 3x3 mm, 8-Lead Molded Leadless Package (MLP) B. DIMENSIONS ARE IN MILLIMETERS.
0.8 MAX
Figure 56. 8-Lead Small Outline Integrated Circuit (SOIC) B) ALL DIMENSIONS ARE IN MILLIMETERS.
1.75 MAX
0.25 C B A
www.onsemi.com 21 FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver N. American Technical Support: 800-282-9855 Toll Free USA/Canada. Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative