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Technical content
Features
3 A Peak Sink/Source at VDD = 12 V 4.5 to 18 V Operating Range 2.5 A Sink / 1.8 A Source at VOUT = 6 V Dual-Logic Inputs Allow Configuration as Non-Inverting or Inverting w ith Enable Function Internal Resistors Turn Driver Off I f No Inputs 13 ns Typical Rise Time and 9 ns Typical Fall-Time w ith 1 nF Load Choice of TTL or CMOS Input Thresholds MillerDrive™ Technology Typical Propagation Delay Time Under 20 ns w ith Input Falling or Rising 6-Lead, 2x2 mm MLP or 5-Pin, SOT23 Packages Rated fr om –40°C to 125°C Ambient
Applications
Sw itched-Mode Pow er Supplies (SMPS) High-Efficiency MOSFET Sw itching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control
Description
The FAN3100 2 A gate driver is designed to drive an N - channel enhancement -mode MOSFET in low -side sw itching applications by providing high peak current pulses during the short sw itching intervals. The driver is available w ith either TTL (FAN3100T) or CM OS (FAN3100C) input thresholds. Internal circuitry provides an under -voltage lockout function by holding the output LOW until the supply voltage is w ithin the operating range. The FAN3100 delivers fast MOSFET sw i tching performance, w hich helps maximize efficiency in high - frequency pow er converter designs. FAN3100 drivers incorporate MillerDrive™ architecture for the final output stage. This bipolar-MOSFET combination provides high peak current during the Miller plateau stage of the MOSFET turn- on / turn- off process to mi nimize sw itching loss, w hile providing rail -to-rail voltage sw ing and reverse current capability. The FAN3100 also offers dual inputs that can be configured to operate in non- inverting or inverting mode and allow implementation of an enable function. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the pow er MOSFET off. The FAN3100 is available in a lead-free finish, 2x2 mm, 6- lead, Molded Leadless Package ( MLP) for the smallest size w ith excellent thermal performance; or industry- standard, 5-pin, SOT23. Functional Pin Configurations 1 6 IN+ AGND VDD IN- PGND OUT VDD GND IN+ IN− OUT
www.onsemi.com FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver Pin Definitions SOT23 Pin # MLP Pin # Name Pin Description 1 3 V DD Supply Voltage . Provides pow er to the IC. 2 A GND Analog ground for input signals (MLP only). Connect to PGND underneath the IC. 2 GND Ground (SOT-23 only). Common ground reference for input and output circuits. 3 1 IN+ Non-Inverting Input . Connect to V DD to enable output. 4 6 IN- Inverting Input . Connect to A GND or PGND to enable output. 5 4 OUT Gate Drive Output : Held LOW unless required inputs are present and VDD is above UVLO threshold. Pad P1 Thermal Pad (MLP only). Exposed metal on the bottom of the package, w hich is electrically connected to pin 5. 5 PGND Power Ground (MLP only). For output drive circuit; separates sw itching noise from inputs. Output Logic IN+ IN− OUT 0(7) 0 0 0(7) 1(7) 0 1 0 1 1 1(7) 0 Note : 7. Default input signal if no external connection is made.
1 VDD
5 OUT
2 GND
Figure 5. Simplified Block Diagram ( SOT23 Pin-out)
3 VDD
4 OUT
5 PGND
Figure 6. Simplified Block Diagram (MLP Pin -out)
www.onsemi.com FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute max imum r atings are stress ratings only. Symbol Parameter Min. Max. Unit VDD VDD to PGND -0.3 20.0 V VIN Voltage on IN+ and IN- to GND, A GND, or PGND GND - 0.3 VDD + 0.3 V VOUT Voltage on OUT to GND, A GND, or PGND GND - 0.3 VDD + 0.3 V TL Lead Soldering Temperature (10 Seconds) +260 ºC TJ Junction Temperature -55 +150 ºC TSTG Storage Temperature -65 +150 ºC Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDD Supply Voltage Range 4.5 18.0 V VIN Input Voltage IN+, IN- 0 VDD V TA Operating Ambient Temperature -40 +125 ºC
www.onsemi.com FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Electrical Characteristics
Unless otherw ise noted, VDD = 12 V, TJ = -40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V IDD Supply Current Inputs/EN Not Connected FAN3100C(8) 0.20 0.35 mA FAN3100T 0.50 0.80 mA VON Turn-On Voltage 3.5 3.9 4.3 V VOFF Turn-O ff Voltage 3.3 3.7 4.1 V Inputs (FAN3100T) VINL_T IN+, IN- Logic LOW Voltage, Maximum 0.8 V VINH_T IN+, IN- Logic HIGH Voltage, Minimum 2.0 V IIN+ Non-inverting Input IN from 0 to VDD -1 175 µA IIN- Inverting Input IN from 0 to VDD -175 1 µA VHYS IN+, IN- Logic Hysteresis Voltage 0.2 0.4 0.8 V Inputs (FAN3100C) VINL_C IN+, IN- Logic LOW Voltage 30 %VDD VINH_C IN+, IN- Logic HIGH Voltage 70 %VDD IINL IN Current, LOW IN from 0 to VDD -1 175 µA IINH IN Current, HIGH IN from 0 to VDD -175 1 µA VHYS_C IN+, IN- Logic Hysteresis Voltage 17 %VDD Output ISINK OUT Current, Mid-Voltage, Sinking(9) OUT at VDD/2, CLOAD = 0.1 µF, f = 1 kHz 2.5 A ISOURCE OUT Current, Mid-Voltage, Sourcing(9) OUT at VDD/2, CLOAD = 0.1 µF, f = 1 kHz -1.8 A IPK_SINK OUT Current, Peak, Sinking(9) CLOAD = 0.1 µF, f = 1 kHz 3 A IPK_SOURCE OUT Current, Peak, Sourcing(9) CLOAD = 0.1 µF, f = 1 kHz -3 A tRISE Output Rise Time(10) CLOAD = 1000 pF 13 20 ns tFALL Output Fall Time(10) CLOAD = 1000 pF 9 14 ns tD1, tD2 Output Prop. Delay, CMOS Inputs(10) 0 – 12 VIN; 1 V/ns Slew Rate 7 15 28 ns tD1, tD2 Output Prop. Delay, TTL Inputs(10) 0 – 5 VIN; 1 V/ns Slew Rate 9 16 30 ns IRVS Output Reverse Current Withstand(9) 500 mA Notes: 8. Low er supply current due to inactive TTL circuitry. 9. Not tested in production. 10. See Timing Diagrams of Figure 7 and Figure 8.
Figure 7. Non-Inverting Figure 8. Inverting
there is a hysteresis voltage of approximately 0.4 V. input, causing erratic operation. obtained from the curves plus this additional current. series resistor can be added. Figure 42. MillerDrive™ Output Architecture
3.9 V operational level, this circuit holds the output LOW ,
often found on driver and controller bias circuits. components of the current pulses.
w ww.onsemi.com FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver T able 1. Related Products Part Number Type Gate Dr ive(11) (Sink/Src) Input Threshold Logic Package FAN3100C Single 2 A +2.5 A / -1.8A CMOS Single Channel of Tw o-Input/One-Output S O T2 3-5, MLP6 FAN3100T Single 2 A +2.5 A / -1.8A TTL Single Channel of Tw o-Input/One-Output S O T2 3-5, MLP6 FAN3226C Dual 2 A +2.4 A / -
1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
FAN3226T Dual 2 A +2.4 A / -
1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
FAN3227C Dual 2 A +2.4 A / -
1.6 A CMOS Dual Non- Inverting Channels + Dual Enable SOIC8, MLP8
FAN3227T Dual 2 A +2.4 A / -
1.6 A TTL Dual Non- Inverting Channels + Dual Enable SOIC8, MLP8
FAN3228C Dual 2 A +2.4 A / - 1.6 A CMOS Dual Channels of Two- Input/One -Output, Pin Config.1 SOIC8, MLP8 FAN3228T Dual 2 A +2.4 A / - 1.6 A TTL Dual Channels of Two- Input/One -Output, Pin Config.1 SOIC8, MLP8 FAN3229C Dual 2 A +2.4 A / - 1.6 A CMOS Dual Channels of Two -Input/One -Output, Pin Config.2 SOIC8, MLP8 FAN3229T Dual 2 A +2.4 A / - 1.6 A TTL Dual Channels of Two- Input/One -Output, Pin Config.2 SOIC8, MLP8 FAN3223C Dual 4 A +4.3 A / -
2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
FAN3223T Dual 4 A +4.3 A / -
2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
FAN3224C Dual 4 A +4.3 A / -
2.8 A CMOS Dual Non- Inverting Channels + Dual Enable SOIC8, MLP8
FAN3224T Dual 4 A +4.3 A / -
2.8 A TTL Dual Non- Inverting Channels + Dual Enable SOIC8, M LP8
FAN3225C Dual 4 A +4.3 A / -
2.8 A CMOS Dual Channels of Two- Input/One -Output SOIC8, MLP8
FAN3225T Dual 4 A +4.3 A / -
2.8 A TTL Dual Channels of Two- Input/One -Output SOIC8, MLP8
Note : 11. Typical currents w ith OUT at 6 V and VDD = 12 V.
w ww.onsemi.com FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver Physical Dimensions TOP VIEW 0.05 C 0.05 C 2.0 2.0 PIN#1 IDENT A B SIDE VIEW RECOMMENDED LAND PATTERN BOTTOM VIEW SEATING PLANE 1 3 PIN #1 IDENT 0.65 1.30 1.21 0.52(6X) 0.90 0.42(6X)0.65 2.25 1.68 (0.40) (0.70) NOTES: A. PAC KAGE DOES NOT FULLY CONFORM T O JEDEC MO-229 REGISTRATION B. D IMENSIONS ARE IN MILLIMETERS. C. D IMENSIONS AND TOLERANCES PER ASM E Y14.5M, 2009. D. L AND PATTERN RECOMMENDATION IS EXIST ING INDUSTRY LAND PATTERN. E. D RAWING FILENAME: MKT-MLP06Krev5. 2.00±0.05 1.40±0.05 0.80±0.05 (0.20)4X 0.32±0.05
0.10 C A B
0.05 C 0.30±0.05 (6X) (6X) (0.60) 0.08 C 0.10 C 0.75±0.05 0.025±0.025 C 0.20±0.05 1.72 0.15 F igure 53. 2x2 mm, 6- Lead, Molded Leadless Package (M LP) P ackage drawings are provided as a service to custom ers considering ON Sem iconductor com ponents. Drawings m ay change in any m anner without notice. Please note the revision and/or date on the drawing and contact an ON Sem iconductor representative to verify or obtain the m ost recent revision. Package specifications do not expand the term s of ON Sem iconductor’s worldwide term s and conditions, specifically the warranty therein, which covers ON Sem iconductor products.
w ww.onsemi.com FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver Physical Dimensions LAND PATTERN RECOMMENDATION B A L C 0.10 C
0.20 C A B
0.60 REF
0.55
0.35 SEATING PLANE
0.25 GAGE PLANE NOTES: UNLESS OTHEWISE SPECIFIED A) T HIS PACKAGE CONFORMS TO JEDEC M O-178, ISSUE B, VARIATION AA, B) AL L DIMENSIONS ARE IN MILLIMETERS. 1.45 MAX1.30 0.90 0.15 0.05 1.90 0.95 0.50 0.30 3.00 2.60 1.70 1.50 3.00 2.80 SYMM C 0.950.95 2.60 0.70 1.00 SEE DETAIL A 0.22 0.08 C) MA05Brev5 TOP VIEW (0.30) F igure 54. 5-Lead SOT-23 Package drawings are provided as a service to custom ers considering ON Sem iconductor com ponents. Drawings m ay change in any m anner without notice. Please note the revision and/or date on the drawing and contact a n ON Sem iconductor representative to verify or obtain the m ost recent revision. Package specifications do not expand the term s of ON Sem iconductor’s worldwide term s and conditions, specifically the warranty therein, which covers ON Sem iconductor products.
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