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Document overview
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Technical content
Features
mWSaver™ Technology Provides Industry’s Best-in-Class Standby Power - Achieves <10mW Below Energy Star’s 5-Star Level: <30mW - Proprietary 500V High-Voltage JFET Startup Reduces Startup Resistor Loss - Low Operation Current in Burst Mode: 350µA Maximum Constant-Current (CC) Control without Secondary- Feedback Circuitry Fixed PWM Frequency at 85kHz with Frequency Hopping to Reduce EMI High-Voltage Startup Low Operating Current: 3.5mA Peak-Current-Mode Control with Slope Compensation Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection (Auto-Restart) VS Over-Voltage Protection (Latch Mode) VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 15V Fixed Over-Temperature Protection (Latch Mode) Available in an 8-Lead SOIC Package
Applications
Battery Chargers for Cellular Phones, Cordless Phones, PDAs, Digital Cameras, and Power Tools Replaces Linear Regulators and RCC SMPS
Description
The FAN302HLMY_F117 advanced PWM controller significantly simplifies isolated power supply design that requires CC regulation of t he output. The output current is precisely estimated with information in the primary side of the transformer and controlled with an internal compensation circuit. This removes the output current sensing loss and eliminates all external Control Circuitry (CC). The Green-Mode function, with an extremely low operating current (200µA) in Burst Mode, maximizes the light-load efficiency, enabling conformance to worldwide Standby Mode efficiency guidelines. Integrated protections include two-level pulse-by-pulse current limit, Over-Voltage Protection (OVP), brownout protection, and Over-Temperature Protection (OTP). Compared with a conventional approach using an external control circuit in the secondary side for CC regulation, the FAN302HLMY_F117 can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. Figure 1. Typical Output V-I Characteristic
Ordering Information
Temperature Range Package Packing Method FAN302HLMY_F117 -40°C to +105°C 8-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch Narrow Body Tape & Reel IO VO Maximum Typical Minimum
Figure 5. Pin Assignments estimate the output current for CC regulation. MOSFET. It is internally clamped at 15V. 3 VDD Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically connected to an external VDD capacitor. time based on the voltage of the auxiliary winding.
5 GND Ground
the internal PWM comparator. This feedback is used to control the duty cycle in CV regulation.
7 NC No Connect
8 HV High Voltage. This pin connects to the DC bus for high-voltage startup.
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN302HLMY_F117 • Rev. 1.0.1 4 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Absolute Maximum Ratings Stresses exceeding the Absolute Maximum Ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VHV HV Pin Input Voltage 500 V VVDD DC Supply Voltage (1,2) 30 V VVS VS Pin Input Voltage -0.3 7.0 V VCS CS Pin Input Voltage -0.3 7.0 V VFB FB Pin Input Voltage -0.3 7.0 V PD Power Dissipation (TA=25°C) 660 mW θJA Thermal Resistance (Junction-to-Air) 150 °C/W θJC Thermal Resistance (Junction-to-Case) 39 °C/W TJ Operating Junction Temperature -40 +150 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature, (Wave Soldering or IR, 10 Seconds) +260 °C ESD Electrostatic Discharge Capability Human Body Model, JEDEC:JESD22_A114 (Except HV Pin)(3) 5000 V Charged Device Model, JEDEC:JESD22_C101 (Except HV Pin) (3) 1500 Notes: 1. All voltage values, except differential vo ltages, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximu m Ratings may cause permanent damage to the device. 3. ESD ratings including the HV pin: HBM=400V, CDM=750V.
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN302HLMY_F117 • Rev. 1.0.1 5 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications
Electrical Characteristics
VDD=15V and TA=25°C unless noted. Symbol Parameter Condition Min. Typ. Max. Unit HV Section VHV-MIN Minimum Startup Voltage on HV Pin 50 V IHV Supply Current Drawn from HV Pin VHV=100V, VDD=0V, Controller Off 0.8 1.5 5.0 mA IHV-LC Leakage Current Drawn from HV Pin VHV=500V, VDD=15V (Controller On with Auxiliary Supply) 0.8 3.0 μA VDD Section VOP Continuous Operation Voltage Limited by VDD Over-Voltage Protection (OVP) 25 V VDD-ON Turn-On Threshold Voltage V DD Rising 15 16 17 V VDD-OFF Turn-Off Threshold Voltage V DD Falling 4.7 5.0 5.3 V VDD-LH Threshold Voltage for Latch-Off Release V DD Falling 2.5 V IDD-ST Startup Current V DD=VDD-ON – 0.16V 400 450 μA IDD-OP Operating Supply Current V DD=18V, f=fOSC, CGATE=1nF 3.5 4.0 mA IDD-BURST Burst-Mode Operating Supply Current V DD=8V, CGATE=1nF 200 350 μA VDD-OVP V DD Over-Voltage Protection Level 25.0 26.5 28.0 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time f=85kHz 100 180 μs Oscillator Section fOSC Frequency Center Frequency V CS=5V, VS=2.5, VFB=5V 82 85 88 kHz Hopping Range ±3 fOSC-CM-MIN Minimum Frequency for Continuous Conduction Mode (CCM) Prevention Circuit (4) 13 18 23 kHz fOSC-CCM Minimum Frequency in Constant Current (CC) Regulation VCS=5V, VS=0V 23 26 29 kHz Feedback Input Section AV Internal Voltage Scale-Down Ratio of FB ZFB FB Pin Input Impedance 38 42 44 k Ω VFB-OPEN FB Pin Pull-Up Voltage FB Pin Open 5.3 V VFB-L FB Threshold to Disable Gate Drive in Burst Mode VFB Falling,VCS=5V, VS=0V 1.2 1.4 1.6 V VFB-H FB Threshold to Enable Gate Drive in Burst Mode VFB Rising,VCS=5V, VS=0V 1.3 1.5 1.7 V Over-Temperature Protection Section TOTP Threshold for Over-Temperature Protection (OVP) +130 +140 +150 °C Continued on the following page…
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN302HLMY_F117 • Rev. 1.0.1 6 FAN302HLMY_F117— mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications Electrical Characteristics (Continued) VDD=15V and TA=25°C unless noted. Symbol Parameter Condition Min. Typ. Max. Unit Voltage-Sense Section ITC Bias Current V CS=5V 8.75 10.00 11.25 μA VVS-CM-MIN VS Sampling Voltage to Switch to the Second Pulse-by-Pulse Current Limit in Power Limit Mode(6) 0.55 V VVS-CM-MAX VS Sampling Voltage to Switch Back to the Normal Pulse-by-Pulse Current Limit(6) 0.75 V VSN-CC VS Sampling Voltage to Start Frequency Decreasing in CC Mode VCS=5V, fS1=fOSC-2KHz 2.05 2.15 2.25 V VSG-CC Vs Sampling Voltage to End Frequency Decreasing in CC Mode VCS=5V, fS2=fOSC-CCM +2KHz 0.45 0.70 0.95 V SG-CC Frequency Decreasing Slope of CC Regulation SG-CC= (fS1-fS2) / (VSN-CC- VSG-CC) 30 38 46 kHz/V VVS-OFFSET ZCD Comparator Internal Offset Voltage(6) 200 mV VVS-OVP Output Over-Voltage Protection with VS Sampling Voltage 2.70 2.80 2.85 V tVS-OVP Output Over-Voltage Protection Debounce Time fOSC=85kHz 100 180 μs Current-Sense Section VVR Internal Reference Voltage for CC Regulation 2.475 2.500 2.525 V VCCR Variation Test Voltage on CS Pin for CC Output (Non-Inverting Input of Error Amplifier for CC Regulation) V CS=0.47V 2.405 2.430 2.455 V VSTH Normal Current Limit Threshold Voltage 0.8 V VSTH-VA Second Current Limit Threshold Voltage, Power Limit Mode (VS<VVS-CM-MAX) VVS=0.3V 0.30 V tPD GATE Output Turn-Off Delay 100 150 ns tMIN Minimum On Time VCS=5V, VVS=2.5, VFB=5V (Test Mode) 430 530 630 ns tLEB Leading-Edge Blanking Time (6) 100 150 200 ns VSLOPE Slope Compensation(6) Maximum Duty Cycle 0.3 V GATE Section DMAX Maximum Duty Cycle 64 67 70 % VGATE-L Output Voltage Low V DD=25V, IO=10mA 0 1.5 V VGATE-H Output Voltage High V DD=8V, IO=1mA 5 8 V VGATE-H Output Voltage High V DD=5.5V, IO=1mA 4.0 5.5 V tr Rising Time V DD=15V, CGATE=1nF 100 140 180 ns tf Falling Time V DD=15V, CGATE=1nF 30 50 70 ns VGATE- CLAMP Gate Output Clamping Voltage V DD=25V 13 15 17 V Notes: 4. f OSC-CM-MIN occurs when the power unit enters CCM operation. 5. A V is a scale-down ratio of the internal voltage divider of the FB pin. 6. Guaranteed by design; not production tested.
- W1 consists of four layers with different number of tu rns. The number of turns of each layer is specified in Table
- Add one insulation tape between the second and third layers.
- W2 consists of two layers with triple-insulated wi re. The leads of positive and negative fly lines are 3.5cm and
- W3 is space winding in one layer.
Table 1. Transformer Winding Specifications
- W4 is the outermost and space winding.
Figure 43. 8-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch, Narrow Body specifically the warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/. B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
1.75 MAX
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN302HLMY_F117 • Rev. 1.0.1 18 FAN302HLMY_F117 — mWSaver™ PWM Controller for Low Standby Power Battery-Charger Applications