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Technical content
Features
VIN Range: 7 V to 15 V Using Internal Linear Regulator for Bias VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC Connected to Bypass Internal Regulator High Efficiency Continuous Output Current: 4 A MOSFETs RDS,ON (Typical): HS: 9.67 mΩ, LS: 5.46 mΩ Internal Linear Bias Regulator Internal VDDQ Resistor Divider Excellent Line and Load Transient Response Output Voltage Range: 0.5 to 1.5 V Programmable Frequency: 200 kHz to 1.5 MHz Programmable Soft-Start Low Shutdown Current Adjustable Sourcing Current Limit Internal Boot Diode Thermal Shutdown Halogen and Lead Free, RoHS Compliant
Applications
Bus Termination Servers and Desktop Computers NVDC Notebooks, Netbooks Game Consoles
Description
The FAN23SV04T is a highly efficient, integrated TinyBuck™ synchronous buck regulator for use in tracking applications, such as DDR termination rails. The V DDQ input includes an internal 2:1 resistive voltage divider to reduce total circuit size and component count. The regulator operates with an input range from 7 V to 15 V and s upports up to 4 A load currents. The device can operate from a 5 V rail (±10%) if V IN, PVIN, and PVCC are connected together to bypass the internal linear regulator. This device utilize s Fairchild’s constant on- time control architecture to provide excellent transient response and to maintain a relatively constant switching frequency. Switching frequency and sourcing over-current protection can be programmed to provide a flexible solution for various applications. Output over -current, and t hermal shutdown protections help prevent damage during fault conditions . A hysteresis feature restarts the device when normal operating temperature is reached.
Ordering Information
Part Number Configuration Operating Temperature Range Output Current Package FAN23SV04TMPX PWM Mode with VDDQ Tracking Input -40 to 85°C 4 A 34-Lead, PQFN, 5.5 mm x 5.0 mm Please address requests and support questions to tinybucksupport@fairchildsemi.com.
4 A Integrated Synchronous Buck Regulator for DDR Termination
Figure 1. Typical Application with VIN = 12 V Figure 2. Typical Application with VIN = 5 V
Figure 3. Block Diagram
Figure 4. Bottom View Figure 5. Top View PVIN P2; 5-11 Power input for the power stage. VIN 1 Power input to the linear regulator; used in the modulator for input voltage feed-forward. and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail. VCC 26 Power supply input for the controller. PGND 18-21 Power ground for the low-side power MOSFET and for the low-side gate driver. AGND P1; 4, 23 Analog ground for the analog portions of the IC and for substrate. SW P3; 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs. ILIM 24 Current limit. A resistor between ILIM and SW sets the current-limit threshold. FB 27 Output voltage feedback to the modulator. EN 29 Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable. to program on-time and switching frequency. NC 28, 33-34 Leave pin open or connect to AGND.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 5 FAN23SV04T — TinyBuck™ Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Condition Min. Max. Unit VPVIN Power Input Referenced to PGND -0.3 25.0 V VIN Modulator Input Referenced to AGND -0.3 25.0 V VBOOT Boot Voltage Referenced to PVCC -0.3 26.0 V Referenced to PVCC, <20 ns -0.3 30.0 V VSW SW Voltage to GND Referenced to PGND, AGND -1 25 V Referenced to PGND, AGND < 20 ns -5 25 V VBOOT Boot to SW Voltage Referenced to SW -0.3 6.0 V Boot to PGND Referenced to PGND -0.3 30 V VPVCC Gate Drive Supply Input Referenced to PGND, AGND -0.3 6.0 V VVCC Controller Supply Input Referenced to PGND, AGND -0.3 6.0 V VILIM Current Limit Input Referenced to AGND -0.3 6.0 V VFB Output Voltage Feedback Referenced to AGND -0.3 6.0 V VEN Enable Input Referenced to AGND -0.3 6.0 V VSS Soft Start Input Referenced to AGND -0.3 6.0 V VFREQ Frequency Input Referenced to AGND -0.3 6.0 V VDDQ VDDQ Input Referenced to AGND -0.3 6.0 V ESD Electrostatic Discharge Human Body Model, JESD22-A114 2000 V Charged Device Model, JESD22-C101 2500 V TJ Junction Temperature +150 °C TSTG Storage Temperature -55 +150 °C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Condition Min. Max. Unit VPVIN Power Input Referenced to PGND 7 15 V VIN Modulator Input Referenced to AGND 7 15 V TJ Junction Temperature -40 +125 °C ILOAD Load Current TA=25°C, No Airflow 6 A VPVIN, VIN , VPVCC PVIN, VIN, and Gate Drive Supply Input VPVIN, VIN , VPVCC Connected for 5 V Rail Operation and Referenced to PGND, AGND 4.5 5.5 V Thermal Characteristics The thermal characteristics were evaluated on a 4-layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm). Symbol Parameter Typ. Unit ΘJA Thermal Resistance, Junction-to-Ambient 35 °C/W ψJC Thermal Characterization Parameter, Junction-to-Top of Case 2.7 °C/W ψJPCB Thermal Characterization Parameter, Junction-to-PCB 2.3 °C/W
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 6 FAN23SV04T — TinyBuck™
Electrical Characteristics
Unless otherwise noted; VIN=12 V, VOUT=0.6 V, TA=TJ=-40 to +125°C. Symbol Parameter Condition Min. Typ. Max. Unit Supply Current IVIN,SD Shutdown Current EN=0 V 16 µA IVIN,Q Quiescent Current EN=5 V, Not Switching 1.8 mA IVIN,GateCharge Gate Charge Current EN=5 V, fSW=500 kHz 10 mA Linear Regulator VREG Regulator Output Voltage 4.75 5.00 5.25 V IREG Regulator Current Limit 60 mA Reference, Feedback Comparator VFB FB Voltage Threshold 590 596 602 mV VDDQ VDDQ Pin Voltage Range 0 3 V IFB FB Pin Bias Current -100 0 100 nA Modulator tON On-Time Accuracy RFREQ=56 k, VIN=10 V, tON=250 ns, No Load -20 20 % tOFF,MIN Minimum SW Off-Time 320 374 ns DMIN Minimum Duty Cycle FB=1 V 0 % Soft-Start ISS Soft-Start Current SS=0 V 7 10 13 µA Current Limit ILIM Valley Current Limit Accuracy TA=TJ=25°C, IVALLEY=4 A -10 10 % KILIM ILIM Set-Point Scale Factor 233 ILIMTC Temperature Coefficient 4000 ppm/°C Enable VTH+ Rising Threshold 1.11 1.26 1.43 V VHYST Hysteresis 122 mV VTH- Falling Threshold 1.00 1.14 1.28 V VENCLAMP Enable Voltage Clamp IEN=20 µA 4.3 4.5 V IENCLAMP Clamp Current EN=5 V 24 µA IENLK Enable Pin Leakage EN=1.2 V 100 nA IENLK Enable Pin Leakage VEN=5 V 76 µA UVLO VON VCC Good Threshold Rising 4.4 V VHYS Hysteresis Voltage 160 mV Thermal Shutdown TOFF Thermal Shutdown Trip Point(1) 155 °C THYS Hysteresis(1) 15 °C Internal Bootstrap Diode VFBOOT Forward Voltage IF=10 mA 0.6 V IR Reverse Leakage VR=5 V 1000 µA MOSFETs RDS,ON,HS Drain to Source On Resistance(2) VGS=5 V, ID=30 A, TA=25°C 9.67 mΩ RDS,ON.LS Drain to Source On Resistance(2) VGS=5 V, ID=30 A, TA=25°C 5.46 mΩ Note: 1. Guaranteed by design; not production tested. 2. Typical RDS,ON value is provided for reference only, and is derived from discrete MOSFET data.
airflow; unless otherwise specified. Figure 6. Efficiency vs. Load Current VIN=12 V Figure 7. Efficiency vs. Load Current VIN=12 V Figure 8. Efficiency vs. Load Current with VIN=12 V Figure 9. Case Temperature Rise vs. Load Current Figure 10. Load Regulation Figure 11. Startup Waveforms Using Soft-Start with
2.4 A Resistive Load
Figure 12. Startup Waveforms Tracking VDDQ with Figure 13. Shutdown Waveforms Tracking VDDQ with Figure 14. Tracking Operation with Variable VDDQ Figure 15. Static Output Ripple with No Load Figure 16. Static Output Ripple with 4 A Load Current Figure 17. Operation as Load Changes from
0 A to 4 A
Figure 18. Operation as Load Changes from
4 A to 0 A
Figure 19. Load Transient from 0% to 50% Load Figure 20. Load Transient from 50% to 100% Load Figure 21. Over-Current Protection with Heavy Load
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 10 FAN23SV04T — TinyBuck™ The FAN23SV04T uses a constant-on-time modulation architecture with a VIN feed-forward input to accommodate a wide V IN range. This method provides fixed switching frequency (fSW) operation when the inductor operates in Continuous Conduction Mode (CCM). Additional benefits include excellent line and load transient response, cycle-by -cycle current limiting, and elimination of loop compensation requirements. At the beginning of each cyc le, FAN23SV04T turns on the high-side MOSFET (HS) for a fixed duration (tON). At the end of tON, HS turn s off for a duration (tOFF) determined by the operating conditions . Once the FB voltage (VFB) falls below the reference voltage (V REF), a new switching cycle begins. The modulator provides a minimum off-time (tOFF-MIN) of 250 ns to provide a guaranteed interval for low-side MOSFET (LS) current sensing and PFM operation. tOFF- MIN provides stability against multiple pulsing and limits maximum switching frequency during transient events. Enable The enable pin can be driven with an external logic signal, connected to a resistive divider from PVIN/Vin to ground to create an Under -Voltage Lockout (UVLO) based on the PVIN/VIN supply, or connected to PVIN/VIN through a single resistor to auto-enable while operating within the EN pin internal clamp current sink capability. The EN pin can be directly driven by logic voltages of 5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic, a small current flows into the pin when the EN pin voltage exceeds the internal clamp voltage of 4.3 V. To eliminate clamp current flowing into the EN pin use a voltage divider to limit the EN pin voltage to < 4 V. To implement the UVLO function based on PVIN/VIN voltage level, select values for R7 and R8 in Figure 1 such that the tap point reaches 1.26 V when VIN reaches the desired startup level using the following equation: 𝑅7 = 𝑅8 𝑉𝐼𝑁,𝑜𝑛 𝑉𝐸𝑁,𝑜𝑛 −1 (1) where VIN,on is the input voltage for startup and V EN,on is the EN pin rising threshold of 1. 26 V. With R8 selected as 10 kΩ, and V IN,on=9 V the value of R7 is 61.9 kΩ. The EN pin can be pulled high with a single resistor connected from VIN to the EN pin. With VIN > 5.5V a series resistor is required to limit the current flow into the EN pin clamp to less than 24 µA to keep the internal clamp within normal operating range. The resistor value can be calculated from the following equation: 𝑅𝐸𝑁 > 𝑉𝐼𝑁,𝑚𝑎𝑥 −𝑉𝐸𝑁,𝐶𝑙𝑎𝑚𝑝,𝑚𝑖𝑛 22µ𝐴 (2) Constant On-Time Modulation The FAN23SV04T uses a constant on-time modulation technique, in which the HS MOSFET is turned on for a fixed time, set by the modulator, in response to the input voltage and the frequency -setting resistor. This on-time is proportional to the desired output voltage, divided by the input voltage. With this proportionality, the frequency is essentially constant over the load range where inductor current is continuous. For a buck converter in Continuous -Conduction Mode (CCM), the switching frequency f SW is expressed as: 𝑓𝑆𝑊 = 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁 ∙𝑡𝑂𝑁 (3) The on-time generator sets the on-time (t ON) for the high-side MOSFET, which results in the switching frequency of the regulator during steady-state operation. To maintain a relati vely constant switching frequency over a wide range of input conditions, the input voltage information is fed into the on-time generator. tON is determined by: 𝑡𝑂𝑁 = 𝐶𝑡𝑂𝑁 𝐼𝑡𝑂𝑁 ∙2𝑉 (4) where ItON is: 𝐼𝑡𝑂𝑁 = 1 10 ∙ 𝑉𝐼𝑁 𝑅𝐹𝑅𝐸𝑄 (5) where RFREQ is the frequency -setting resistor described in the Setting Switching Frequency s ection; CtON is the internal 2.2 pF capacitor; and ItON is the VIN feed-forward current that generates the on-time. The FAN23SV04T implements open-circuit detection on the FREQ pin to protect the output from an infinitely long on-time. In the event the FREQ pin is left floating, switching of the regulator is disabled. The FAN23SV04T is designed for a VIN input range 7 to 15 V and fSW from 200 kHz to 1.5 MHz, resulting in an ItON ratio of 1 to 16. As the ratio of VOUT to VIN increases, tOFF,min introduces a limit on the maximum switching frequency as calculated in the following equation, where the factor 1.2 is included in the denominator to provide some headroom for transient operation: 𝑓𝑆𝑊 < 1 − 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁,𝑚𝑖𝑛 1.2 ∙𝑡𝑂𝐹𝐹,𝑚𝑖𝑛 (6) VDDQ This pin is connected to the V DDQ supply, which the FAN23SV04T must track during startup and produce an output (VTT) equal to half of VDDQ in steady -state conditions. To accomplish this, the VDDQ pin has an internal resistor divider to AGND that provides a reference voltage equal to VDDQ/2 at the positive input of the FB comparator. Soft-Start (SS) A conventional soft-start ramp is implemented to provide a controlled startup sequence of the output voltage. A current is generated on the SS pin to charge an external capacitor. The lesser of the voltage on the SS pin and the reference voltage is used for output regulation.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 11 FAN23SV04T — TinyBuck™ During normal operation, the SS voltage is clamped to 400 mV above the FB voltage. The clamp voltage drops to 40 mV during an overload condition (when V FB is ≤ 400 mV) to allow the converter to recover using the soft- start ramp once the overload condition is removed. There is no on- time modulation during normal normal soft -start or when recovering from an overload condition. The nominal startup time is programmable through an internal current source charging the ext ernal soft -start capacitor CSS: 𝐶𝑆𝑆 = 𝐼𝑆𝑆 ∙𝑡𝑆𝑆 𝑉𝑅𝐸𝐹 (7) where: CSS = External soft-start programming capacitor; ISS = Internal soft-start charging current source, 10 µA; tSS = Soft-start time; and VREF = VDDQ/2. For example; for 1ms startup time, CSS=15 nF. The soft-start option can be used for ratiometric tracking. When EN is LOW, the soft-start capacitor is discharged. Internal Linear Regulator The FAN23SV04T includes a linear regulator to facilitate single-supply operation for self -biased applications. PVCC is the linear regulator output and supplies power to the internal gate drivers. The PVCC pin should be bypassed with a 2.2 µF ceramic capacitor. The devic e can operate from a 5 V rail if the V IN, P VIN, and P VCC pins are connected together to bypass the internal linear regulator. VCC Bias Supply and UVLO The V CC rail su pplies power to the controller. It is generally connected to the PVCC rail through a low - pass filter of a 10 Ω resistor and 0.1 µF capacitor to minimize any noise sources from the driver supply. An Under -Voltage Lockout (UVLO) circuit monitors the VCC voltage to ensure proper operation. Once the V CC voltage is above the UVLO threshold, the part begin s operation after an i nitialization routine of 50 µs. There is no UVLO circuitry on either the PVCC or VIN rails. Over-Current Protection (OCP) The FAN23SV04T uses current informat ion through the LS to implement valley -current limiting. While an OC event is detected, the HS is prevented from turning on and the LS is kept on until the current falls bel ow the user-defined set point. Once the current is below the set point, the HS is allowed to turn on. The ILIM pin has an open detection circuit to provide protection against operation without a current limit. Over-Temperature Protection (OTP) FAN23SV04T incorporates an over-temperature protection circuit that disables the converter when the die temperature reaches 155°C. The IC restarts when the die temperature falls below 140°C.
Application Information
Constant on-time stability consists of two parameters: stability criterion and sufficient signal at V FB. Stability criterion is given by: 𝑅𝐸𝑆𝑅 ∙𝐶𝑂𝑈𝑇 ≫ 𝑡𝑂𝑁 2 (8) Sufficient signal requirement is given by: ∆𝐼𝐼𝑁𝐷 ∙𝑅𝐸𝑆𝑅 > ∆𝑉𝐹𝐵 (9) where ∆IIND is the inductor current ripple and ∆VFB is the ripple voltage on VFB, which should be ≥12 mV. In certain applications, especially designs utilizing only ceramic output capacitors, there may not be sufficient ripple magnitude available on the feedback pin for stable operation. In this case, an external circuit , such as R2-C4-C5 shown in Figure 1, can be added to inject ripple voltage into the FB pin. There are some specific considerations when selecting the RCC ripple injector circuit. For typical applications, the value of C4 can be selected as 0.1 µF and approximate values for R2 and C5 can be determined using the following equations. R2 must be small enough to develop 12 mV of ripple: 𝑅2 < (𝑉𝐼𝑁 −𝑉𝑂𝑈𝑇) ∙𝑉𝑂𝑈𝑇 𝑉𝐼𝑁 ∙0.012𝑉∙𝐶4 ∙𝑓𝑆𝑊 (10) R2 must also be selected such that the R2C4 time constant enables stable operation: 𝑅2 < 0.33 ∙2𝜋∙𝑓𝑆𝑊 ∙𝐿𝑂𝑈𝑇 ∙𝐶𝑂𝑈𝑇 𝐶4 (11) The minimum value of C5 can be selected to minimize the capacitive component of ripple appearing on the feedback pin: C5MIN = LOUT ∙COUT R2 ∙R3 ∙C4 (12) Using the minimum value of C5 generally offers the best transient response, and 100 pF is a good initial value in many applications. However, under some operating conditions excessive pulse jitter may be observed. To reduce jitter and improve stability, the value of C5 can be increased: 𝐶5 ≥ 2 ∙C5MIN (13)
5 V PVCC
The PV CC is the output of the internal regulator that supplies power to the drivers and VCC. It is crucial to keep this pin decoupled to PGND with a ≥ 1 µF X5R or X7R ceramic capacitor. Because V CC powers the internal analog circuit, it is filtered from PVCC with a 10 Ω resistor and 0.1 µF X7R decoupling ceramic capacitor to AGND.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 12 FAN23SV04T — TinyBuck™ Setting the Output Voltage (VOUT) The output voltage, VOUT, is regulated by initiating a high- side MOSFET on- time interval when the valley of the divided output voltage appearing at the FB pin reaches VREF. Since this method regulates at the valley of the output ripple voltage, the actual DC output voltage on VOUT is offset from the programmed output voltage by the average value of the output ripple voltage. The output VOUT setting of the regulator can be determined using the following equation: 𝑉𝑂𝑈𝑇 = 𝑉𝐷𝐷𝑄 2 (14) where VDDQ is the voltage applied to pin 31. For example; if VDDQ=1.2 V thenVOUT=600mV. VFB is trimmed to a value of 596 mV when VDDQ=VREF=600 mV. The final output voltage , including the effect of the output ripple voltage , can be approximated by: 𝑉𝑂𝑈𝑇 = 𝑉𝐹𝐵 ∗𝑉𝑟𝑖𝑝 2 (15) Setting the Switching Frequency (fSW) fSW is programmed through external RFREQ as follows: 𝑅𝐹𝑅𝐸𝑄 = 𝑉𝑂𝑈𝑇 20 ∗𝐶𝑡𝑂𝑁 ∗𝑓𝑆𝑊 (16) where CtON=2.2 pF). For example ; for fSW=500 kHz and VOUT=0.6 V, then select a standard resistor value for RFREQ=27.4 kΩ. Inductor Selection The inductor is typically selected based on the ripple current (∆IL), which is approximately 25% to 45% of the maximum DC load. The inductor current rating should be selected such that the saturation and heating current ratings exceed the intended currents encountered in the application over the expected temperature range of operation. Regulators that require fast transient response use smaller inductance and higher current ripple; while regulators that require higher efficiency keep ripple current on the low side. The inductor value is given by: 𝐿 = (𝑉𝐼𝑁 −𝑉𝑂𝑈𝑇) ∆𝐼𝐿 ∙𝑓𝑆𝑊 ∙𝑉𝑂𝑈𝑇 𝑉𝐼𝑁 (17) For example: for 12 V VIN, 0.6 V VOUT, 4 A load, 25% IL, and 500 kHz f SW; L is calculated to be 1.1 µH and a standard value of 1 µH is selected. Input Capacitor Selection Input capacitor CIN is selected based on voltage rating, RMS current I CIN(RMS) rating, and capacitance. For capacitors with DC voltage bias derating , such as ceramic capacitors, hig her rating is strongly recommended. RMS current rating is given by: 𝐼𝐶𝐼𝑁(𝑅𝑀𝑆) = 𝐼𝐿𝑂𝐴𝐷−𝑀𝐴𝑋 ∙𝐷 ∙(1 −𝐷) (18) where ILOAD-MAX is the maximum load current and D is the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs at 50% duty cycle. The capacitance is given by: 𝐶𝐼𝑁 = 𝐼𝐿𝑂𝐴𝐷−𝑀𝐴𝑋 ∙𝐷 ∙(1 −𝐷) 𝑓𝑆𝑊 ∙∆𝑉𝐼𝑁 (19) where ∆VIN is input voltage ripple, normally 1% of VIN. For example: for V IN=12 V, ∆VIN=120 mV, VOUT=0.6 V,
4 A load, and f SW=950 kHz; then CIN is calculated as
1.7 µF, select a single 10 µF, 25 V-rated ceramic capacitor with X7R or similar dielectric, recognizing that the capacitor DC bias characteristic indicates that the capacitance value falls approximately 40% at VIN=12 V. Output Capacitor Selection Output capacitor COUT is also selected based on voltage rating, RMS current I CIN (RMS) rating, and capacitance. For capacitors with DC voltage bias derating , such as ceramic capacitors, higher rating is recommended. When calculating C OUT, usually the dominant requirement is the current load step transient. If the unloading transient requirement (IOUT transitioning from HIGH to LOW ), is satisfied, the load transient (IOUT transitioning LOW to HIGH ), is also usually satisfied. The unloading C OUT calculation, assuming C OUT has negligible parasitic resistance and inductance in the circuit path, is given by: 𝐶𝑂𝑈𝑇 = 𝐿∙ 𝐼𝐿𝐸𝑉𝐸𝐿1 2 −𝐼𝐿𝐸𝑉𝐸𝐿2 (𝑉𝑂𝑈𝑇 + ∆𝑉𝑂𝑈𝑇)2 −𝑉𝑂𝑈𝑇 2 (20) where Ilevel1 and I level2 are current levels before and after load steps, and ∆VOUT is the voltage overshoot, usually specified at 5%. For example: for V I=12 V, VOUT=0.6 V, ILEVEL1=3 A, ILEVEL2=2 A, fSW=500 kHz, L OUT=1 µH, and 4.0% ∆VOUT overshoot of 24 mV; the C OUT value is calculated to be 170 µF, and four 47 µF, 6.3 V-rated X5R ceramic capacitors may be used. This equation assumes that the load current rises instantaneously : with reduced current slew rate, the value for COUT can be reduced. Setting the Current Limit Current limit is implemented by sensing the inductor valley current across the LS R DS(ON) during the LS on- time. The current -limit comparator prevents a new on- time from starting until the valley current is less than the current limit. The set point is configured by connecting a resistor fr om the ILIM pin to the SW pin. A trimmed current of approximately 20 µA is output onto the ILIM pin, which creates a volt age across the resistor. When the voltage on ILIM goes negative, an over -current condition is detected.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 13 FAN23SV04T — TinyBuck™ The current flowing out of the ILIM pin through R ILIM is trimmed to compensate for both the R DS(ON) of the LS MOSFET and the offset v oltage of the current limit comparator. RILIM is calculated by: 𝑅𝐼𝐿𝐼𝑀 = 1.02 ∗𝐾𝐼𝐿𝐼𝑀 ∗ 𝐼𝑉𝐴𝐿𝐿𝐸𝑌 (21) where KILIM is the current source scale factor equal to the average RDS,ON of the LS MOSFET divided by the average ILIM pin current of 20 µA, and I VALLEY is the inductor valley current when the current limit threshold is reached. The factor 1.01 accounts for the temperature offset of the LS MOSFET compared to control circuit (approximately 5°C), and the approximate increase in the RDS,on of the LS MOSFET of 4000 ppm/°C. With the c onstant on-time architecture, HS is always turned on for a fixed on-time . This determines the peak - to-peak inductor current. Current ripple ∆I is given by: ∆𝐼𝐿 = (𝑉𝐼𝑁 −𝑉𝑂𝑈𝑇) ∗ 𝑡𝑂𝑁 𝐿 (22) From the equation above, the worst -case ripple occurs during an output short circuit (where V OUT is 0 V). This should be taken into account when selecting the current limit set point. The FAN23SV04T uses valley -current sensing. T he current limit (IILIM) set point is the valley (IVALLEY). The valley current level for calculating RILIM is given by: 𝐼𝑉𝐴𝐿𝐿𝐸𝑌 = 𝐼𝐿𝑂𝐴𝐷 (𝐶𝐿) −∆𝐼𝐿 2 (23) where ILOAD (CL) is the DC load current when the current limit threshold is reached. For example: in a converter designed for 4 A steady- state operation and 1 A current ripple , the current -limit threshold could be selected at 1 20% of I LOAD,(SS) to accommodate transient operation and inductor value decrease under loading. As a resul t; ILOAD,(SS) is 4.8 A, IVALLEY=4.3 A, and R ILIM is selected as the standard value of1.02 kΩ. Boot Resistor In some applications, especially with higher input voltage, the VSW ring voltage may exceed the derating guidelines of 80% to 90% of absolute rating for VSW. In this situation, a resistor can be connected in series with the boot capacitor (C3 in Figure 1) to reduce the turn-on speed of the high- side MOSFET to reduce the amplitude of the VSW ring voltage. PCB (Printed Circuit Board) Layout Guidelines The following should be considered before beginning a PCB layout using the FAN23SV0 4T. A sample PCB layout from the TinyBuck™ evaluation board following the layout guidelines is shown in Figure 22 - Figure 25. Power components consisting of the input capacitors, output capacitors, inductor, and TinyBuck device should be on a common side of the PCB in close proximity to each other and connected using surface copper. Sensitive analog components ; including SS, FB, ILIM, FREQ, and EN ; should be placed away from the high- voltage switching circuits , such as SW and BOOT, and connected to their respective pins with short traces. The inner PCB layer closest to the TinyBuck device should have Power Ground (PGND) under the power - processing portion of the device (PVIN, SW, and PGND). This inner PCB layer should have a separate Analog Ground (AGND) under the P1 pad and the associated analog components. AGND and P GND should be connected together near the IC between PGND pins 18-21 and AGND pin 23, which connects to P1 thermal pad. The AGND thermal pad (P1) should be connected to AGND plane on the inner layer using four 0.25 mm vias spread under the pad. No vias are included under PVIN (P2) and SW (P3) to maintain the PGND plane under the power circuitry intact. Power circuit loops that carry high currents should be arranged to minimize the loop area. Primary focus should be directed to minimize the loop for current flow from the input capacitor to PVIN, through the internal MOSFETs, and returning to the input capacitor. The input capacitor should be placed as close to the PVIN terminals as possible. The current return path from PGND at the low -side MOSFET source to t he negative terminal of the input capacitor can be routed under the inductor and also through vias that connect the input capacitor and low - side MOSFET source to the PGND region under the power portion of the IC. The SW node trace that connects the source of the high-side MOSFET and the drain of the low -side MOSFET to the inductor should be short and wide. To control the voltage across the output capacitor, the output voltage divider should be located close to the FB pin, with the upper FB voltage divider resistor connected to the positive side of the output capacitor, and the bottom resistor should be connected to the AGND portion of the TinyBuck device. When using ceramic capacitor solutions with external ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and C4 should be connected near the inductor and coupling capacitor C5 should be placed near the FB pin to minimize FB pin trace length. Decoupling capacitors for PVCC and VCC should be located close to their respective device pins. SW node connections to BOOT, ILIM, and ripple injection resistor R2 should be through separate traces.
Figure 22. Evaluation Board Top Layer Copper Figure 23. Evaluation Board Inner Layer 1 Copper
Figure 24. Evaluation Board Inner Layer 2 Copper Figure 25. Evaluation Board Bottom Layer Copper
Figure 26. 34-Lead, PQFN, 5.5 mm x 5.0 mm warranty therein, which covers Fairchild products. B) ALL DIMENSIONS ARE IN MILLIMETERS. BURRS DOES NOT EXCEED 0.10MM.
0.10 C A B
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 17 FAN23SV04T — TinyBuck™