FAN105B ONSEMI | Alldatasheet
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© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X FAN105BM6X Offline Primary-Side-Regulation (PSR) Quasi-Resonant Valley Switch Controller FAN105B is offline Primary -Side-Regulation (PSR) PWM controller with Quasi-Resonant (QR) mode controller to achieved constant-voltage (CV) and constant-current (CC) control for Travel Adaptor (TA) requirement, and provide cost -effective, simplified circuit for energy-efficient power supplies. FAN105B integrates proprietary operation of energy saving feature at no load, mWSaver Technology that combines our most energy efficient process and circuit technologies for power adapter design. FAN105B can be used in Travel Adapter design by stand-alone or co-work with secondary-side SR controller FAN6292B. When paired FAN105B with FAN6292B, both SR and USB Type -C connector are compatible to achieve higher power and advanced control applications.
Features
mWSaver® Technology Provides Ultra-Low Standby Power Consumption for Energy Star’s 5-Star Level (<30 mW with HV FET) Constant-Current (CC) and Constant-Voltage(CV) with Primary-Side Regulation Eliminates Secondary-Side Feedback Component Valley Switch Operation for Highest Average Efficiency Programmable Cable Drop Compensation(CDC) with One External Resistor Integrated Dynamic Response Enhanceement(DRE) Function Low EMI Emissions and Common Mode Noise Cycle-by-Cycle Current Limiting Output Short-Circuit Protection Scondary side Rectifier Short Detection via Current Sense Protection(CSP) Integrated Constant Current Compensation for Precise CC Regulation Output Over-Voltage Protection (VSOVP) Output under-Voltage Protection (VSUVP) VDD Over-Voltage Protection (VDD OVP) Internal Thermal-Shutdown Protection (OTP) Programmable Brown-In and Brown-Out Protection Typical Applications Travel Adapter for Smart Phones, Feature Phones, and Tablet PCs AC-DC Adapters for Portable Devices that Require CV/CC Control www.onsemi.com MARKING DIAGRAM PXXEX- - -- PIN CONNECTIONS CS GND GATE AUX VS VDD
ORDERING INFORMATION
FAN105BM6X -40 º C ~125º C 6-Lead, SOT23 Tap & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D .
- · · = Year Code PXX = 5A0 : FAN105BM6X = 5B0 : FAN105BM6X E X = Die Run Code - - - = Week Code
© Semiconductor Components Industries, LLC, 2017 3 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X PIN FUNCTION DESCRIPTION Pin # Name Description 1 CS Current Sense. This pin connects to a current-sense resistor to detect the MOSFET current for Peak-Current-Mode control for output regulation. The current-sense information is also used to estimate the output current for CC regulation.
2 GND Ground
3 GATE PWM Signal Output. This pin has an internal totem-pole output driver to drive the power MOSFET. The gate driving voltage is internally clamped at 7.5 V. 4 VDD Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically connected to an external VDD capacitor. 5 VS Voltage Sense. This pin detects the output voltage information and diode current discharge time based on the voltage of auxiliary winding. It also senses sink current through the auxiliary winding to detect input voltage information.
6 AUX
Auxiliary Function. This pin generates one voltage level proportional to output current to compensate output voltage drop due to cable resistance. The pin is also used for startup with external HV FET.
© Semiconductor Components Industries, LLC, 2017 4 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X ABSOLUTE MAXIMUM RATINGS (Note 1,2,3,4) Parameter Symbol Min. Max. Unit DC Supply Voltage VVDD -0.3 30 V AUX Pin Input Voltage VAUX -0.3 30 V VS Pin Input Voltage VVS -0.3 6.0 V CS Pin Input Voltage VCS -0.3 6.0 V Power Dissipation (TA=25C) PD 0.391 mW Operating Junction Temperature TJ -40 +150 C Storage Temperature Range TSTG -60 +150 C Lead Temperature (Soldering, 10 Seconds) TL +260 C Electrostatic Discharge Capability Human Body Model, ANSI/ESDA/JEDEC, JESD22_A114 ESD >1.5 kV Charged Device Model, JEDEC:JESD22_C101 >0.5 1. Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. 2. All voltage values, except differential voltages, are given with respect to the GND pin. 3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 4. Meets JEDEC standards JS-001-2012 and JESD 22-C101. THERMAL CHARACTERISTICS (Note 5) Parameter Symbol Min. Max. Unit Junction-to-Ambient Thermal Impedance θJA 242 °C/W Junction-to-Top Thermal Impedance θJT 56 °C/W 5. TA=25°C unless otherwise specified. RECOMMENDED OPERATING RANGES (Note 6) Parameter Symbol Min. Max. Unit CS Pin Input Voltage VCS 0 0.8 V Gate Pin Input Voltage VGATE 0 8.0 V VDD Pin Input Voltage VDD 7.0 25 V VS Pin Input Voltage VVS 1.6 3.2 V AUX Pin Input Voltage VAUX 5.0 25 V 6. The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance. On Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings.
© Semiconductor Components Industries, LLC, 2017 5 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X Continues on next page…
ELECTRICAL CHARACTERISTICS
VDD=12 V and TA=-40~85C unless noted Parameter Test Conditions Symbol Min Typ Max Unit VDD Section Turn-On Threshold Voltage VDD-ON 16.5 17.5 18.5 V Turn-Off Threshold Voltage VDD-OFF 6.1 6.5 6.9 V VDD Over-Voltage-Protection Level VDD-OVP 26.5 28.0 29.5 V VDD Over-Voltage-Protection De- bounce Time tD-VDD-OVP - 120 200 µs Startup Current(8) IDD-ST - 20 µA Operating Current IDD-OP 1 1.4 1.7 mA Deep Green-Mode Operating Current IDD-DPGN 375 450 525 µA Oscillator Section Maximum Voltage-Mode Quasi- Resonant Blanking Frequency fOSC-BNK-MAX 70 76 82 kHz Minimum Current-Mode Time-Out Blankig Frequency fOSC-BNK-MIN 4.5 5.0 5.5 kHz Deep Green Mode Operating Frequency(8) fOSC-DPGN 320 420 480 Hz Minimum CCM Prevention Frequency(7) fOSC-CCM-PRVENT 18 21 24 kHz Over-Temperature Protection Section Over-Temperature Protection Threshold(7) TOTP-H 120 C Over-Temperature Protection Recovery Threshold(7) TOTP-L 100 C
© Semiconductor Components Industries, LLC, 2017 6 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X Continues on next page… VDD=12 V and TA=-40~85C unless noted Parameter Test Conditions Symbol Min Typ Max Unit Voltage Sampling Section Reference Voltage of Constant Voltage Feedback VVR 2.475 2.500 2.525 V VS Sampling Phase-Shift Resistance(7) RVS-S/H 300 kΩ VS Sampling Phase-Shift Capacitance(7) CVS-S/H 5 pF VS Sampling Blanking Time of High Level Io over 100mA tVS_BNK-H 1.65 1.80 2.00 µs VS Sampling Blanking Time at CC Controlling tVS_BNK-CC 2.05 2.20 2.35 µs VS Discharging Time Judgment Threshold Voltage(7) VVS-Offset 150 200 250 mV Voltage Sense Section Temperature-Independent Bias Current ITC 9.0 10.0 11.0 μA VS Pin Source Current Threshold to Enable Brown-Out IVS-BROWN-OUT 260 310 360 μA Brown-Out De-bounce Time tD-BROWN-OUT 12 17 22 ms VS Pin Source Current Threshold to Enable Brown-In IVS-BROWN-IN 405 475 545 μA Brown-In De-bounce Time NBROWN-IN 3 4 5 cycle Output Over-Voltage-Protection of VS Sampling threshold VVS-OVP 2.70 2.80 2.90 V Output Over-Voltage-Protection Debounce Cycle Counts NVS-OVP 3 4 5 Cycle Output Low Level Under-Voltage- Protection of VS Sampling threshold VVS-UVP 1.50 1.60 1.70 V Output Under-Voltage Protection Debounce Time tVS-UVP 30 40 50 ms No-Load Control Section Deep Green Mode Entry Threshold Voltage of COMV(7) VCOMV-CV-DPGN- ENTRY 0.4 0.5 0.6 V Criteria to Enter Deep Green Mode VVS_EAV_Hi 2.550 2.600 2.650 V Deep Green Mode Band-Band Control High Threshold Voltage VVS-EAV-H 2.550 V Deep Green Mode Band-Band Control Low Threshold Voltage VVS-EAV-L 2.525 V Criteria to Exit Deep Green Mode VVS_EAV_Lo 2.425 2.450 2.475 V Dynamic Event Trigger Threshold Voltage in Deep Green Mode VVS-EAV-DYN 2.375 2.400 2.425 V Minimum On-time at 264VAC CGATE=1nF tON-MIN-264VAC 450 500 550 ns Minimum On-time at 230VAC CGATE=1nF tON-MIN-230VAC 500 550 600 ns Minimum On-time at 115VAC CGATE=1nF tON-MIN-115VAC 1250 1350 1450 ns Minimum On-time at 90VAC CGATE=1nF tON-MIN-90VAC 1500 1650 1800 ns
© Semiconductor Components Industries, LLC, 2017 7 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X Notes: 7. Guaranteed by Design. 8. TA guaranteed range at 25C VDD=12 V and TA=-40~85C unless noted. Parameter Test Conditions Symbol Min Typ Max Unit Current Feedback Section Reference Voltage of Constant Current Feedback VCCR 1.19 1.2 1.21 V VCS Peak Value Amplifying Gain(7) APK 3.9 V/V Attenuator ratio of Constant Current Feedback Loop(7) AV-CC 1/3.5 V/V Current Sense Section Current Limit Threshold Voltage VCS-LIM 0.70 0.75 0.80 V GATE Output Turn-Off Delay(7) tPD 100 ns Leading-Edge Blanking Time(7) tLEB 150 200 250 ns GATE Section Maximum On-Time tON-MAX 15 17 20 μs Gate Output Voltage Low VGATE-L 0 1.5 V Internal Gate PMOS Driver ON VDD-PMOS-ON 7.0 7.5 8.0 V Internal Gate PMOS Driver OFF VDD-PMOS-OFF 9.0 9.5 10.0 V Gate Output Clamping Voltage VDD level higher than 9V VGATE-CLAMP 7.0 7.5 8.0 V AUX Section Dynamic Response Enhancement (DRE) function trigger threshold current at AUX IDRE-DET 110 140 170 μA CDC compensation voltage at internal reference RCDC is 330kΩ VVS-CDC4 0.298 0.320 0.343 V RCDC is 560kΩ VVS-CDC3 0.223 0.240 0.257 V RCDC is 920kΩ VVS-CDC2 0.149 0.160 0.171 V RCDC is 1.3MΩ VVS-CDC1 0.074 0.080 0.086 V
© Semiconductor Components Industries, LLC, 2017 14 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X VVS regulated boundary are between VVS-EAV-H and VVS-EAV- L. After exit DPGN, internal regulation reference voltage was changed to VVR. FAN105B DPGN entry and exit criteria showed as below: DPGN entry need to meet both criteria as below: Minimum frequency (f OSC-MIN) operation continues over than NDPGN-Entry switching cycles. EAV > VVS-EAV-H(2.550V). DPGN exit criteria, meet one of below criteria: EAV < V VS-EAV-L (2.525V) and maximum on time at DPGN. EAV < VVS-EAV-DYN(2.4V). During the DPGN mode controlling, FAN105B decreases the operating current down to 450µA. Therefore, the standby power could meet international standard requirement when work with flexible start up circuit, designer have flexible start up circuit that HV FET or start up resistor depending on cost and better standby power consideration Cable Drop Compensation (CDC) FAN105B integrates cable drop compensation function and the compensation weighting is calculated based on tDIS, current sense voltage (VCS), and CDC setting resistor (RCDC) needed to between VDD and AUX pin . During start up, as VDD reached VDD-ON, CDC programming block detects AUX pin current and determine cable drop compensation weighting based on current weighting of AUX pin. Once finished CDC compensation weighting detecting, the information will stored until shunt-down by protections or VDD lower than V DD-OFF. The CDC weighting automatic detected input current during start up . which provides a constant output voltage at the end of the cable over the entire load range in CV Mode. The table show s the compensation weighting with corresponding R CDC setting as below: TA designer can easily to set up CDC weighting via choose RCDC following above table. In the table, resisance of R CDC is recommended for corresponding compensation level. Cable drop compensation voltage at output is proportional to V VS compensation weighting that is internal referce voltage for CDC compensation. Programmable Brown In/ Brown Out FAN105B implement Brown out and Brown I n through high side resistor setting at VS PIN . In actual system operation , VS PIN is drain a current (I VS) that proportional to line voltage during MOSFET turns on. IVS could predict by below equation: (5) Operating Current The operating current in FAN105B is as small as 1.4mA. The small operating current results in higher efficiency and reduces the VDD hold-up capacitance re quirement. During DPGN mode, the FAN105B consumption current is reduced to 450µA, assisting the power supply meet standby power standard requirements. Protections The FAN105B self-protection includes VDD Over-Voltage- Protection (V DD OVP), Internal Chip Over-Temperature- Protection (OTP), VS Over-Voltage Protection (VSOVP), VS Under-Voltage Protection (VS UVP), CS pin Protection(CSP), Brownout and Brown In protection, and all of protection are implemented as Auto Restart(AR) mode. When When an Auto-Restart Mode protection is triggered , switching is terminated and the MOSFET remains off, causing V DD to drop till V DD-OFF and shut -down the system then all protections are reset. After then VDD will be charged again by the input AC voltage and once touch V DD-ON then switching resumes. This is the reason why it is called Auto - Restart, resumes switching automatically. VDD Over-Voltage-Protection(VDD OVP) When V DD is raised up to higher level by some reasons, transformer VDD winding turns are too many, load regulation is not good between transformer winding, VS information is not available anyhow and so on, and touches VDD-OVP, then FAN105B stops switching and prot ects IC from higher V DD voltage. This is different then output voltage is over than pre determined level. VS Under-Voltage Protection (VSUVP) FAN105B bulid-in VSUVP function that prevent TA keep deliver power to phone side when output voltage is under the set voltage at VS pin. VSUVP has a 40ms de-bounce time and once VDD touches V DD-ON, during the later 40ms VSUVP is disabled because VSUVP should not be triggered during the start up. VSUVP level can be calculated as below: (6) VS Over-Voltage Protection (VSOVP) The VSOVP is design ed to prevent TA output voltage is over then the rating of used components, like capacitor . VSOVP has 4 s witching cycles of denounce time and that prevent mis-triggered of VSOVP by switching noise. The protection level is changed in proportional to the CDC CDC Weighting and RCDC Setting RCDC Label VVS Compensation weighting 1.3MΩ VVS-CDC1 0.08V 920kΩ VVS-CDC2 0.16V 560kΩ VVS-CDC3 0.24V 330kΩ VVS-CDC4 0.32V
© Semiconductor Components Industries, LLC, 2017 16 Publication Order Number: May 2017- Rev. 1.0 FAN105BM6X VGATE (FAN105B) IAUX tAUX-ON IO VBUS VIN-AUX IDRE-DET tOPTO-DELAY Heavy Load Figure 30.DRE function Detecting Sequency Accurately Constant Current (CC) Compensation FAN105B provides accurate constant current with universal line voltage range, In order to achieve this accurately output current regulated, FAN105B build in circuits that compensate a DC level at CS signal based on difference line voltage . It could avoid output current gap of difference line voltage during constand current controlling . For noise immunity, the recommendation of CS pin series resistor is 10Ω.
NOTES: A. THIS PACKAGE CONFORMS TO JEDEC MO-178, VARIATION AB. B. ALL DIMENSIONS ARE IN MILLIMETERS. C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. D. DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. E. DIMENSIONS AND TOLERANCING AS PER ASME Y14.5M-1994 F. DRAWING FILE NAME: MA06EREV2 1.30 0.90 0.15 0.05 SEATING PLANE
0.60 REF
0.60 0.30 FORMERLY: SCALE: 2:1 DETAIL A APPROVALS
5 JULY 07
SHEET :N/A OF1 1 1.6MM WIDE MO-178 VARIATION AB, 6LD,SOT23,JEDEC SEE DETAIL A GAGE PLANE 0.25
1.45 MAX
0.08 0.22 LAND PATTERN RECOMMENDATION RELEASE TO DOCUMENT CONTROL
DESCRIPTION
A CL REVISIONS E.C.N. DATE BY/APP'D C C0.10 1:1 NA/
0.15 C A-B
0.15 C 2X 3 TIPS 2.9 1.6 1.9 A 2.8 1.4
0.15 C D
0.95 B 2X 0.3-0.5
0.20 C A-B D
D PIN 1 INDEX AREA (0.95) (0.95) (1.00MIN) (1.90) (2.60) (0.70MIN) R0.10MIN R0.10MIN C D DC 11/4/2006 H.ALLEN 2 DWG UPDATED TO CONFORM TO MO178 5 JULY 07 L.HUEBENER L.HUEBENER H.ALLEN 17 JULY 07
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