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Technical content

Features

 Single-Pin Direct-Drive of ERM for Simple Vibration Control  External Motor Enable/Disable, Vibration Control  Register-Based I2C Control (Optional; Device Operates in Default Condition)  Over-Driving Motor Control, Drive ERM Voltage to VDD Rail  Programmable Motor Drive Voltage  Low Standby Current: <1 µA  Fast Wake-up Time  Nearly Rail-to-Rail Output Swing  Protections: Under-Voltage, Over-Current, Over-Temperature  Package: 10-Lead MLP

Applications

 Mobile Phones  Handheld Devices  Keypad Interfaces

Description

The FAH 4820 is a high-performance enhanced ERM driver for mobile phone and other hand-held devices. This device does not require a PWM signal to generate vibration of the ERM; it is controlled by the drive level on the HEN input. The ERM spins for the length of time that the HEN pin is held HIGH , then stop猀 when the HEN pin is pulled LOW . The FAH4820 ’s register maps are accessible via I2C serial communication, which is useful for higher or lower drive voltage across the ERM or if disabling the device is desired. Related Resources  AN-5067 — PCB Land Pattern Design and Surface- Mount Guidelines for MLP Packages

Ordering Information

Temperature Range Package Packing Method FAH4820MPX -40°C to +85°C 10-Lead, Dual, JEDEC MO-229, 3 mm Square, Molded Leadless Package (MLP)

3000 Units on

Tape & Reel

© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAH4820 • 1.0.0 3 FAH4820 — Driver for DC Motors (ERMs) Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage -0.3 6.0 V VIO Analog and Digital I/O (All Input and Output Pins) -0.3 VCC+0.3 V Reliability Information Symbol Parameter Min. Typ. Max. Unit TJ Junction Temperature +150 °C TSTG Storage Temperature Range -65 +150 °C JA Thermal Resistance, JEDEC Standard, Multi-Layer Test Boards, Still Air 200 °C/W Electrostatic Discharge Information Symbol Parameter Max. Unit ESD Human Body Model, JESD22-A114 ±4 kV Charged Device Model, JESD22-C101 ±1 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit TA Operating Temperature Range -40 +85 °C VDD Supply Voltage Range 2.7 3.3 5.5 V

TA = 25°C, VDD = 3.3 V, and VLDO = 3.0 V unless otherwise noted. Figure 3. Enable/Disable Functional Timing

TA = 25°C, VDD = 3.3 V, and VLDO = 3.0 V unless otherwise noted.

  1. A Fast-Mode I2C Bus® device can be used in a Standard-Mode I2C bus system, but the requirement tSU;DAT

specification) before the SCL line is released.

  1. Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are

allowed according to the I2C specification. Figure 4. Definition of Timing for Full-Speed Mode Devices on the I2C Bus

which is the clock signal for all other devices on the bus. All other devices on the bus are called “slave” devices. slave devices can send and receive data on the bus. or not acknowledge (NACK) from the receiving device. stream of data and ACKs/NACKs during data transfers. device cannot issue a START or STOP condition. line transitions from HIGH to LOW while SCL is HIGH. data transfer is about to begin. line transitions from LOW to HIGH while SCL is HIGH. acknowledge (ACK) after receiving every byte of dat a. leaving SDA HIGH during the clock after the last byte. is 0000110 X binary , where “X” is the read/write bit. Master write operations are indicated when X = 0. Master read operations are indicated when X = 1. bit by pulling the SDA line LOW for one clock cycle.

  1. This indicates that the master writes new information

sends an ACK after receiving the new pointer data. Figure 8. Any time a pointer-set is performed, it must be operations always require the pointer be reset. by responding with a NACK, followed by a STOP. must again send the device address and read/write bit. described for reading from a preset pointer location. pointer is already pointing to the desired register.

Table 1. Control Registers and Default Values Table 2. Control Register MAP (Control0, Control1, Status)

  1. Connect the bottom DAP to ground.

Table 3. Control 0

7 En 1

6 ODRV_EN 1

5 ODRVEN_HL 1

4 Reserved 1 Not used

Table 4. Control 1 Table 5. Status

3 VDD_G 1

2 VLDO_OUT_G 1

1 OT 1 0: Over-temperature protection is tripped

0 Reserved 1 Not used, default is 0

Table 6. VDD vs. VLDO_OUT

Figure 9. 555 Timer Control of Single Vibration from ERM

© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAH4820 • 1.0.0 12 FAH4820 — Driver for DC Motors (ERMs) digitalWrite(VIBpin,HIGH); delay(600); digitalWrite(VIBpin,LOW); delay(300); digitalWrite(VIBpin,HIGH); delay(300); digitalWrite(VIBpin,LOW); delay(300); digitalWrite(VIBpin,HIGH); delay(150); digitalWrite(VIBpin,LOW); delay(300); else digitalWrite(VIBpin,LOW); if (digitalRead(switchPin1) == HIGH) /* run this sequence if pin 9 is high - double pulse*/ digitalWrite(VIBpin,HIGH); delay(600); digitalWrite(VIBpin,LOW); delay(300); digitalWrite(VIBpin,HIGH); delay(150); digitalWrite(VIBpin,LOW); delay(300); else digitalWrite(VIBpin,LOW); if (digitalRead(switchPin2) == HIGH) /* run this sequence if pin 10 is high - single pulse*/ digitalWrite(VIBpin,HIGH); delay(600); digitalWrite(VIBpin,LOW); delay(300); else digitalWrite(VIBpin,LOW); Internal LDO The internal LDO is designed for an I 2C seven -step adjustable output voltage. This provides flexibility for various motor voltages and configurations for low-power consumption. The LDO includes an internal circuit for short-circuit current protection. Serial Interface On power -up, the device default values are invoked . The FAH4820 allows programming through the registers: the VLDO out , over drive , power down , and others functions . The device function s without any I 2C input signals connected. Thermal Shutdown If the junction tempera ture is above 1 50°C, the temperature control block shuts down and stays o ff until the temperature is below 134°C. The register values are kept as written so that it’s not required to initialize again. Over-Current Limitation The driver includes a current-limitation block to protect against an over-current condition, mainly caused by a stuck-rotor condition. Over-current protection limitation is 500 mA, typical. Over-Drive Motor Control A common approach to driving DC motors is to over - drive a voltage that overcomes the inertia of the motor ’s mass. The motor is often overdriven for a short time before returning to the rated voltage to sustain rotation. The FAN 4820 block can over -drive a motor up to the VDD voltage. Over-Drive Duration It is important that over-drive time not damage the motor. The over -drive duration must be dependent on the motor datasheet and care must be taken not to assert an over-voltage condition over the rated time limit of the motor. Status Registers The FAH4820 has a status register set that monitors LDO input voltage, regulator output voltage , and over - temperature status.

Figure 11. 10-Lead, JEDEC MO-229, 3 mm Square, Molded Leadless Package (MLP) warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/. B. DIMENSIONS ARE IN MILLIMETERS.

0.10 C A B

0.8 MAX

© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAH4820 • 1.0.0 14 FAH4820 — Driver for DC Motors (ERMs)