FAD8253 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Floating Channel for Bootstrap Operation to +1200 V
  • Peak Output Current Capability of 2.5 A Source/3.4 A Sink
  • Allowable Negative VS Transient Swing of up to −15 V at VBS =1 5V
  • Built−in Common Mode dv/dt Noise Canceling Circuit
  • Separate Power and Signal Ground for Enhanced dl/dt Immunity
  • Matched Propagation Delay < 50 ns
  • 3.3 V and 5 V Input Logic Compatible
  • Built in Shoot−through Prevention Logic with 120 ns (Typ) Dead Time
  • Built−in UVLO Functions for both High and Low Side with Thresholds Optimized for IGBTs
  • Built−in Low Side Short−circuit Protection with Soft Shutdown
  • In SOIC14NB with Non Connected Pins for High V oltage Creepage and Clearance Requirements
  • Fault Reporting during Overcurrent or Short−circuit Condition
  • External Shutdown Pin to Enable or Disable Driver Outputs
  • AEC−Q100 Qualified and PPAP Capable
  • Pb−Free Devices Typical Applications
  • High V oltage Auxiliary Motor Drive
  • Generic Half−Bridge and Full−Bridge Driver
  • On−Board Chargers & DC/DC Converters
  • Traction Inverters www.onsemi.com MARKING DIAGRAM SOIC−14 NB CASE 751A FAD8253MX AWLYWW FAD8253MX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week ON Pin 1 Bar or Pin 1 Dot PIN ASSIGNMENT Device Package Shipping †

ORDERING INFORMATION

FAD8253MX SOIC −14 NB (Pb−Free) 2,500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 11 4 21 3 31 2 41 1 51 0 VB HO VS NC NC LO COM VSS LIN SD HIN FO CSC VDD

8 COM

Figure 3. Block Diagram

1 VSS Logic Ground

2 LIN Logic Input for Low−Side Gate Driver Output

3 SD Shutdown Control Input with Active Low

4 HIN Logic Input for High−Side Gate Driver Output

5 FO Fault Output with Open Drain (Low True)

6 CSC Short−Circuit Current Detection Input

7 VDD Low−Side and Logic Power Supply Voltage

8 COM Low−side Driver Return

9 LO Low−Side Driver Output

12 VS High−Side Floating Supply Return

13 HO High−Side Driver Output

14 VB High−Side Floating Supply

www.onsemi.com SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified.) Symbol Rating Value Unit VS High−side Offset Voltage VS (VB − 25) to (VB + 0.3) V VB High−side Floating Supply Voltage VB −0.3 to 1225 V VHO High−side Floating Output Voltage (VS – 0.3) to (VB + 0.3) V VDD Low−side and Logic−fixed Supply Voltage −0.3 to 25 V VIN Logic Input Voltage (HIN, LIN, SD) −0.3 to (VDD + 0.3) V VCSC Current Sense Input Voltage −0.3 to (VDD + 0.3) V dVS/dt Allowable Offset Voltage Slew Rate 50 V/ns PD Power Dissipation (SO14NB) (Note 1) 0.8 W θJA Thermal Resistance, Junction−to−Ambient (SO14NB) 156 °C/W TJ(max) Junction Temperature +150 °C TSTG Storage Temperature −55 to +150 °C ESDHBM ESD, Human Body Model (Note 3) 2500 V ESDCDM ESD, Charged Device Model (Note 3) 750 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Do not exceed PD under any circumstances. − JESD51−2: Integral circuits thermal test method environmental conditions – natural convection − JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages 3. This device series incorporates ESD protection and is tested by the following methods: − ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012 − ESD Charged Device Model tested per JESD22−C101 RECOMMENDED OPERATING RANGES (Parameters are referenced to VSS) Symbol Rating Min Max Unit VDD Supply Voltage Range 4.5 18.0 V VS High−Side VS Floating Supply Offset Voltage (Note 4) 5 − VBS 1200 V VBS High−side VBS Bootstrap Voltage VBSUV+ 22 V VHO High−Side Output Voltage VS VB V VDD Low−Side and Logic Supply Voltage VDDUV+ 22 V VLO Low−Side Output Voltage COM VDD V VIN Logic Input Voltage (IN, SD) VSS VDD V COM Power Ground VDD − 22 VDD V TA Ambient Temperature (Note 5) −40 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Recommended based on min 5 V on VB, for proper operation of the level shifter circuit and ensure proper propagation of the signal from the input to the output. 5. Power and thermal impedance should be determined with care so that T j does not exceed 150°C.

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ELECTRICAL CHARACTERISTICS

(VBIAS (VDD, VBS) = 15 V, TA = −40°C to 125°C unless otherwise specified. The VIN and IIN parameters are referenced to VSS. The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO.) Symbol Parameter Test Conditions Min Typ Max Unit LOW SIDE POWER SUPPLY SECTION IQDD Quiescent VDD Supply Current VLIN = 0 V or 5 V 50 280 400 /C0109A IPDD Operating VDD Supply Current CL = 1 nF, fLIN = 20 kHz, rms value 400 660 800 /C0109A VDDUV+ VDD Supply Under−Voltage Positive−going Threshold VDD = Rising 11 12 12.9 V VDDUV− VDD Supply Under−voltage Negative going Threshold VDD = Falling 10.5 11.4 12.4 V VDDHYS VDD Supply Under−voltage Lockout Hysteresis − 0.6 − V BOOSTRAPPED POWER SUPPLY SECTION IQBS Quiescent VBS Supply Current VHIN = 0 V or 5 V − 25 45 /C0109A IPBS Operating VBS Supply Current CL = 1 nF, fHIN = 20 kHz, rms value − 430 550 /C0109A ILK Offset Supply Leakage Current VB = VS = 1200 V − − 120 /C0109A VBSUV+ VBS Supply Under−Voltage Positive−going Threshold VBS = Rising 10.6 11.7 12.5 V VBSUV− VBS Supply Under−voltage Negative Going Threshold VBS = Falling 10.1 11.1 11.9 V VBSHYS VBS Supply Under−voltage Lockout Hysteresis − 0.6 − V GATE DRIVER OUTPUT SECTION VOH High−level Output Voltage, VBIAS−VO IO = 0 mA (No Load) − − 50 mV VOL Low−level Output Voltage, VO IO = 0 mA (No Load) − − 50 mV IO+ Output HIGH Short−circuit Pulsed Current VO =0V , VIN = 5 V with PW < 10 /C0109s 1200 2700 − mA IO− Output LOW Short−circuit Pulsed Current VO =1 5V , VIN = 0 V with PW < 10 /C0109s 1200 4200 − mA VS Allowable Negative VS Pin Voltage, with Signal Propagation Capability from HIN to HO VBS =1 5V −10.0 − − V VS (Note 6) Allowable Transient Negative VS Pin Voltage, No Signal Propagation Capability from HIN to HO VBS =1 5V −15.0 − − V COM−VSS Allowable COM−VSS Power/Signal Grounds Offset VDD =1 5V , VSS =0V −7.0 − − V LOGIC INPUT SECTION (HIN, LIN, SD) VIH Logic “1” Input Voltage Threshold − − 2.5 V VIL Logic “0” Input Voltage Threshold 1.2 − − V VINHYS Logic Input Hysteresis Voltage − 0.5 − V IIN+ Logic “1” Input Bias Current (HIN, LIN) VIN =5V − 23 − /C0109A IIN− Logic “0” Input Bias Current (HIN, LIN) VIN =0V − − 2.0 /C0109A ISD+ Logic “1” Input Bias Current (SD) VSD =5V − 15.7 − /C0109A ISD− Logic “0” Input Bias Current (SD) VSD =0V − − 2.0 /C0109A SHORT−CIRCUIT PROTECTION VCSCREF Short−circuit detector reference voltage 0.45 0.50 0.6 V RCSCIN Input Pull Down Short Circuit Resistance − 210 − k/C0087 ICSCIN Short−Circuit Input Current VCSCIN =5V 15 23.5 37.5 /C0109A ISOFT Soft Turn−off Source Current VDD =1 5V , LO = 7.5 V 70 110 140 mA

www.onsemi.com ELECTRICAL CHARACTERISTICS (continued) (VBIAS (VDD, VBS) = 15 V, TA = −40°C to 125°C unless otherwise specified. The VIN and IIN parameters are referenced to VSS. The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO.) Symbol UnitMaxTypMinTest ConditionsParameter FAULT DETECTION SECTION VFOH Fault Output High Level Voltage VCSC =0V , RPULL−UP = 4.7 k/C00874.7 − − V VFOL Fault Output Low Level Voltage VCSC =1V , IFO =2m A − − 0.8 V DYNAMIC OUTPUT SECTION (VBIAS (VDD, VBS) = 15.0 V, TA = −40°C to 125°C, VS = VSS, CLOAD = 1000 pF unless otherwise specified.) ton Turn−on Propagation Delay (Note 7) VS =0V 65 100 145 ns toff Turn−off Propagation Delay VS = 0 V or 1200 V 65 90 145 ns tSDOFF_LO SD to Low−side Propagation Delay 25 45 70 ns tSDOFF_HO SD to How−side Propagation Delay 65 95 145 ns tr Turn−on Rise Time − 13 25 ns tf Turn−off Fall Time − 15 26 ns MtON Delay Matching HO and LO Turn−On − − 25 ns MtOFF Delay Matching HO and LO Turn−Off − − 25 ns DT Dead−time (Note 8) 70 120 200 ns tUVFLT Under−voltage Filtering Time (Note 6) − 10 − /C0109s tCSCFLT CSC Pin Filtering Time (Note 6) − 300 − ns tCSCFO Time from CSC Triggering to FO − 530 1250 ns tFO Fault Output Pulse Width 24 65 140 /C0109s tCSCLO Time from CSC Triggering to Low−side and High−side Gate Output From VCSC = 1 V to starting gate turn−off − 600 1350 ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Parameter guaranteed by design. 7. The turn −on propagation delay does not includes the dead time. 8. The dead time includes the turn on propagation time.

Figure 22. SD Logic High Input Bias Current vs. Figure 23. Input Pull Down Short Circuit Figure 24. Fault Output High Level Voltage vs. Figure 25. Fault Output Low Level Voltage vs. Figure 26. Allowable Negative VS Voltage vs. Figure 27. High−level Output Voltage vs.

310 Min Typ Max

SOIC−14 NB CASE 751A−03 ISSUE L DATE 03 FEB 2016SCALE 1:1 GENERIC MARKING DIAGRAM* XXXXXXXXXG AWLYWW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb −Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. STYLES ON PAGE 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. H 14 8 M0.25 B M C h X 45 SEATING PLANE A M /C0095 SAM0.25 B SC b13X B A E D e DETAIL A L DETAIL A DIM MIN MAX MIN MAX INCHESMILLIMETERS D 8.55 8.75 0.337 0.344 E 3.80 4.00 0.150 0.157 A 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 L 0.40 1.25 0.016 0.049 e 1.27 BSC 0.050 BSC A3 0.19 0.25 0.008 0.010 A1 0.10 0.25 0.004 0.010 M 0 7 0 7 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 6.50 14X 0.58 14X 1.18 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0.10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ASB42565BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2SOIC−14 NB © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE STYLE 2: CANCELLED ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ASB42565BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2SOIC−14 NB © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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