FAD7171MX ONSEMI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 11

Technical content

Features

  • Floating Channel for Bootstrap Operation to +600 V
  • 4 A Sourcing and 4 A Sinking Current Driving Capability
  • Common−Mode dv/dt Noise−Cancelling Circuit
  • 3.3 V and 5 V Input Logic Compatible
  • Output In−phase with Input Signal
  • Under−Voltage Lockout for VBS
  • 8−SOIC Package, Case 751−07 (JEDEC MS−012, 0.150 inch Narrow Body)
  • AEC−Q100 Qualified and PPAP Capable for Ambient Operating Temperature from −40°C to 125°C

Applications

  • Common Rail Injection Systems
  • DC−DC Converter
  • Motor Drive (Electric Power Steering, Fans) Related Product Resources
  • FAN7171 Product Folder
  • FAD7171 Product Folder
  • AND9674 Design and Application Guide of Bootstrap Circuit for High−Voltage Gate−Drive IC
  • AN−8102 Recommendations to Avoid Short Pulse Width Issues in HVIC Gate Driver Applications
  • AN−9052 Design Guide for Selection of Bootstrap Components FAD7171MX SOIC8 (Pb−Free / Halogen Free) 2500 / Tape & Reel MARKING DIAGRAM Device Package Shipping †

ORDERING INFORMATION

†For information on tape and reel specifications , including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. These devices passed wa ve soldering test by JESD22A−111. SOIC−8 NB CASE 751−07 FAD7171MX ALYW FAD717MX = Device A = Assembly Site L = Wafer Lot Number YW = Assembly Start Week

www.onsemi.com PIN DESCRIPTION Pin No. Symbol Description

1 VDD Supply Voltage

2 IN Logic Input for High−Side Gate Driver Output

3 NC No Connection

4 GND Ground

5 NC No Connection

6 VS High−Voltage Floating Supply Return

7 HO High−Side Driver Output

8 VB High−Side Floating Supply

Symbol Characteristics Min Max Unit VS High−Side Floating Offset Voltage VB − 25 VB + 0.3 V VB High−Side Floating Supply Voltage −0.3 625.0 V VHO High−Side Floating Output Voltage VS − 0.3 VB + 0.3 V VDD Low−Side and Logic Supply Voltage −0.3 25 V VIN Logic Input Voltage −0.3 VDD + 0.3 V dVS/dt Allowable Offset Voltage Slew Rate − ±50 V/ns PD Power Dissipation (Notes 2, 3, 4) − 0.625 W /C0113JA Thermal Resistance − 200 °C/W TJ Junction Temperature −55 150 °C TSTG Storage Temperature −55 150 °C TA Operating Ambient Temperature −40 125 °C ESD Human Body Model (HBM) − 2000 V Charge Device Model (CDM) − 500 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Refer to the following standards: JESD51−2: Integral circuits thermal test method environmental conditions, natural convection, and JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages. 4. Do not exceed power dissipation (P D) under any circumstances. RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit VBS High−Side Floating Supply Voltage 10 20 V VS High−Side Floating Supply Offset Voltage (DC) @ VBS = 15 V −11 600 V VHO High−Side Output Voltage VS VB V VIN Logic Input Voltage GND VDD V VDD Supply Voltage 10 20 V TPULSE Minimum Input Pulse Width 80 − ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

www.onsemi.com ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS) = 15 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND. The VO and IO parameters are relative to VS and are applicable to the respective output HO) Symbol Parameter Conditions Min Typ Max Unit POWER SUPPLY SECTION IQDD Quiescent VDD Supply Current VIN = 0 V or 5 V − 85 200 /C0109A IPDD Operating VDD Supply Current CLOAD = 1 nF, fIN = 20 kHz − 105 170 /C0109A BOOTSTRAPPED SUPPLY SECTION VBSUV+ VBS Supply Under−Voltage Positive−Going Threshold Voltage VBS = Sweep 8.4 9.4 10.1 V VBSUV− VBS Supply Under−Voltage Negative−Going Threshold Voltage VBS = Sweep 7.7 8.7 9.3 V VBSHYS VBS Supply UVLO Hysteresis Voltage VBS = Sweep − 0.7 − V ILK Offset Supply Leakage Current VB = VS = 600 V − − 50 /C0109A IQBS Quiescent VBS Supply Current VIN = 0 V or 5 V − 43 95 /C0109A IPBS Operating VBS Supply Current CLOAD = 1 nF, fIN = 20 kHz − 620 1200 /C0109A INPUT LOGIC SECTION (IN) VIH Logic “1” Input Voltage 1.8 − − V VIL Logic “0” Input Voltage − 0.8 V VINHYS Logic Input Hysteresis Voltage − 0.5 − V IIN+ Logic Input High Bias Current VIN = 5 V − 45 100 /C0109A IIN− Logic Input Low Bias Current VIN = 0 V − − 2 /C0109A RIN Input Pull−down Resistance 30 105 − k/C0087 GATE DRIVER OUTPUT SECTION (HO) VOH High Level Output Voltage (VBIAS − VO) No Load − − 35 mV VOL Low Level Output Voltage No Load − − 35 mV IO+ Output High, Short−Circuit Pulsed Current (Note 5) VHO = 0 V, VIN = 5 V, PW ≤ 10 /C0109s 2.5 4.0 − A IO− Output Low, Short−Circuit Pulsed Current (Note 5) VHO = 15 V, VIN = 0 V, PW ≤ 10 /C0109s 2.5 4.0 − A VS Allowable Negative VS Pin Voltage for IN Signal Propagation to HO − − 11 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. These parameters guaranteed by design. DYNAMIC ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS) = 15 V, VS = GND = 0 V, CL =1000 pF, and −40°C ≤ TA ≤ 125°C, unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit tON Turn−On Propagation Delay VS = 0 V − 48 100 ns tOFF Turn−Off Propagation Delay VS = 0 V − 46 95 ns tR Turn−On Rise Time − 11 18 ns tF Turn−Off Fall Time − 12 19 ns

SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751 −01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) SCALE 1:1 STYLES ON PAGE 2 DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package GENERIC MARKING DIAGRAM* XXXXX ALYWX IC Discrete XXXXXX AYWW /C0071 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the onsemi Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* Discrete XXXXXX AYWW (Pb−Free) XXXXX ALYWX /C0071 IC (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week /C0071 = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “/C0071”, may or may not be present. Some products may not follow the Generic Marking. MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 98ASB42564BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2SOIC−8 NB onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N −SOURCE 2. N −GATE 3. P −SOURCE 4. P −GATE 5. P −DRAIN 6. P −DRAIN 7. N −DRAIN 8. N −DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 98ASB42564BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2SOIC−8 NB onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ADDITIONAL INFORMATION TECHNICAL PUBLICATIONS: Technical Library: www.onsemi.com/design/resources/technical−documentation onsemi Website: www.onsemi.com ONLINE SUPPORT: www.onsemi.com/support For additional information, please contact your local Sales Representative at www.onsemi.com/support/sales