FAD3151MXA ONSEMI | Alldatasheet
Document overview
- Manufacturer or author: onsemi
- PDF pages: 15
Technical content
Features
Single Channel Gate Driver with 110 V floating Vs capability Negative Transient Capability up to −80 V 2.5 A Output Source and Sink Current MOSFET Drain−Source Desaturation Detection with Soft Shutdown Integrated Charge Pump to support 100% Duty Cycle Operation (FAD3171MXA only) Under−voltage Lock Out for both Input Logic and Output Stage Bi−directional Fault Reporting Pin High Speed Driver with Short Propagation Delay dVs/dt Immune to min 50 V/ns 3.3 V and 5 V Input Logic Compatible Up to VDD Swing on Input Pins SOIC−8 package Automotive Qualified to AEC Q100 These Devices are Pb−Free and are RoHS Compliant Support integration into customer’s safety application with a set of safety documents including FMEDA and a hardware −software interface document. SAFETY SUPPORT SOIC−8 CASE 751EB Device Package Shipping †
ORDERING INFORMATION
FAD3151MXA SOIC −8 (Pb−Free) Tape & Reel FAD3171MXA SOIC −8 (Pb−Free) Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Typical Applications Gate Driver for 80V and 100V MOSFETs 48 V Belt Starter Generator 48 V Auxiliary Motor Control (A/C com- pressor, e−turbo, ) 48 V Battery Switches 48 V DC−DC converter PTC Heater, Active Discharge Circuit etc. This document, and the information contained herein, is CONFIDENTIAL AND PROPRIETARY and the property of Semiconductor Components Industries, LLC., dba onsemi. It shall not be used, published, disclosed or disseminated outside of the Company, in whole or in part, without the written permission of onsemi. Reverse engineering of any or all of the information contained herein is strictly prohibited. /C0069 2022, SCILLC. All Rights Reserved.
Figure 3. Pin Connection
1 VDD Power supply for logic stage
2 IN Input command
3 FLT Bi−directional fault pin
4 COM Ground for logic stage
5 VS Floating source connection
6 Desat Drain to source desaturation detection pin
7 HO Output
8 VB Floating power supply for power stage
FAD3151MXA, FAD3171MXA CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com MAXIMUM RATINGS TA = −40C ~ 125C unless otherwise noted. Voltage potentials are referenced to COM unless otherwise noted. Rating Symbol Value Unit Logic Power Supply VDD −0.3 to 20 V Logic Input Voltage (IN, FLT) VIN −0.3 to (VDD + 0.3) V Floating Source Voltage VS −115 to 115 V Floating Bootstrap Supply Voltage VB (VS – 0.3) to (VS + 20) V Output Voltage VHO (Vs – 0.3) to (VB + 0.3) V Desaturation Voltage VDESAT (Vs – 0.3) to (VB + 0.3) V Allowable Offset Voltage Slew Rate dVs/dt +/−50 V/ns Maximum Junction Temperature TJ 150 C Thermal Resistance, Junction−to−Ambient (Note 1) RthJA 200 C/W Power Dissipation at TA= 25C PD 0.625 W Storage Temperature Range TSTG −55 to 150 C ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV ESD Capability, Charged Device Model (Note 2) ESDCDM 500 for all pins V 750 for corner pins Moisture Sensitivity Level MSL 3 − Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) TSLD 260 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to the following standards: JESD51−2: Integral circuits thermal test method environmental conditions – natural convection JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012 ESD Charged Device Model tested per JESD22−C101 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D RECOMMENDED OPERATING RANGES TA = −40C ~ 125C unless otherwise noted. Voltage potentials are referenced to COM unless otherwise noted. Rating Symbol Min Max Unit Power Supply VDD VDDUV+ 18 V Logic Input Voltage (IN, FLT) VIN 0 18 V High−Side Vs Floating Supply Offset Voltage VS −80 110 V High−side VBS Bootstrap Voltage VBS VBSUV+ 18 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.
FAD3151MXA, FAD3171MXA CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com
ELECTRICAL CHARACTERISTICS
VBIAS (VDD, VBS) = 15 V, VS = 0 V unless otherwise noted, TA = −40C to 125C. Voltage potentials are referenced to COM unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit POWER SUPPLY SECTION VBS Under−Voltage Positive−going Threshold VBSUV+ 6 8 10.5 V VBS Under−Voltage Negative−going Threshold VBSUV− 5.5 7.5 9.7 VBS Slew Rate During Startup (Note 4) VBS(SR) 2.5 V/ms VDD Under−Voltage Positive−going Threshold VDDUV+ 6 V VDD Under−Voltage Negative−going Threshold VDDUV− 2.2 3.9 Offset Supply Leakage Current VB = VS = 80 V ILK1 5 /C0109A Quiescent VDD Supply Current VIN = 0 V or 5 V IQDD 270 500 /C0109A Quiescent VBS Supply Current VIN = 0 V or 5 V IQBS 525 1000 Operating VDD Supply Current VIN = 0 V or 5 V; fSW = 20 kHz; CL = 1 nF IPDD 250 600 Operating VBS Supply Current VIN = 0 V or 5 V; fSW = 20 kHz; CL = 1 nF IPBS 1000 2000 4. This limitation applies only to temperatures exceeding 105 C. LOGIC INPUT SECTION Logic “1” Input threshold for IN, FLT VIH 2.1 2.5 V Logic “0” Input threshold for IN, FLT VIL 1.3 1.7 Logic Input High Bias Current VIN = 5 V IIN+ 48 70 /C0109A Logic Input Low Bias Current VIN = 0 V IIN− 2 /C0109A Input Pull−down Resistance RIN 80 k/C0087 FAULT SECTION Fault Output Internally pulled down voltage level 10 k/C0087 pull up resistor to VDD, VDESAT > VDESAT+ VFLT+ 200 mV Fault Output Not Internally pulled down voltage level 10 k/C0087 pull up resistor to VDD, VDESAT < VDESAT+ VFLT− 13.8 V Fault Pin Pull−down Resistance RFLT 110 k/C0087 Desaturation High detection threshold (Note 5) VDESAT,TH 2.3 3.0 4 V Desaturation Bias Current IDESAT 180 320 430 /C0109A 5. The actual desaturation threshold at the Power MOSFET can be adjusted to a value lower than VDESAT,TH with an external resistor (see Application Note) GATE DRIVER OUTPUT SECTION High−Level Output Voltage (VB − VHO) VIN = 5 V, No Load VHOH 50 mV Low−Level Output Voltage (VHO−VS) VIN = 0 V, No Load VHOL 50 mV Source Peak Pulsed Current (Note 6) VIN = 5 V, VHO = 0 V, Pulse Width 10 /C0109s IO+ 2.5 A Sink Peak Pulsed Current (Note 6) VHO = VBS= 15 V, Pulse Width 10 /C0109s IO− 2.5 Allowable Negative VS pin voltage, with signal Prop- agation Capability from IN to HO VS −80 V Driver Output Pull−up Resistance IOUT = 90 mA (DC) ROH 3 /C0087 Driver Output Pull−down Resistance IOUT = 90 mA (DC) ROL 1.2 /C0087 6. Guaranteed by design
FAD3151MXA, FAD3171MXA CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com VBIAS (VDD, VBS) = 15 V, VS = 0 V unless otherwise noted, TA = −40C to 125C. Voltage potentials are referenced to COM unless otherwise noted. Parameter UnitMaxTypMinSymbolTest Conditions CHARGE PUMP SECTION [FAD3171MXA only] Turn on threshold level, referenced to VBS VDD > VDDUV+, RL = 100 k/C0087, VS = 48 V CPON 7.9 10.8 15.2 V Turn off threshold level, referenced to VBS CPOFF 8.3 11.2 15 V Charge Pump VBS hysteresis CPHYS 0.4 V Delta (CPON − VBSUV−) (Note 7) VDD > VDDUV+, RL=100 k/C0087, VS = 48 V /C0068CP,VBSUV− 1 V Charge Pump Supply Voltage VS,CP 24 V Charge Pump Output Current capability (Note 8) VBS = CPON, VS > VS,CP ICP,OUT 150 /C0109A Charge Pump Oscillation Frequency (Note 6) CPfs 5.5 MHz 7. Difference between the charge −pump turn on threshold and VBS under−voltage negative−going threshold. 8. Net output current, excluding the internal current consumption of the gate driver in steady state. DYNAMIC SECTION Input pulse filtering time (Note 9) TIN_FILT 40 ns Turn−On Propagation Delay VS = 0 V, CL = 1000 pF tON 50 100 ns Turn−Off Propagation Delay VS = 0 V, CL = 1000 pF tOFF 50 100 ns Turn−On Rise Time Vs = 0 V, CL = 1000 pF tR 15 25 ns Turn−Off Fall Time tF 10 20 ns VDD and VBS Under−Voltage filtering time (Note 6) VDD < VDDUV− or VBS< VBSUV− to VHO falls by 10% tVDDUV tVBSUV 10 /C0109s External FLT Pulse Width (Note 10) VFLT < VIL to VHO falls by 10% tFLT_Pulse 3 /C0109s Desat detection to HO propagation delay VDESAT > VDESAT+ to VHO falls by 10% with RL= 0 /C0087 and CL = 1 nF TDESAT_HO 75 110 ns Desat detection to FLT propagation delay VDESAT > VDESAT,TH to VFLT < VFLT− TDESAT_FLT 80 110 ns FLT Locking Duration Desaturation or UVLO detected tFLT_LO 150 550 /C0109s Soft shutdown resistance RSOFT 170 /C0087 9. Shorter input pulses are filtered out and do not cause the output to change state. 10.The pulse width of the external fault signal at which the driver output turns off.
gate capacitance to discharge slowly [see Figure 19]. duration (typ. 550 /C0109s). shutdown and turn off the output again. Figure 19. Desaturation Protection and Soft Shutdown the external FLT pulse width (min. 3 /C0109s), the driver turns off. to the Application Note for more details.
FAD3151MXA, FAD3171MXA CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com PACKAGE DIMENSIONS SOIC8 CASE 751EB ISSUE A DATE 24 AUG 2017
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