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Technical content
Features
Single Supply: 2.8V – 5.25V Pop and Click Suppression Differential or Single-Ended Audio Inputs Rejects TDMA Noise from GSM Handsets Filterless Fully Differential Class-D Speaker Amplifier Programmable Edge-Rate Control and Spread Spectrum Minimize EMI 1.2W into 8Ω at 4.2V, THD+N < 10% 970mW into 8Ω at 4.2V, THD+N < 1% 90% Efficiency Automatic Gain Control Limits Distortion and Protects Speakers at All Battery Voltages Noise Gate Improves Audio Quality Headphone Amplifier Power-Saving Class-G Operation Audio Taper I 2C Volume Control Capacitor-Free Outputs Integrated Regulated Charge Pump SGND Pin Eliminates Ground-Loop Noise Noise Gate Improves Audio Quality DPST Analog Bypass Switch I2C Control Low-Power Shutdown Mode Current Limit and Thermal Protection 25-Bump, 0.4mm Pitch WLCSP Package
Description
The FAB2200 combines a capacitor-free stereo headphone amplifier with a monolithic class-D speaker amplifier. An integrated charge pump generates multiple supply rails for a ground-centered class-G headphone output. The charge pump is regulated for high Power Supply Rejection Ratio (PSRR). The filterless class-D amplifier can be connected directly to a speaker without external filters. The programmable Automatic Gain Control (AGC) limits maximum speaker out put levels to protect speakers without introducing distortion. It can also dynamically limit clipping as the battery voltage falls. The noise gate can automatically mute the speaker or headphone amplifiers to reduce noise when input signals are low.
Applications
Cellular Handsets Notebook Computers Tablet PCs
Ordering Information
Part Number Operating Temperature Range Package Packing Method FAB2200UCX -40 to +85°C 25-Bump, 0.4mm Pitch, Wafer-Level Chip-Scale Package (WLCSP)
3000 Units on
Tape & Reel
Figure 1. Typical Application Circuit
Figure 2. Top-View (Bump-Side Down)
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 4 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The Absolute Maximum Ratings are stress ratings only. All voltages are referenced to GND. Symbol Parameter Min. Max. Unit VBATT Voltage on VBATT Pin -0.3 6.0 V VIN Voltage on IN1, IN2, IN3, IN4, HPL, HPR Pins CPV SS-0.3 CPV DD+0.3 V VSGND Voltage on SGND Pin -0.3 0.3 V VS Voltage on SDA, SCL, SDB Pins -0.3 V BATT+0.3 V VSP Voltage on SPKRP, SPKRN Pins -0.3 V BATT+0.3 V VBYP Voltage on BYPIN1, BYPIN2, BYPO UT1, BYPOUT2 Pins -0.3 V BATT+0.3 V Duration of SPKRP, SPKRN Short Circuit to GND or VBATT Continuous Duration of Short Circuit Between SPKRP and SPKRN Continuous Duration of HPL, HPR Short Circuit to GND Continuous Reliability Information Symbol Parameter Min. Typ. Max. Unit TJ Junction Temperature +150 °C TSTG Storage Temperature Range -65 +150 °C TL Peak Reflow Temperature +300 °C θJA Thermal Resistance, JEDEC Standard, Multilayer Test Boards, Still Air 60 °C/W TSD Thermal Shutdown Threshold +150 °C THYS Thermal Shutdown Hysteresis +35 °C ESD Protection Symbol Parameter Condition Min. Unit HBM Human Body Model (HBM) JESD22-A114-B Level 2, EC61340-3-1: 2002 Level 2, ESD-STM5.1-2001 Level 2, MIL-STD-883E 3015.7 Level 2 3 kV CDM Charged Device Model (CDM) JESD22-C101-C Level III, IEC61340-3-3 Level C4, ESD-STM5.3.1-1999 Level C4 2 kV Notes: 1. Device-use-level ESD tests are conducted at the connector pins. 2. External ESD suppressor ASIP protects the amplifie r outputs. Suppressor is between amplifier and connector; 15Ω serial resistance + 5nF capacitor and Zener diodes (14V breakdown voltage) connected to the ground. In addition, there is a ferrite bead in series between the suppressor and the connector. 3. The air discharge test can be ignored if the contact discharge test range is increased to the same voltages as air discharge (contact discharge is more stable and repeatable test than air discharge).
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 5 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Recommended Operating Conditions The Recommended Operatin g Conditions table de fines the conditions for act ual device operatio n. Recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit TA Operating Temperature Range -40 +85 °C VBATT Supply Voltage Range 2.80 5.25 V
Electrical Characteristics
Unless otherwise noted: HPA uses stereo single-ended inputs, SPA uses differential input, unused inputs AC are grounded, fIN = 1KHz, AGC off, PGAINxx = 0dB, HPxVOL = 0dB , PRESENTGAIN = 6dB, ERC = 1, SSMT = 000, SHDNB = 1, SDB = 1.8V, SDA and SCL pull-up voltage = 1.8V, Z SPK = 8Ω+68µH, RHP = 32Ω, speaker amplifier and headphone amplifier on. Typical values are at VBATT = 3.7V, TA = 25°C. Minimum and maximum values are at VBATT = 2.8V to 5.25V, TA = -40°C to 85°C. Symbol Parameter Conditions Min. Typ. Max. Unit IDD Quiescent Supply Current (ZSPK = Open) Headphone Amplifiers Enabled, Speaker Amplifier Disabled, DIFFIN43=1 3.5 mA Headphone Amplifiers Disabled, Speaker Amplifier Enabled, DIFFIN21=1 4.7 Headphone and Speaker Amplifiers Enabled 6.2 ISD Shutdown Current SHDNB = 0, SDB = 1.8V 2.2 µA SHDNB = 1, SDB = GND 2.2 tON Turn-On Time Time from Shutdown to Full Speaker and Headphone Operation, ZCD and Ramps Disabled 1.25 ms RIN Input Resistance PGAINxx = 0dB 21.0 KΩ PGAINxx = 12dB 8.5 Maximum Input Signal Swing (VBATT = 2.8V to 5.25V, Single-Ended Input) PGAINxx = 0dB 2.300 Vpk-pk PGAINxx = 12dB 0.575 Analog Bypass Switch RON On Resistance IBYPOUTx = 20mA, BYPx = 0V and VBATT, BYPEN = 1 TA = 25°C 1 Ω THD Total Harmonic Distortion VDIF = 2VPP, VCM= VBATT/2, f = 1kHz, BYPEN = 1, Load = 8 Series Resistance is 10Ω per Switch 0.05 0.25 No Series Resistors 0.10 IOFF Off Isolation BYPEN = 0, 10KHz 1VRMS Sine Wave Applied Across BYPOUT1 and BYPOUT2, BYPIN1 and BYPIN2 to GND = 50Ω 94 dB Continued on the following page…
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 6 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Electrical Characteristics (Continued) Unless otherwise noted: HPA uses stereo single-ended inputs, SPA uses differential input, unused inputs AC are grounded, fIN = 1KHz, AGC off, PGAINxx = 0dB, HPxVOL = 0dB , PRESENTGAIN = 6dB, ERC = 1, SSMT = 000, SHDNB = 1, SDB = 1.8V, SDA and SCL pull-up voltage = 1.8V, Z SPK = 8Ω+68µH, RHP = 32Ω, speaker amplifier and headphone amplifier on. Typical values are at V BATT = 3.7V, TA = 25°C. Minimum and maximum values are at V BATT = 2.80V to 5.25V, TA = -40°C to 85°C. Symbol Parameter Conditions Min. Typ. Max. Unit Speaker Amplifier VOS Output Offset Voltage PRESENTGAIN = Mute ±0.5 mV PRESENTGAIN = 6dB ±2.5 KCP Click-and-Pop Level Peak Voltage, A-Weighted,
32 Samples per Second,
PRESENTGAIN = Mute, Inputs AC Grounded Into Shutdown -70 dBV Out of Shutdown -70 PSRR Power-Supply Rejection Ratio Inputs AC Grounded VBATT = 2.8V to 5.25V 74 dB f = 217Hz, 100mVPP Ripple 77 f = 1kHz, 100mVPP Ripple 75 POUT Output Power THD+N < 1%, ERC Disabled, SSMT = 100, VBATT = 4.2V 970 mW THD+N < 10%, ERC Disabled, SSMT = 100, VBATT = 4.2V 1200 THD+N < 10%, ERC Disabled, SSMT = 100, VBATT = 3.7V 930 THD+N < 10%, ERC Enabled, SSMT = 000, VBATT = 3.7V 945 THD+N < 1%, ERC Enabled, SSMT = 000 VBATT = 4.2V 930 975 VBATT = 3.7V 750 THD+N Total Harmonic Distortion Plus Noise POUT = 350mW 0.030 0.075 % SNR Signal-to-Noise Ratio A-Weighted, POUT = 720mW, Headphone Amplifiers Off DIFFINxx = 0 (Single-Ended) 97 dB DIFFINxx = 1 (Differential) 90 97 A-Weighted, POUT = 720mW, Headphone Amplifiers On DIFFINxx = 0 (Single-Ended) 97 DIFFINxx = 1 (Differential) 97 Vn Output Noise A-Weighted, Headphone Amps Off, DIFFINxx = 0, Inputs AC Grounded 32 µV RMS Output Frequency Spread Spectrum, SSMT = 000 330 KHz Fixed Frequency, SSMT = 100 330 IOUT Output Current Limit 1.3 A Efficiency P OUT = 720mW, f = 1kHz 90 % Mute Attenuation 100 dB Continued on the following page…
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 7 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Electrical Characteristics (Continued) Unless otherwise noted: HPA uses stereo single-ended inputs, SPA uses differential input, unused inputs AC are grounded, fIN = 1KHz, AGC off, PGAINxx = 0dB, HPxVOL = 0dB , PRESENTGAIN = 6dB, ERC = 1, SSMT = 000, SHDNB = 1, SDB = 1.8V, SDA and SCL pull-up voltage = 1.8V, Z SPK = 8Ω+68µH, RHP = 32Ω, speaker amplifier and headphone amplifier on. Typical values are at VBATT = 3.7V, TA = 25°C. Minimum and maximum values are at VBATT = 2.80V to 5.25V, TA = -40°C to 85°C. Symbol Parameter Conditions Min. Typ. Max. Unit Headphone Amplifiers IVBATT Supply Current IN1 and IN2 On, IN3 and IN4 Off, DIFFIN43=1, Speaker Amplifier Off POUT = 2x50µW into 32Ω 4.4 mA POUT = 2x250µW into 32Ω 5.8 POUT = 2x500µW into 32Ω 6.8 VOS Output Offset Voltage HPxV OL = Mute ±0.15 mV KCP Click-and-Pop Level Peak Voltage, A-Weighted, HPxVOL = Mute, Inputs AC Grounded Into Shutdown -70 dBV Out of Shutdown -70 PSRR Power-Supply Rejection Ratio Inputs AC Grounded VBATT = 2.8V to 5.25V 95 dB f = 217Hz, VRIPPLE = 200mVPP f = 1KHz, VRIPPLE = 200mVPP 95 POUT Output Power THD+N < 1% RHP = 16 39 mW RHP = 32 HPxVOL = 4dB 27 31 THD+N < 10% RHP = 32 HPxVOL = 6dB 41 THD+N Total Harmonic Distortion Plus Noise RHP = 32, POUT = 20mW 0.010 0.075 % RHP = 16, POUT = 10mW 0.020 SNR Signal-to-Noise Ratio A-Weighted, POUT = 32mW, Speaker Amplifier Off HPxVOL = 4dB DIFFINxx = 0 (Single-Ended) 95 100 dB DIFFINxx = 1 (Differential) 100 A-Weighted, POUT = 32mW, Speaker Amplifier On HPxVOL = 4dB DIFFINxx = 0 (Single-Ended) 100 DIFFINxx = 1 (Differential) 103 Output Noise A-Weighted, Speaker Amplifier Off, DIFFINxx = 0 6.5 µV RMS CL Capacitive Drive 100 pF XTALK Crosstalk HPL to HPR, HPR to HPL, P O = 15mW -85 dB fP Charge-Pump Frequency 1.3 MHz AV Headphone Gain Accuracy Across All Gain Stages ±0.4 dB Channel-to-Channel Gain Tracking HPL to HPR, HPxVOL = 0dB ±0.3 % Channel-to-Channel Gain Tracking HPL to HPR Across Entire Pre-Amplifier and Volume Range ±1 % Mute Attenuation 100 dB
Unless otherwise noted, VBATT = 2.80V to 5.25V and TA = -40°C to 85°C. Unless otherwise noted, VBATT = 2.80V to 5.25V and TA = -40°C to 85°C.
- A fast-mode I 2C-Bus® device can be used in a standard-mode system, but the requirement tSU;DAT ≥250ns must
- C b equals the total capacitance of one bus line in pf. If mixed with high-speed mode devices, faster fall times are
allowed according to the I2C specification. Figure 3. Definition of Timing for Full-Speed Mode Devices on the I 2C-Bus®
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 12 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Functional Description Shutdown Mode When SHDNB bit is set to 0 or the SDB pin is grounded, the FAB2200 enters low-power Shutdown Mode. While SHDNB=0 and SDB is HIGH, I 2C communication is available. I 2C values are preserved. Values are not reset on exiting Shutdown Mode. If the SDB pin is grounded, I 2C communication is unavailable. I 2C values are not preserved. Values are reset to default values after SDB goes HIGH. Inputs During Shutdown To achieve low supply current during shutdown, all inputs must be at DC levels (except the BYPASS pins). Audio inputs must be AC grounded. V BATT must be within recommended operating conditions. I2C pins must be grounded or pulled HIGH with no toggling. If AC is presented to the inputs during shutdown, standby current may increase slightly, but there are no other negative effects. Thermal Shutdown If the junction temperature of the device exceeds the thermal shutdown threshold (see Electrical Characteristics table), the device protects itself by shutting down. The device remains shut down until the junction temperature falls below the thermal shutdown hysteresis. The I2C port remains functional and the OVRTEMP bit is set to O. This bit remains set until it is read. If the device is still in thermal shutdown when the bit is read, it remains set to 1. Otherwise, the bit is cleared to 0. Over-Current Shutdown If the output current limit of either amplifier is exceeded (see the Electrical Characteristics table ), the amplifier in question shuts down for approximately one second. After one second, the amplifier is re-enabled. If the amplifier output current ex ceeds the limit again, the cycle repeats. During current-limit shutdown, the I 2C port remains functional. If the cu rrent-limit shutdown was caused by the speaker amplifier, the OVRCURSP bit is set to 1. This bit remains set until it is read. If the speaker amplifier is still in current-limit shutdown when the bit is read, it remains set to 1. Otherwise, the bit is cleared to 0. Signal Path The input channels have a pr e-amplifier stage that can be set from 0dB to 21dB of gain. The headphone amplifiers have separate volu me controls that range from -53dB to 6dB. The speaker amplifier has a volume control that ranges from -25dB to 6dB. In addition, the speaker amplifier has a fixed gain of 6dB. A variety of combinations of these signals can be routed to the headphone amplifiers or the speaker amplifier (see Table 1 ). For example, to connect the left headphone amplifier channel to IN3 and IN1, set the SELHPL3 and SELHPL1 bi ts to 1. SELHPL4 and SELHPL2 should be set to 0. The DIFFIN43 and DIFFIN21 bi ts configure the inputs as differential pairs. When conf igured as differential, the even-numbered selection bit should be 1 and the odd- numbered selection bit should be 0. For example, if channels 4 and 3 are a differential pair that should be connected to the speaker amplifier, DIFFIN43 and SELSPA4 should be set to 1. SELSPA3, SELSPA2, and SELSPA1 should be set to 0. Amplifier channels that hav e no inputs selected should be muted (HPxVOL = 00000 or STARTGAIN = 000000). If an amplifier channel has no input selection bits set to 1, the amplifier c hannel is turned off. When the speaker amplifier is turned off, the SPKRP and SPKRN outputs stop switching. Unused audio input pins must be AC grounded. An integrated Dual-Pole Single-Throw (DPST) analog bypass switch can be used to route system audio signals. For example, baseband audio can be routed to the speaker by connecting the BYPOUTx pins to the SPKRx pins. Baseband audio outputs would then be connected to the BYPINx pins through optional external resistors if the baseband device expects a higher impedance than the existing speaker. Gain for the headphone amplifier signal path is defined by PGAINxx + HPxVOL. Gain for the speaker amplifier signal path is defined by PGAINxx + PRESENTGAIN + 6dB. Internal signal amplitude should not exceed 2.3V PP. Extra caution should be taken when mixing signals. For example, if IN1 is mixed with IN3, the maximum peak to peak amplitude of IN1 plus the maximum peak to peak amplitude of IN3 should not exceed 2.3VPP.
Table 1. Input Channel Selection
resulting in longer battery run time. output DC blocking capacitors. Table 2. Headphone Amplifier Output Table 3. Headphone Volume Change Behavior 0 0 Volume changes immediately. zero crossing does not occur within HPRAMPSPEED, volume is forced to the new setting. 1 0 Volume is ramped to the new setting at a rate of HPRAMPSPEED per step. Table 4. Headphone Volume Change Timing
are returned to the former HPxVOL values. (SELHPxx=0) so the noise gate ignores the HIZ channel. detection and ramp settings. zero crossing detection and ramp settings. Table 5. Headphone Noise Gate Threshold
000 Headphone Noise Gate Disabled
Table 7. Headphone Noise Gate Timing
111 Reserved
and HPNGZRR are valid as shown in Table 8. Table 8. Valid Headphone Amplifier Ramp /
1 X 1 0
The class-D amplifier achieves greater than 90% efficiency. times are limited to 20ns per transition at all power levels. amplitude and reduce clipping as supply voltage varies. distortion and protecting the speaker element. the threshold again or the starting gain is reached. SELSPAn bits to 0 or clearing SHDNB to 0.
Table 9. THMAX Threshold the AGC reduces gain (see Table 10). Table 10. THVBATT Threshold THMAX are both set to 0, the AGC is disabled. Figure 21. AGC Threshold, THMAX = 0111,
maximum gain when the AGC is active. Starting gai n is controlled by the STARTGAIN register ( see Table 11). Table 11. Speaker Gain Values
be too high and gain should be stepped down by 1dB. Attack speed is not exceeded. Table 12. AGC Attack Speed Table 13. AGC Release Speed
Figure 22. AGC Flow Chart
the speaker amplifier, the SPNGTRIP bit is set to 1. Table 14. Speaker Noise Gate Threshold Voltage
000 Speaker Noise Gate Disabled
Table 15. Speaker Noise Gate Timing
Table 16. Speaker Gain Change Behavior 0 0 STARTGAIN changes immediately. crossing does not occur within SPRAMPSPEED, STARTGAIN is forced to the new setting. 1 0 STARTGAIN is ramped to the new setti ng at a rate of SPRAMPSPEED per step. Table 17. Speaker Gain Change Timing with a slow SPRAMPSPEED and a fast AGCATTACK. The user changes STARTGAIN from 111111 to 000001. not listed may produce unpredictable results. Table 18. Valid Speaker Amplifier Ramp / Zero Crossing / Noise Gate Combinations detection and ramp settings.
devices can send and receive data on the bus. or not acknowledge (NACK) from the receiving device. stream of data and ACKs/NACKs during data transfers. slave device cannot issue a START or STOP condition. line transitions from HIGH to LOW while SCL is HIGH. data transfer is about to begin. line transitions from LOW to HIGH while SCL is HIGH. leaving SDA HIGH during the clock after the last byte. operations are indicated when X=1. SDA line LOW for one clock cycle. new information into the Command register. sends an ACK after receiving the new pointer data. Figure 26. Any time a pointer set is performed, it must be immediately followed by a read or write operation. operations always require the pointer be reset. by responding with a NACK, followed by a STOP. must again send the device address and read/write bit.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 24 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Register Map The I2C slave address is 1001101x, where x=0 for write operations and x=1 for read operations. Address B7 B6 B5 B4 B3 B2 B1 B0 0x00 VERSION HPNGTRIP SPNGTRIP OVRTEMP OVRCURSP 0 0x01 HIZL HIZR 0 BYPEN 0 0 0 SHDNB 0x02 DIFFIN43 DIFFIN 21 PGAIN43 PGAIN21 0x03 SELSPA4 SELSPA3 SELSPA2 SELSPA1 HPRAMPSPEED HPZCD HPRAMP 0x04 SELHPL4 SELHPL3 SELHPL2 SELHPL1 SEL HPR4 SELHPR3 SELHPR2 SELHPR1 0x05 0 0 HPLVOL 0 0x06 0 0 HPRVOL 0 0x07 HPNGZR A HPNGTHRESH HPNGZRR HPNGTIME 0x08 ERC 0 0 0 SPRAMPSPEED SPZCD SPRAMP 0x09 SPNGZRA SPNGTHRESH SPNGZRR SPNGTIME 0x0A THMAX THVBATT 0x0B 0 AGCATTACK 0 AGCRELEASE 0x0C 0 0 AGCMIN 0x0D 0 0 PRESENTGAIN 0x0E 0 0 STARTGAIN 0x0F 0 0 MCSSMT SSMT Bits labeled “0” have no effect if written. When read, the value is always 0. Bits and addresses not listed in the register map are for testing only. These bits should never be written. When read, they may return any value.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 25 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Register Descriptions Address B7 B6 B5 B4 B3 B2 B1 B0 0x00 VERSION HPNGTRIP SPNGTRIP OVRTEMP OVRCURSP 0 default 010 0 0 0 0 0 VERSION (Read only) Indicates the silicon revision number. HPNGTRIP (Read only) 1 = Headphone amplifiers are being muted by the noise gate. 0 = Normal operation. SPNGTRIP (Read only) 1 = Speaker amplifier is being muted by the noise gate. 0 = Normal operation. OVRTEMP (Read/Clear) 1 = The junction temperature of the device has exceeded the thermal shutdown threshold. (This bit remains set until it is read.) 0 = Normal operation. OVRCURSP (Read/Clear) 1 = The output current limit of the speaker amplifier has been exceeded. (This bit remains set until it is read.) 0 = Normal operation. Address B7 B6 B5 B4 B3 B2 B1 B0 0x01 HIZL HIZR 0 BYPEN 0 0 0 SHDNB default 0 0 0 0 0 0 0 0 HIZx 1 = HPx is muted and output is in High-Impedance Mode (see Table 2). 0 = Normal operation. BYPEN 1 = DPST analog bypass switch is closed. 0 = DPST analog bypass switch is open. SHDNB 1 = Normal operation. 0 = Low-power Shutdown Mode.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 26 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Address B7 B6 B5 B4 B3 B2 B1 B0 0x02 DIFFIN43 DIFFIN 21 PGAIN43 PGAIN21 default 0 0 0 0 0 0 0 0 DIFFIN43 1 = IN4 and IN3 are configured as a differential pair. 0 = IN4 and IN3 are independent. DIFFIN21 1 = IN2 and IN1 are configured as a differential pair. 0 = IN2 and IN1 are independent. PGAIN43 PGAIN43 sets the pre-amplifier gain for IN4 and IN3. PGAIN21 PGAIN21 sets the pre-amplifier gain for IN2 and IN1. PGAINxx [2:0] Pre-Amplifier Gain (dB) PGAINxx [2:0] Pre-Amplifier Gain (dB) 000 0 100 12 001 3 101 15 010 6 110 18 011 9 111 21 Address B7 B6 B5 B4 B3 B2 B1 B0 0x03 SELSPA4 SELSPA3 SELSPA2 SELSPA1 HPRAMPSPEED HPZCD HPRAMP default 0 0 0 0 0 0 0 0 0x04 SELHPL4 SELHPL3 SELHPL2 SELHPL1 SELHPR4 SELHPR3 SELHPR2 SELHPR1 default 0 0 0 0 0 0 0 0 SELSPAx 1 = Channel INx is added to the speaker amplifier’s input. 0 = Channel INx is disconnected from the speaker amplifier’s input. If all four SELSPAx bits are 0, the speaker amplifier is turned off and the SPKRP and SPKRN outputs stop switching. SELHPLx 1 = Channel INx is added to the left headphone amplifier’s input. 0 = Channel INx is disconnected from left headphone amplifier’s input. If all four SELHPLx bits are 0, the left headphone amplifier is turned off. SELHPRx 1 = Channel INx is added to the right headphone amplifier’s input. 0 = Channel INx is disconnected from right headphone amplifier’s input. If all four SELHPRx bits are 0, the right headphone amplifier is turned off. HPRAMPSPEED HPRAMPSPEED sets timing for the headphone amplifiers’ ramp function according to Table 4. HPZCD 1 = Headphone amplifier zero-crossing detection is enabled. 0 = Headphone amplifier zero-crossing detection is disabled. HPRAMP 1 = Headphone amplifier volume ramping is enabled. 0 = Headphone amplifier volume ramping is disabled.
HPxVOL sets the gain of the headphone amplifiers according to Table 19. Table 19. Headphone Amplifier Gain Settings 1 = The headphone noise gate attack function obeys headphone zero-crossing detection and ramp settings. HPNGTHRESH sets the threshold voltage for the headphone amplifiers’ noise gate function according to Table 1. HPNGTIME sets the timing for the headphone amplifiers’ noise gate function according to Table 6.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 28 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Address B7 B6 B5 B4 B3 B2 B1 B0 0x08 ERC 0 0 0 SPRAMPSPEED SPZCD SPRAMP default 0 0 0 0 0 0 0 0 ERC 1 = Speaker amplifier edge-rate control is enabled. 0 = Speaker amplifier edge-rate control is disabled. SPRAMPSPEED SPRAMPSPEED sets timing for the speaker amplifier’s ramp function according to Table 17. SPZCD 1 = Speaker amplifier zero-crossing detection is enabled. 0 = Speaker amplifier zero-crossing detection is disabled. SPRAMP 1 = Speaker amplifier gain ramping is enabled. 0 = Speaker amplifier gain ramping is disabled. Address B7 B6 B5 B4 B3 B2 B1 B0 0x09 SPNGZRA SPNGTHRESH SPNGZRR SPNGTIME default 0 0 0 0 0 0 0 0 SPNGZRA 1 = The speaker noise gate attack function obeys speaker zero-crossing detection and ramp settings. 0 = The speaker noise gate attack (mute) function occurs imm ediately rather than waiting for zero-crossing detection or ramping. SPNGTHRESH SPNGTHRESH sets the threshold voltage for the speaker amplifier’s noise gate function according to Table 14. SPNGZRR 1 = The speaker noise gate release (un-mute) function obeys speaker zero-crossing detection and ramp settings. 0 = The speaker noise gate release (un-mute) function o ccurs immediately rather than waiting for zero-crossing detection or ramping. SPNGTIME SPNGTIME sets the timing for the speaker amplifier’s noise gate function according to Table 15. Address B7 B6 B5 B4 B3 B2 B1 B0 0x0A THMAX THVBATT default 0 0 0 0 0 0 0 0 THMAX THMAX sets the maximum threshold voltage for the speaker amplifier’s AGC according to Table 9. THVBATT THVBATT sets the clipping level relative to VBATT for the speaker amplifier’s AGC according to Table 10.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 29 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Address B7 B6 B5 B4 B3 B2 B1 B0 0x0B 0 AGCATTACK 0 AGCRELEASE default 0 0 0 0 0 0 0 0 AGCATTACK AGCATTACK sets the attack speed for the speaker amplifier’s AGC according to Table 12. AGCRELEASE AGCRELEASE sets the release speed for the speaker amplifier’s AGC according to Table 13. Address B7 B6 B5 B4 B3 B2 B1 B0 0x0C 0 0 AGCMIN default 0 0 0 0 0 0 0 0 AGCMIN AGCMIN sets the minimum gain for the speaker amplifier’s AGC according to Table 11. Address B7 B6 B5 B4 B3 B2 B1 B0 0x0D 0 0 PRESENTGAIN PRESENTGAIN (Read only) PRESENTGAIN is the actual gain setting for the speaker amplifie r according to Table 11 . The target value for PRESENTGAIN is set by STARTGAIN. However, PRESENTGA IN may be changed automati cally by the AGC or the noise gate. PRESENTGAIN does not include PGAINxx. Gain for the entire speaker amplifier signal path is defined by PGAINxx + PRESENTGAIN. Address B7 B6 B5 B4 B3 B2 B1 B0 0x0E 0 0 STARTGAIN default 0 0 0 0 0 0 0 0 STARTGAIN STARTGAIN is the volume setting for the speaker amplifier according to Table 11. Address B7 B6 B5 B4 B3 B2 B1 B0 0x0F 0 0 MCSSMT SSMT default 0 0 1 0 0 0 0 0 SSMT Sets the spread-spectrum modulat ion of the class-D amplifier. See Table 20 for the amount of modulation . A setting of 000 results in a ±5.3% modulation in the speaker amplif ier’s output frequency. A setting of 100 disables spread- spectrum modulation.
Table 20. Class-D Spread-Spectrum Modulation Trim master clock does not modulate the class-D output frequency because the triangle wave generator is PLL controlled. Table 21. Master Clock Spread-Spectrum Modulation Trim
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 31 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier Applications Information Layout Considerations General layout and supply bypassing play a major role in analog performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation (contact Fairchild for details). Following this layout configuration provides optimum performance for the device. For the best results, follow the steps and recommended routing rules listed below. Recommended Routing / Layout Rules Do not run analog and digital signals in parallel. Use separate analog and digital power planes to supply power. Place the speaker amplifier output as close as possible to the speaker element to reduce EMI. Traces should be run on top of the ground plane at all times. No trace should run over ground / power splits. Avoid routing at 90-degree angles. Place bypass capacitors within 0.1 inches of the device power pin. Minimize all trace lengths to reduce series inductance.
Figure 27. 25-Bump, 0.4mm Pitch, Wafer-Level Chip-Scale Package (WLCSP) warranty therein, which covers Fairchild products.
0.005 CAB
0.05 C E
A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. ±39 MICRONS (547-625 MICRONS). G. DRAWING FILNAME: MKT-UC025AArev2.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB2200 • Rev. 1.0.1 33 FAB2200 — Audio Subsystem with Stereo Class-G Headphone Amplifier