F38C70

F38C70 NSC | Alldatasheet

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. NATL SEMICOND {UP/UC} O2E D | 6501128 OObe225 9 | 38C70 7 ¥P-/P-OF Single-Chip Microcomputer Microprocessor Product Description Connection Diagram 40-Pin DIP The Fairchild F98C70 8.bit single-chip microcomputer is a member of the F387X series; it executes all of the F8 . _ instruction set and Is software-compatible with the F3870. wuch whee “ Additional power-save instructions provide two different xu qe a9 Faaeset power-save modes. mat 38 tect int Implemented in lon-Implanted CMOS doublepoly silicon- me i =a gate technology, the F38C70 offers maximum cost effec- Pocys hd aly tiveness in a wide range of applications requiring very low Poa E6 i mad power consumption. ~_ =i oe =o os ies More than 70 commands of the F8 instruction set are pate ed la 4 | executed by the single-chip microcomputer, which features re a Paes 2048 bytes of ROM, 64 bytes of scratchpad RAM, a pro- Pan sos grammable timer, 32 bits of VO, and a single +5 V aoe a es: power supply. rai 20) Pas rade se © Single CMOS integrated Circuit POs as faes © Software-Compatible with F8 and F3870 Pate sen © —2048-Byte Mask Programmable ROM an ube © 64-Byte Scratchpad RAM eon zh Fine © 32-.Bit 10 with Four Options sats nara, © Bit Programmable Timer with 16-Bit vest 2 xifareer Programmable Prescaler : © External Interrupt © Crystal, LG, RG, or External Clock {ep view © Single +5 V (10%) Power Supply © Power-Save (PS) and Power-Save All (PSA) a ; Modes © Option for all Short Machine Cycles Signal Functions © Direct Replacement for F3870 i @ Low Power (50 mW typ., 5 mW in PS mode, py, : 0.5 mW in PSA mode) evoee {7h sy : Fo, Fale : . FO, "3, 70, Fila : lr, ah i 70. ae ++/r0, Ri, : a i” Perr : port ) >|FOr 5, : aooness re a bed i an Pl i <elen, 4, : i pad iy ps pee : . fe, Pa] H ca i pan neser | ‘ss SSS 4-29 2566 a-43

. || NATL SEMTCOND tuP/UC? OBE D Pesorse2s ooneee, o / F38C70. FYG/D-0OF ; Ss Figure 1 Block Diagram i ———Vee— 40 i ‘Ector : er Poa fom mane Bo i ris Po.—17 i P16 Fa INDIRECT tla sagan [> sees? [> voronrs ra i = Fas i Patt Pay—13 Pa 4 Pay 15 STROBE Bien F531 | a ed P5268 ( 2567 a-14 ‘30 | nr ‘ |

“' NATL SEMICOND {UP/UC} O2E D | 6501126 oObee27 2 | F38C70 . : FESPA P-OF- i Main Control Logic . contiguous scratchpad bytes. For example, when the iow- : order octal digit Is incremented or decremented,.the ISAR : The instruction register (IR) receives the operation code is incremented from octal 27 (0'27) to 0'20 or Is (OP code) of the instruction to be executed from the pro- decremented from 0'20' to 0'27’. This feature of the ISAR is . gram ROM. through the data bus. Eight bits are latched into very useful in many program sequences. the IR during all OP code fetches. Some instructions are completely specified by the upper four bits of the OP code; All six bits of the ISAR can be loaded at one time, or elther i in these Instructions, the lower four bits are an immediate half can be loaded independently. j register address or an immediate 4-bit operand. Once latch- - : ed Into the IR, the main control logic decodes the instruc- The decimal scratchpad registers (9 through 16) are given tion and provides the necessary control gating signals to all mnemonic names (J, H, K, and Q) because of special circuit elements. linkages between these and other registers, such as the stack register. These special linkages simplify the perfor- ROM Address Registers mance of multt-level interrupts-and subroutine nesting. For Four 12-bit registers are associated with the program ROM: example, the Instruction LR K,P stores the lower eight bits program counter PO, stack register P, data counter DCO, of the stack register into register 13 (K lower, or KL) and and auxiliary data counter DC1, The program counter is us- stores the upper three bits of P into register 12 ed to address instructions or immediate operands; the {K upper, or KU). stack register is used to save the contents of PO during an interrupt or subroutine call. Thus, P contains the return ad- Arithmetic and Logic Unit (ALU) dress at which processing is to resume upon completion of After receiving commands from the main control logic, the the subroutine or the Interrupt routine, ALU performs the required arithmetic or logic operations (using the data presented on the two input buses) and pro- The data counter Is used to address data tables, This vides the result on the result bus. The arithmetic operations register is autoincrementing. Of the two data counters, only Performed in the ALU are binary add, decimal adjust, add : DCO can access the ROM; however, the XDC instruction with carry, decrement, and increment. The logic operations : allows DCO and DC1 to be exchanged. performed are AND, OR, exclusive-OR, ones complement, shift right, and shift left.-The ALU also provides four signals : Associated with the address registers is a 12-bit adder! Presenting the status of the result. These signals, stored in Incrementer. This logic element is used to increment PO status register W, represent the carry, overflow, sign, and or DC when required and to add displacements to PO on zero condition of the operation, ' relative branches or to add the data bus contents to DCO in : the add data counter (ADC) instruction, Accumulator i ‘The accumulator (ACC) is the prinicpal register for data i Program ROM manipulation within the F38C70, The ACC serves as one in- . The microcomputer program and data constants are stored put to the ALU for arithmetic or logic operations; the in the 2048 X 8 byte program ROM. When a ROM access is Tesults of ALU operations are stored in the ACC. required, the appropriate address register (PO or DCO) is gated onto the ROM address bus and the ROM output is Status Register gated onto the main data bus. The first byte in the ROM is The status (W) register holds five status flags: : location zero. 43 2 1 0 BITNo. SUMMARY OF SraTUS BITS Scratchpad and ISAR sTatus ovenr.owecanar, «canary The scratchpad provides 64 8-bit registers that can be used leoTe Te] ] rien ZERO =KUUy AID, ACD, AAUO,A as general purpose RAM memory. The indirect scratchpad peed canny wong ADA RED AUD 1 address register (ISAR) is a 6-bit register used to address son aay : the 64 registers. All 64 registers can be accessed using the 2€RO t ISAR, In addition, the lower order 12 registers can also be OVERFLOW A directly addressed. MTERPUPT COMTROL BT : i The ISAR can be visualized as holding two octal digits. This division of the ISAR Is important, since a number of Instruc- . tions increment or decrement only the least significant . three bits of the ISAR when referencing scratchpad bytes through the ISAR, This simplifies referencing a buffer of 431 2368 6-01 os i

Figure 2. Timer and Interrupt-Control Port Block Diagram ,

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i NATL SEMICOND {UP/UC} O2E D J escues O0b2229 & | | F38C70 : : PSPSPS Timer and interrupt Control Port prescaler values are +2, +5, +10, +20,+40, +100, and t The timer is an 8-bit binary down counter that is software- + 200. If bits 5, 6, and 7 of the interrupt control port are set, i programmable to operate in one of three modes: interval and the contents of either of the two prescaler registers are i timer, pulse width measurement, or event counter, As not zero, the timer uses the value that is held in the two i shown in figure 2, an 8-bit register (interrupt control port), a registers as a 16-bit prescaler value. : programmable 16-bit prescaler, and an 8-bit modulo-N i register are associated with the timer. Any of three conditions will cause the prescaler to be reset: ; i The timer mode, prescale value, timer start and stop, active 1, When the timer is stopped by clearing ICP bit 3 i level of the EXT INT pin, and interrupt local enable/disable | are selected by the proper bit configuration output from the 2. When an output instruction to port 7 (the timer is | accumulator to Interrupt control port 6 with an OUT or assigned Port Address 7) is executed a | OUTS instruction. Bits within the interrupt control port are i defined as follows: 3. On the trailing edge transition of the EXT INT pin q when in the pulse width measurement mode ! Bit 0 = External interrupt enable ' Bit 1 = Timer interrupt enable An OUT or OUTS instruction to port 7 loads the contents of : Bit 2 = EXT INT active level the accumulator to both the timer and the 8-bit modulo-N i Bit 3 = Start/stop timer register, resets the prescaler, and clears any previously HT Bit 4 = Pulse width/internal timer ‘stored timer interrupt request. The timer is an 8-bit down- Bit 5 = +2 Prescaler control counter clocked by the prescaler In both the interval timer Bit 6 = +5 Prescaler control mode and the pulse width measurement mode. The Bit 7 = +20 Prescaler control prescaler is not used in the event counter mode. The | modulo register is used as a buffer in all three timer Timer modes. Its function is to save the value that was most recently output to port 7. i ‘The F38C70 timer, like the F3870, is an 8-bit programmable down counter, However, the F38C70 has two additional 8-bit Interval Timer Mode i registers (ports 8 and 9) that can be accessed by output in- When ICP bit 4 Is cleared (logic 0) and at least one prescale structions. These registers can be used to generate very bit is set, the timer operates in the interval timer mode. : Jong interval timer interrupts or any desired prescaler value. When bit 3 of the ICP is set, the timer starts counting down : from the modulo-N value. After counting down to H’01’, the i A special situation exists when reading the interrupt control timer returns to the modulo-N value at the next count. On i port with an IN or INS instruction). The accumulator is not the transition from H'01' to H'N’, the timer sets a timer in- | loaded with the content of the ICP; instead, accumlator bits terrupt request latch. Note that the interrupt request latch { 0 through 6 are loaded with zeros, and bit 7 is loaded with is set by the transition of H'N' in the timer, thus allowing a . the logic level being applied to the EXT INT pin. Thus, the full 256 counts if the modulo register is preset to H'00’. i status of EXT INT can be determined without needing to service an external Interrupt request. This capability is If bit 1 of the ICP is set, the interrupt request is passed on useful in establishing a high-speed polled handshake pro- to the CPU section of the F38C70, However, if bit 1 of the cedure or for using EXT INT as an extra input pin if external ICP Is a logic 0, the interrupt request Is not passed on the i interrupts are not required and the timer is used ‘only in the the CPU section, although the interrupt request latch re- : interval timer mode. mains set. If ICP bit 1 is subsequently set, the interrupt F request is then passed on to the CPU section. (The inter- 3 The rate at which the timer is clocked in the interval timer rupt request is acknowledged by the CPU section only if : mode is determined by the frequency of an Internal @ clock ICB is set.) Only two events reset the timer interrupt re- : and by the division value selected for the prescaler. (The in- quest latch: the timer interrupt request is acknowledged by : ternal @ clock operates at one-half the external time base the CPU section, or a new load of the modulo-N register ' frequency.) Assuming ports 8 and 9 have been loaded with Is performed. i zeros, If ICP bit 5 Is set and bits 6 and 7 are cleared, the i prescaler divides by two. in the same manner, If bit 6 or 7 If the modulo register is loaded with H'64' (decimal 100), H Is Individually set, the prescaler divides © by 6 or 20, the timer interrupt request latch is set at the 100th count H respectively. Combinations of bits 5, 6, and 7 may also be following the timer start and the latch is repeatedly set on selected, For example, if bits 5 and 7 are set, while 6 is precise 100-count intervals. If the prescaler Is set at + 40, cleared, the prescaler will divide by 40, Thus, possible the timer interrupt request latch Is set every 4000 © clock

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NATL SEMICOND {UP/UC} O2E D | 4501124 0062230 2 I - H . . ZZ. — ! F38C70 Ti YIASP OS a periods. For a 2mHz @ clock (4-mHz time base frequency), {ts inactive level, The active level of EXT INT Is defined by . this produces 2 ms Intervals. ICP bit 2: It cleared, EXT INT is active low; if set, EXT INT Is. i active high. 1 ports 8 and 9 are loaded with zeros, the range of possible intervals Is from 2 to 51,200 © clock periods (1 ys to 25.6 I ICP bit 3 is set, the prescaler and timer start counting ms for a 2-mHz @ clock). However, approximately 50 © when EXT INT transfers to the active level. When EXT INT : periods is a practical minimum, because the time between retums to the inactive level, the timer stops, the prescaler ! setting the interrupt request latch and the execution of the resets, and, if ICP bit 0 is set, an external interrupt request : first instruction of the Interrupt service routine is at least latch Is set. (Unlike timer Interrupts, external Interrupts are : 29 @ periods (the response time is dependent on how many not latched If the ICP Interrupt enable bit is not set.) i privileged instructions are encountered when the j request occurs). As in the Interval timer mode, the timer can be read at any { time and can be stopped at any time by clearing ICP bit 3 i To establish time intervals greater than 51,200 ® clock (the prescaler and ICP bit 1 function as described in the in- t periods, the 16-bit prescaler or the timer interrupt service terval timer mode section). The timer still functions as an : routine can be used to count the number of interrupts, sav: &>bit binary down counter with the interrupt request latch | ing the result In one or more of the scratchpad registers un- set on the timer's transition from H'01" to H'N" (modulo-N 1 til the desired interval Is achieved. Virtually any time value). Note that the EXT INT pin has nothing to do with } interval, or several time intervals, can be generated using loading the timer; its action is that of automatically starting | this technique. and stopping the timer and of'generating external inter- rupts. Pulse widths longer than the prescale value times the | The timer Is read at any time and In any mode, using an in- modulo-N value are easily measured by using the timer in- ' put instruction (IN 7 or INS 7), and can take place “on-the- terrupt service routine to store the number of timer i fly" without Interfering in normal timer operation. Also, the interrupts in one or more scratchpad registers. timer can be stopped at any time by clearing bit 3 of the ICP. The timer holds its current contents indefinitely and The actual pulse duration Is typically slightly longer than . resumes counting when bit 3 Is set again. The prescaler is the measured value, because the prescaler status Is not reset whenever the timer Is stopped; thus, a series of readable and Is reset when the timer Is stopped. Thus, for . starting and stopping results in a cumulative maximum accuracy, It Is advisable to use a small truncation error. division setting for the prescaler, For a free-running timer in the interval timer mode, the time Event Counter Mode interval between any two Interrupt requests can be In error When ICP bit 4 is cleared and all prescale bits (ICP bits 5, by +6 ® clock periods, although the cumulative error over 6, and 7) are cleared, the timer operates in the event . many intervals Is zero. The prescaler and timer generate counter mode. This mode Is used for counting pulses ap- : precise intervals for setting the timer interrupt request plied to the EXT INT pin. If IGP bit 3 Is set, the timer will latch, but the time out can occur at any time within a decrement on each transition from the Inactive level to the : machine cycle. (There are two machine cycle types: short, aotiva level of the EXT INT pin. The prescater is not used in; which consist of 4 © clock perlods, and tong, which consist this mode. As in the other two timer modes, the timer can : of 6 @ clock periods.) The Fairchild multi-chip F8 family has be read at any time and can be stopped at any time by : a write clock signal that corresponds to a machine cycle. clearing ICP bit 3, ICP bit 1 functions as previously describ»: Interrupt requests are synchronized with the internal write ‘ed, and the timer interrupt request latch is set on the . clock, thus providing the possible +6 @ error. Additional timer's transition from H'01" to H'N' (moduto-N value). errors may arise if the Interrupt request occurs while a privileged instruction or multi-cycle instruction is being Normally, ICP bit 0 should be kept cleared In the event executed, Nevertheless, for most applications, all the above counter mode; otherwise, external interrupts are generated : errors are negligible, especially if the desired time interval ‘on the transition from the Inactive level to the active level is greater than one ms, of the EXT INT pin, : Pulse Width Measurement Mode For the event counter mode, the minimum pulse width re- : When ICP bit’ is set (logic 1) and at least one prescale bit quired on. EXT INT Is 2 clock periods and the minimum is set, the timer operates in the pulse width measurement inactive time is 2 © clock periods; therefore, the maximum : mode. This mode is used to accurately measure the dura- repetition rate is 600 Hz. ! tion of a pulse applied to the EXT INT pin. The timer is. { stopped and the prescaler Is reset whenever EXT INT Is at :

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} ' NATL SEMICOND {UP/UC} O2E D | 6501126 0062231 4 I i ee —.- : F38C70 roa Yr. SP-0, ia i Extemal interrupts The power-on clear circuitry contains on-chip sensors to ‘ When the timer Is in the interval timer mode, the EXT INT monitor various conditions. The following conditions must : pin Is available for non-timer related interrupts. If ICP bit 0 be satisfied before the power-reset sequence is allowed is set;an external Interrupt request latch is set for a transi- to start: tion from the inactive level to the active level of EXT INT. (The EXT INT signal is an edge+triggered Input) The inter- 1. Supply voltage must be above a certain value, Tupt request Is latched elther until acknowledged by the typically +3 V to +4 V. : CPU section or until ICP bit 0 is cleared (unlike timer inter- : fupt requests that remain latched even when ICP bit 1 is 2. The clocks of the device must be functioning. i cleared). : 3. The substrate bias must reach a certain level. i Extemal interrupts are handled in the same fashion when the timer is in the pulse width measurement mode or in the All three conditions must be met before the power-on clear event counter mode, except that when in the pulse width Circuitry initiates a reset cycle, However, these conditions Measurement mode, the external interrupt request latch is can be satisfied even with a supply voltage of as low as 3 : set on the trailing edge of EXT INT (that is, on the transi- volts. The latest versions of the F38C70 have a modifled i tion from the active level to the inactive level). delay circuit that gives a typical delay of 500 ys (with a 4 : mbz crystal) after the above conditions are met. This is an : Interrupt Handling improvement over the earlier F38C70 versions. j When elther a timer or an external interrupt request is com- | municated to the CPU section of the F38C70, it is Since the F38C70 is only guaranteed to operate at a supply acknowledged and processed at the completion of the first voltage of 4.5 V or greater, the user must ensure that the | Non-privileged instruction if the interrupt contro! bit of the Supply voltage is at least 4.5 V when the F38C70 initiates Hi status register Is set. if the interrupt control bit is not set, the reset cycle. For power supplies having a slow rise time, | the interrupt request continues elther until the interrupt an external RC network can be converted to the external { control bit is set and the CPU section acknowledges the in- reset Input of the F38C70 to hold the device in a reset state : terrupt or until the interrupt request is cleared (as previous- ong enough to allow the power supply to reach a voltage ly described). of 4.5 V. For example: i If a timer interrupt request and an external interrupt request in : ‘occur simultaneously, when the CPU section starts to pro- i cess the requests, the timer interrupt is R : handled first. i rare EXTERNAL RESET i When an interrupt is allowed, the CPU section requests i that the interrupting element pass Its interrupt vector ad- : : dress to the program counter through the data bus. The c vector address for a timer interrupt Is H'020'. The vector ad- i dress for external interrupts is H'0A0’. After the vector ad- dress is passed to the program counter, the CPU section : sends an acknowledge signal to the appropriate interrupt : : request latch, which clears that latch. The Interrupt service External Reset routine executes; the return address of the original program : s automatically stored in stack When the RESET signal is taken low, the contents of the : register P, Program counter are pushed to the stack register and the Program counter and the ICB of the status register are : Power-On Clear Cleared, The original stack register contents are lost. As | ~ with power-on clear, ports 4, 5, 6, and 7 are loaded with t The F38C70 contains power-on clear circuitry to H'00". The contents of all other registers and ports are un- : automatically reset the internal logic following the applica- changed. When the RESET signal is taken high, the first i tion of external power. Since many variations of power sup: Program instruction is fetched from ROM location H'0000'. i ply circultry exist, Fairchild cannot guarantee that the 1 Power-on clear will operate under every power-up condition. H 2572 8-05 435 | . y

NATL SEMICOND {UP/UC} O2E D | 6501128 Oob2232 & I ~ a F38C70 W-LPSP OF: i EE Figure 3 Clock Configurations aT curt = 4MHE OPEN EXTERNAL ‘eLock Yoo fe] . a CST can * : se omirreo) bede=d * ‘Cextennat (OPTIONAL) Minimum f= 4k0 : Example with CextemwaL=0 (210 pF# 13 pF+CexreaNaL As 15 kot 6% 1 . C= 205 pF £25 pF+C, f= 2.9 MHz 26% —_ A se +CexTERNAL {ae . —_ I =0.1 {win ® TRC+ 650 Minimum Gea) Example with CextennaL= 0 L=03 mH + 10% . tox 1 Maximum Cexrernat = 90 PF AO RC+ 1519 f= 3.0 MHz 10% ee Ee Test Logic The TEST pin capabilities are impractical for user applica- tlons because of timing complexities; however these Special test logic Is Implemented to allow access to the In- capabilities are sufficient to enable Fairchild to Implement ternal main data bus for test purposes. in normal operation, rapid methods for thoroughly testing the F38C70. the TEST pin must be connected to ground. When the TEST : a signal Is set to Vpp, port 4 becomes an output of the Inter- Clocks nal data bus and port § becomes a wired-OR Input to the In- . ternal data bus, The data appearing on the port 4 pins is The time bases for the F38C70 originate from one of four logically true, whereas input data forced on port 5 must be external sources by mask options. These four configura- logically false. When the TEST signal Is set to one-half the tlons are Illustrated In figure 3. External capacitors are not level of Veg (Vcc/2), the ports act as above and the 2K X 8 required. In all external clock modes, the external time base program ROM is prevented from driving the data bus, In frequency.|s divided by two to form the internal @ clock. this mode, operands and Instructions are forced externally The selection of clock configurations Is by mask options. through port 5 Instead of being accessed from the program . ROM, When the TEST signal Is In elther the Vop/2 or the . . _ high state, the STROBE signal ceases Its normal function : and becomes a cycle clock (identical to the F8 multi-chip system write clock, except Inverted). . a 0658 €-09 446

:, NATL SENICOND {UP/UC} O2E D Jp escii2s 00b2233 8 | i . F38C70 . FSIS 9-08 eee Figure 4 F38C70 Programmable Registers and Ports 1 ° meemnnon f 7 o ° ° ° i toa 4 ran yor eC ogo : : aoonese 1 | 4 | » A : son pe 2 oe ow : ‘0 u KL 3 cc) 18 ara of 4 “oe ow S8tooran a eee sw » ° ye ae [| | os ween for I Ink on ® ° se on ne comm « oon eon n : so 7 : A 1 ‘ ae wren ponte vo eon son : 2 seal presonuen mv ROBE ‘ “| . wow SERRE

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:: ' NATL SEMICOND {UP/UC} O2E D | 6501128 OOb2234 0 | | Fescro FUP/POE a Figure 5 PS Instruction savenseron cv vagaries se maa” a SERVICE EXTERNAL FETCH NEXT ‘SERVICE TIMER, FETCH NEXT { Figure 6 PSA Instruction : PSA. meqwence : wane ve i FROM LOCATION | | ne senetlamn scale i et

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: | € NATL SEMICOND {UP/UC} OeE D i 6501128 0062235 1 | F38C70 FE LP SIO Instruction Set PowerSave All Mode When the power-save all instruction (mnemonic PSA, Op ‘ The F38070 executes the entire instruction set of the F3870 _cade 2F) is executed, the F38C70 halts all its operations family. In addition, two instructions exclusive to the F38C70 and goes into a power-save mode (refer to Figures and 6). : allow the F38C70 to further reduce its power consumption The microcomputer is returned to the previous operating by entering into one of two power-save modes. status by an external reset or an external interrupt. Both the ; timer and prescaler are reset when PSA is executed, except t A summary of programmable registers and ports is shown in the event counter mode. in Figure 4, Table 1 lists the F38C70 instruction set and { F8-compatible instructions, In returning from either power-save mode, the microcom- i puter exercises the interrupt routine or continues with the | Power-Save Mode next instruction, depending on whether the interrupt is When the power-save instruction (mnemonic PS, OP code enabled. ‘| 2D) Is executed, the F38C70 halts all its operations except the timer and Interrupts. The microcomputer is returned to If the return is by an external reset, the microcomputer H the operating status by an external reset, an external inter- restarts from the reset mode. : Tupt, or a timer interrupt (as the timer Is timed out). Table 1 F38C70 Instruction Set and F8-Compatible Instructions i Accumulator Group Instructions : [wr | pram Status Bits Operation OP Code _| Op OVE Zero CRY Sign ‘Add Carry LNK ACC + (ACC) + CRY 19 10 10 10 10 ‘Add immediate Al it | ACC + (aco) H «it 24 10 10 10 1/0 And Immediate NI ii | ACG (aco) H Air 2tii 0 0 0 10 Clear cLR ACG ~ H'00" 70 : ‘Compare Immediate cl uo | Hae 261i 10 10 10 10 Complement com ACC -+ (ACC) eH'FF* 18 0 W 0 10 Exclusive or xi Wi | ACC + (ACC) @ Hil 23 1 0 1 0 10 ‘ Immediate : Increment INC ACC -* (ACC) + 1 1F 110 110 40 110 : Load Immediate u i | Accs HA 20 ---- i Load Immediate Short} Lis 1 | Acc Hor 7i ---+- : Or Immediate ol fi | ACC (Aco) V Hit 22ii 0 10 0 10 Shift Left One SL 1 | Shift Left 1 13 0 10 0 10 Shift Left Four st 4 | Shift Left 4 15 0 10 0 10 . Shift Right One SR 1 | Shift Right 4 12 0 10 0 10 Shift Right Four SR 4 _| shift Right 4 14 0 0 0 10 t i _—_— : (2576 B-09 439 | (manors ep

j NATL _SEMTCOND _TUP/UC} O2E D | 6501124 OOb223b 3 I ! F38C70 KV S?O (ne ee Table 1 F38C70 Instruction Set and F8-Compatible Instructions (Continued) Branch Instructions (In all conditional branches, PO (PO) + 2if the test conditions are not met. Execution is complete in 30 cycles.) Mnemonic] Machine Status Bits Operation OP Code | Operand Code | Bytes OVF Zero CRY Sign Branch on Garry Bc aa PO + [(PO) + 1] + Hiaa' if 82 aa 2 | 35 ---- CRY = 1 Branch on Positive P aa PO [(PO) + 1] + H'aa’ if 8iaa 2 | 35 ---- Branch on Zero BZ aa PO ~ [(PO) + 1] + Hiaa’if 84aa 2 | 35 ---- Zero = 1 : Branch on True BT taa | PO+{(PO) + 1] + H'aa' it any test is true 8t aa 2 | 35 ---- 4- TEST CONDITION zero | crY [SIGN | : Branch if Negative 8M aa PO + {(PO) + 4] + H’aa’ it Staa 2 | 35 ---- s Sign = 0 Branch if No Carry BNC aa PO + [(PO) + 1] + H’aa’ if 92 aa 2 35 ---- Cary #0 . Branch if No Overflow} BNO aa PO+[(PO)i + 1] + Hiaa' if | 98 aa 2 | 35 ---- i OVF = 0 Branch if Not Zero BNZ aa PO + {(PO) + 1) + H’aa’ it 94 aa 2 35 ---- i Zero = 0 : Branch if False Test BF taa | PO+{(PO) + 1] + Hiaa’if all] 9taa 2 | 35 ---- false test bits 1 = TEST CONDITION i [> |e |x |e : [ove [Zeno [cry | sian] : Branch If ISAR(Lowen7 BR7 aa PO~ {(PO)+1]+H'aa" If ISARL | 8Faa 2 | 25 ---- PO +-(PO) + 2ifISARL = 7 | 20 —-|-- Branch Relative BR aa PO ~{(PO) + 1] + Hiaa’ 90 aa 2 | 35 ---- Jump? ump | aaaa | PO + Haga’ waa | 3 | 55 —---- +P aon ; Note i IMP and P1 change accumulator contents to the high byte address. i

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4-40 |

to _ NATL SEMICOND {UP/UC} D@E D | 6501128 0062237 5 | . F38C70 Ky? S? . <= SP OF Table 1 F38C70 Instruction Set and F8-Compatible Instructions (Continued) Memory Reference Instructions (In all memory reference instructions, the data counter is incremented DC~-DC — 1) Mnemonic] Status Bits Operation OP Code |Operand} Function Bytes OVE Zero CRY Sign Add Binary AM JACC~(ACC) + [(0C)] 88 1 25 1/0 1/0 110 110 Add Decima! AMD IACC+{ACC) + [(0C)} 89 1 25 110 1/0 1/0 10 AND NM IACC+-(ACC)AT(OC)) 8A 1 25 0 10 0 10 COMPARE cM KOC) + (ACC) + 1 8D 1 25 10 110 110 110 EXCLUSIVE OR XM |ACC*(ACC) @ ((DC)] 8c 1 25 0 1 0 10 LOAD iM IACC+[(00)) 16 1 25 ---- LOGICAL OR om JACC+(ACC) y(0C)] 8B 1 25 0 10 0 10 STORE sT (0c)-(ACc) 7 1 25 ee Address Register Group Instructions [Mnemonic Machine Status Bits Operation OP Code | Operand Code _| Bytes OVE Zero CRY Sign Add to Data Counter | ADC DC+(0C) + (ACC) 8E 1 25 ----+ Call to Subroutine PK Px{PO}OPOU~(r12) + oc 1 4 ---- PL+(r13) Call to Subroutine PI aaaa_| P~(P)PO-H'aaaa’ $ 2baaaa | 3 65 ---- Immediate Exchange DC xo octpc1 2c 1 2 ---- Load Data Counter uR 0C,Q | DCU+(r14), DCL=(r15) OF 1 4 ---- Load Data Counter LR DGH | DCU+(r10), DCL~(r11) 10 1 4 ----+ Load DC Immediate pet aaaa_| DC+H'aaaa’ 2Aazaa | 3 6 ---- Load Program Counter| LR PO,Q | POU+(r14), POL~(r15) oD 1 4 ----+ Load Stack Register LR PK | PUH(12), PL=-(r13) 09 1 4 +o-- Return From POP Pow 1c 1 2 ---- Subroutine Store Data Counter LR Q,DC | r4+(0CU), 15-(OCL) OE 1 4 ----+ Store Data Counter LR H,DC | r10+(0CU), 11-(0CL) n 1 4 —---- Store Stack Register LR KP | 12+(PU), r13—P 08 1 4 ----+ Ee i

2578 B-11 4-41 |

"NATL SEMECOND {UP/UC} O2E D Pf) LSOL228 OOL2238 2 | i F38C70 VPSPOE eee Table 1 F38C70 Instruction Set and F8-Compatible Instructions (Continued) . ‘Scratchpad Register instructions (refer to scratchpad addressing modes.) ' Mnemonic Status Bits Operation OP Code | Operand OVF Zero CRY Sign Add Binary AS t ACC(ACC) + (A) cr 1 1 10 10 10 10 Add Decimal ASD r ACC+(ACC) + (7) Or 1 2 10 10 110 1/0 Decrement Ds id (9) + H'FF’ . or 1 1.6 10 110 110 110 : Load LR Ar ACC+(r) 4r 1 1 ---- t Load LR AKU | AC+(r12) : 0 1 1 ---- i Load LR AKL | ACC~(r13) 01 1 1 aoe Load LR AQU ACC+(r14) 02 1 1 ---- Load LR Aat | acc~(r15) 03 1 1 clll Load LR 5A | rH(ACC) Sr 1 1 Soll : Load LR KU,A | 12+(ACC) 04 1 1 ~- - Load LR KLA | 13+(acc) 05 1 1 Soal ' Load LR Qua | ri4+(acc) 06 1/4 Soll : Load LR QLA | ri5+(ACC) 07 1 1 ---- And NS t ACC=(ACC)A(r) Fr 1 1 0 10 0 10 2 Exclusive Or xs r ACC+(ACC)a(r) Er 1 1 ow 0 i i tess ES

2579 B12 — |

‘' NATL SEMICOND {UP/UCH D2E D I 6501126 0062239 9 | i ~ — Se Table 1 F38C70 Instruction Set and F&-Compatible instructions (Continued) ° Miscellaneous Instructions wo : Mnemonic Status Bits Operation -_ | OP Code p i OVF Zero CRY Sign Disable Interrupt or Reset ICB 1A 2 -- Enable Interrupt* er SETICB . 1B 2 ee lied Input IN ~ aa | ACC + (Input PORT aa) 26aa 4 0 10 0 Ww : Input Short ~ *-INS | ACC + (input PORT a) Aa aslo 10 0 10 Load ISAR tR ISA | ISAR + (ACC) 0B 1 —-- ee i Load ISAR Lower ‘LISL a ISARL ~ a 01101a** 1 -oo oS = a Load ISAR Upper usu a ISARU +a 01100°* 1 -- Load statusregister'| LR WS | W+ (9) 1D 2 1 10 10 10 No-Operation - Nop : PO (PO) +1 2B 1 —- = =- OUTPUT - OUT “aa OUTPUT PORT aa = (ACC) 27 aa 4 --- - OUTPUT Short “OUTS a OUTPUT PORT a + (ACC) Ba ae Store ISAR - LR A185 | ACC + (ISAR) . 0A 1 -- Se Store Status Reg LR JW | aw 1€ 1 ---- Power Save . PS Halt Internal Clock 2D 3 f---- - } Power Save All PSA-- Halt Internal Clock and Timer | 2F 3 --- - i *Privlteged instruction - . { 3bit octal digit oe : 7 i *Two machine cycles for CPU ports i Notes 4 scratchpsd regiter # a Each lower case character represents a hexadecimal digit, k registers #12 ond #13 . Each cycle equals four machina clock periods, KL register #13, . i Lower case denotes variables specified by programmer. KU register #12 - . Po ‘program counter Function definitions POL {east signiticant eight bits of program counter iu FOU most significant eight bits of program counter : + lo roplaced by P stack register : 0 the contents of PL toast significant eight bits of program counter 0 binary ones complement of PU most significant eight bits of active stack register + arithmetic add (binary or decimsl) Q registers #14 and #15 . fogical OR exclusive QL register #15 logical AND QU rogister #14 logical OR inclusive r ‘cratchpadlregister (any addrass through 11) He hexadecimal digit w status register Reglater Names Scratchpad Addressing Modes (Machine Code Formal) a address vartabio 1 = © (hexadecimal) register addressed by ISAR (unmodified) A ‘accumulator 1 =D (hesadecimal register addressed by ISAR, ISAAL incremented oc ata counter (indirect address register) 1 = E (hexadecimal) Register addressed by ISAR, ISARL decremented ct data counter #4 (auxiliary deta counter) 1 =F (no operation performed) DCL —_—_teast significant eight bite of data counter addressed 1 = OB (hexadecimal register 0 through 11 addressed directly DCU most significant eight bits of data counter addressed . from the instivotion 4 scratchped register #10 and #11 : Vand ti immediate operand ‘Status Register 168 interrupt control bit : i is Indirect soratchpad addross register : 1 change in condition ISAR indirect seratchpad address register 110 Is et to 1 oF 0 depending on conditions : ISARL least significant three bits of ISAR CRY any flag ; 'SAAU most significant threo bits of [SAR i LL LS SS SSS SSS i

2580 B-13 443 i

. NATL SEMICOND {UP/UC} O2E D | 6501128 Oob2e40 s | F38C70 KS PSP eS ‘Supplementary Notes For the F38C70, execution of an INS or OUTS Instruction requires two machine cycles for ports 0 and 1, whereas The interrupt control bit of the status register is. ports 4 an § require four machine cycles. When an external automatically reset when an interrupt request Is reset of the F38C70 occurs, PO is stored in P and the old acknowledged. It is then the programmer's responsibility to contents of P are lost. Note that an external reset Is determine when ICB will again be set (by executing an El recognized at the start of the machine cycle and not Instruction). This actlon prevents an interrupt service routine necessarily at the end of an instruction. Thus, If the F38C70 from being interrupted, unless the programmer so desires. Is executing a multi-cycle instruction, that Instruction Is not completed, and the contents of P, upon reset, may not When reading the interrupt control port (port 6), bit 7 of the necessarily be the address of the instruction that would accumulator 1, loaded with the actual logic level being ap- have been executed next. They may, for example, point to piled to the EXT INT pin, regardless of the status of ICP bit an immediate operand, if the reset occurred during the se- 2 (the EXT INT active level bit); that i, if EXT INT is at +5 cond cycle of an LI or Cl Instruction. Additionally, several “ _V, bit 7 of the accumulator is set to a logic 1, but if EXT instructions (JMP, Pl, PK, LR, PO, Q) as well as the inter- INT Is at Vsg, the accumulator bit 7 Is raset to logic 0, rupt acknowledge sequence, modify PO in parts. That is, they alter PO by first loading one part, then the other part, In the instruction set summary (table 1), the number of and the entire operation takes more than one cycle. Should cycles shown are nominal machine cycles. A nominal cycle reset occur during this modification process, the value is defined as 4 ® clock periods, thus requiring 2 ys for a stored in P becomes part of the old PO (the not yet 2-mHz clock frequency (4mHz external time base frequen- modified part), and part of the new PO (already moditied cy). When desired, the long machine cycles can be altered part). Thus, care should be taken (perhaps by external to short machine cycles by mask option. gating) to ensure that reset does not ocour atan undesirable time, if any significance is to be The following nomenclature for register names Is used for given to the contents of P after a reset occurs. consistency with the assembly language mnemonics: If desired, the F38070 can execute all instructions in short F8 —-F8C70 —=Register cycles via mask options to improve the execution speed of PC, PO program counter the device, PC, P stack register _ DC, oC data counter . 1 oc, o¢c1 auxiliary data counter H i fl i

2581 B-14 444 |

NATL SEMICOND tuPsucy Qee D | 6504128 OObe2241 7 | F38C70 F-99928 Signal Descriptions : The F38C70 input and output signals are described in Table 2, Table 2 F38C70 Signal Descriptions Mnemonic | PinNo. | Name Description Clock : XTL, 1 Clock The time base inputs to which a crystal (1 to 4 mHz), LC xT, network, RC network, or an external single-phase clock i is connected, UO Ports PO, ~ PO, 3, 4,5, Port Address The 32 ports are individually used as either TTL-compatible 6, 19, 18 inputs or as latched outputs. 17, 16 : Pi, - 6, 37, 36, Port Address : 35, 34, 22, 23, } _ 24, 25 H Pa, - Pa, 8, 9, 10, HO Port : 14, 12, i _ 13, 14, 15, i PS, —P5, 33, 32, VO Port i 31, 30, ! 28, 28, i 27, 26 InterruptiReset EXT INT External The active state of the external interrupt signal is software ; Interrupt Programmable; it Is also used in conjunction with the timer i for pulse width measurement and event counting, : RESET Reset This Input signal is used to reset the F38C70 externally. When the signal is allowed to go low, the F38C70 resets. : When subsequently allowed to go high, the F38C70 begins program execution at location H'0000. Strobe STROBE 7 Strobe This output pin, which is normally high, provides a single low pulse after valid data is present on the Pay — P4, pins during an output instruction, ee Tost TEST 2 Test An input signal used only in testing the F38G70. For formal circult function, this pin must be connected i to ground, Power . : Vss Ground ‘Common power and signal return ‘ Veo Power Supply Power supply input signal, +5 (+ 10%) V 2582 c-01 “s | ' .

; NATL SEMICOND {UP/UCH O2E p Besories Oob2e42 49 | F38C70 Fe SGSP-OF i DC Characteristics ‘The characteristics of the F38C70 are provided In table 3. Table 3 F38C70 DC Charateristics T,=0° to 70°C, Vog=8V + 10%, I/O Power DissipationsmW : : Symbot_[ Parameter | Min | Max | Unit |. Tost Conditions ; too | Power Supply Curent | | ta0 | ma | Outputs Open : Po Power Dissipation [__[__teo_{_ mw | outputs open ‘ Vinex External Glock input High Voltage | 24 | 8 =| V_ | : Visnex External Clock Input Low Voltage | -os | o6 | v | lex External Clock input High Current | | 100 | wA_| Vinx = 24V. : hex External Clock input Low Current | | -100—«| uA | Vnex = O6V i Vu Input Low Voltage [sos [os |v | is ta Input High Current (except 3- vA | Vin = 24 V, internal pull-up | state option) H in Input Low Current (except open Vi = 04V i drain and direct drive ports) \\ hoo Leakage Current es Se ea i lou Output High Current (except open -100 vA | Von = 24V drain and direct drive ports) std. i lonoo Output Drive Current (push-pull) | -1s | Teo | ma [Von =07Vt015V lox Output Low Current [ae [| ma [Vu = ov i lon Output High Current (STROBE Output) | -300 | |__| Von = 24V ! : lous Output Low Current (STROBE Output) | 50 | | mA | Vo = 04V : Absolute Maximum Ratings Ordering Information i These are stress ratings only, and functional operation at these ratings, or under any conditions above those in- rae Temperature . dicated in this data sheet, is not implied, Exposure to the Number Package Reng : absolute maximum rating conditions for extended periods : of time may affect device reliability, and exposure to F98c70D6 Ceramic c i stresses greater than those listed may cause permanent F38C700L Ceramic L damage to the device. F38C70DM. Ceramic M ! Temperature (Ambient) Under Bias 0°C, +70°C F8C70PC Plastic c ¢ F38C70PL Plastic L Storage Temperature 55°C, + 150°C . seCrOPM Voltage on Any Pin with Respect 03 V, Vog+0.3 V F38C701 | __ Plastic M j to Ground (Except Open Drain Pins) *C = Commercial Temperature Range 0°C to +70°C Power Dissipation Ww L = Limited Temperature Range ~40°C to + 65°C M = Military Temperature Range - 55°C to + 125°C t ; { — a) 2583 c-02 446 | _ a cn ae oe !