F3861DM

F3861 FAIRCHILD | Alldatasheet

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Jk Schlumberger Company Peripheral Input/Output Microprocessor Product a Description Connection Diagram The Fairchild F3861 Peripheral Input/Output (PIO) device wet whee: provides two &-bit I/O ports, external interrupt, and a pro- grammable timer. An 8-bit wide bidirectional data bus vom [2 id he transfers /O data bytes between the F3870 Central voo (] wlion Processing Unit (CPU) and the PIO. veo d+ wwe The PIO is used in systems that require the /O capability exrint (fs aspvow and interrupt functions of the F3851 PSU but do not need parovr Ce Pe the read-only memory (ROM) storage of the PSU. The PIO is ware C17 a FJ ons pin-compatible with the PSU. oe a3 Low. ‘The F3861 PIO has five versions available, each with its mv ReS [Jo ulion own set of preassigned I/O port addresses and interrupt ATH [10 nfgion vectors. or a BaoR C11 wen The F3861 Is manufactured using isoplanar N-channel, no C12 alias silicon-gate technology; therefore, power dissipation is very nome. (]19 2a [oe low (less than 250 mW). owes 14 Fo © 16 Bidirectional, Individualy Controlled I/O Lines nome: [1s aios Organized as Two 8-bit Ports nome: [416 ashe © Programmable Timer-Preset, Start, Stop, and Read- a Back Ability; Selectable Timer Count Rates romeo} 17 brow © Full Interrupt Level-Daisy-Chain Expandable, vss 8 ation Independent Interrupt Address Vectors for Timer and wee foe. External interrupt _* © Pulse Width Measurement Capability Woe (20 21 [1] 08 © TTL and LSTTL Compatible @ +5 Vand +12 V Power Supplies © 2MHz Operation ‘© Low Power Dissipation, Typically Less Than 250 mW Signal Functions ° Bo crock | TV ane De, oe: 1% 08, TO Ay By En TO, 085 TOA, ey |< WOR, 08, TO Ay DBDR Ports pica, fOMC, he omc, }=— } controt ioe ONC, oe ROMC 0B or wit INT REG my ao INTERRUPT 170 8; om oor Yoo Yee Power ss. ES 3-55

Device Organization System Clock Timing The peripheral input/output device includes 1/0 logic, timer All timing within the F3861 PIO is controlled by the @ and logic, interrupt logic, data bus logic and control logic, as WRITE signals, which are input from the F3850 CPU. Refer illustrated in figure 1. to the F3850 data sheet for a description of these clock signals, The WRITE clock refreshes and updates PIO The interrupt logic responds to an interrupt request signal registers, which are dynamic. The © clock also drives the originating from internal timer logic or an external device. programmable timer. Based on priority considerations, the interrupt request is passed on to the F3850 CPU. The programmable timer uses VO Ports a polynomial shift register in conjunction with interrupt logic to generate real-time intervals. The PIO has two bidirectional 8-bit /O ports used to transmit data between itself and extemal devices. In binary The bit data bus in the PIO is the main path for transfer notation, the address for port A is XXXXXX00 and for port B of information between the F3850 CPU and other devices in is XXXXXX01, where the X binary digits are the unique VO the F8 microprocessor system. The device contains four port select code for the PIO (see table 2). For example, if reassigned I/O port addresses: the two lowest are assign- the port select code is 000001, port A may be called port 4 ed to the two I/O ports (A and B) and are used to tranfer and port B may be called port 5. (The PIO port select code data to and from external devices. The other two /O ad- is never designated as all 0s, since ports 0 and 1 are reserv- dresses are assigned to two internal registers of the PIO ed for the F3850 CPU) In addition, the interrupt control Port that control interrupt logic and are treated as 1/O ports. (ICP) is addressed as port XXXXXX10 and the binary timer is addressed as port XXXXXX11, which become ports 6 and Signal Descriptions 7, respectively, for the port select code example given The F3861 input and output signals are described in table 1. above. Figure 1 F3861 Block Diagram Table 2 F3861 Port Addresses a0 age XXxx xx00 | 1/0 Port A xxx xxX01_ | 1/0 Port B Ur 200K XX10 | Interrupt Control Register BUS. XXXX XX11_| Programmable Timer oon vecTon ADDRESS nom

3 Contnot The port and interrupt address vector assignments are

Unes given in table 3. jg exrenwat INTERRUPY Table 3 F3861 Port and Address Assignments (HEX) inrennuet wrennuer | [7 CONTROL voare PRIORITY OUT Version Interrupt Address Vector request | Addresses External FO86TA a7 0600 068C ss 8 F3861B 8B 0340 0300 Yoo oo Ves . ware F 38616 20.23 0320 030 F3961D 24.27 0360 03E0 F3861E 47 0020 000 3:56

A F3861 oe Table 1 F3861 Signal Descriptions tinomorio [Pina | Name | _Besrpion Clock ° 8 Clock The two clock input signals originate at the F3850 CPU. WRITE 7 WO Ports WO Ag- 19, 24, WO Ports A Bidirectional ports through which the PIO communicates with WO Ay 25, 30 logic external to the microprocessor system. 31,36 37,2

10 By - 20, 23, vO Ports B

31, 35, 38,1 Control ROMC 17, 16, Read Only Input signals that originate at the F3850 CPU and control ROMC, 15, 14, Memory internal functions of the PIO. 13, Control Data Bus DBy - 21, 22, Data Bus Bidirectional three-state lines that link the PIO to all other DB; 27, 28, devices within the microprocessor system. 33, 34, 39, 40 DBDR 1" Data Bus A low output, open drain signal that indicates the data bus Drive currently contains data flowing from the PIO. Interrupt Ext iNT 5 External A high-to-low transition on this input signal is interpreted as Interrupt an interrupt request from an external device. INT REG 9 Interrupt This output signal is the INT REQ input to the F3850 CPU; it Request must be output low to interrupt the CPU, which occurs only if PRI IN is low and PIO interrupt control logic is requesting an interrupt. PRI IN 10 Priority Unless this input signal is low, the PIO does not set the INT In REQ signal low in response to an interrupt. PRI OUT 6 Priority This output signal becomes the PRI IN signal to the next Out device in the interrupt-priority daisy chain; it is output high unless the PRI IN signal is entering the PIO low and the PIO is not requesting an interrupt. Power Vop 4 Power 5V (+ 5%) Supply Veo 3 Power +12V (+ 5%) Supply Vss 18 Ground System ground—O V; Vpp and Vag are referenced to Vss. el 36) 3

CC ——— F3861 Port Pin Description When outputting data through an I/O port, the pin can be ‘An output instruction (OUT or OUTS) causes the contents connected directly to @ TTL gate input; data is input to the of the CPU accumulator (ACC) to be latched into the ad- pin from a TTL device output. Since the VO pin and the TTL dressed port. An input instruction (IN or INS) transfers the device output are wire-ANDed, it is possible for the state of contents of the port to the ACC (port 6 Is an exception that one to affect the transfer of data out from the /O pin or in is described later). The VO pins on the PIO are logically from the TTL device output. In most cases, therefore, 1/0 inverted; the schematic of an WO pin and available output port bits should be set for a high level (logic 0) before data drive options are shown in figure 2. Each output pin has an input to prevent incoming logic zeros from being masked output latch that holds the data last output to that pin, The by logic ones present at the port from previous outputs. VO ports of the PIO are configured in the standard However, the ability to mask bits of a port to logic 1 is pull-up option. useful during some input functions. SSC Programmable Timer lagram with Output Butfer Options Figure 21/0 Pin Diagra pu p The &bit shift register, addressable as an I/O port, functions as a polynomial timer. This timer is loaded with a value of Yoo delay; it counts down this value of delay and, after the programmed interval, generates an interrupt through the z interrupt logic of the PIO. Ff > wi The OUT or OUTS instruction is used to load the interval Pare letD- value into the programmable timer, the port number is 8 | 88 LD) H07', H'0B, H'23', or H'27', as appropriate. The timer times AB out alter a time interval given by the product 3 18/8 £ Cl < (period of © clock) x (timer counts) x 31 8 | The timer continues to run after a time-out; subsequent 5 time-outs occur at intervals of 7905 ¢ clock periods. The timer does not run if itis loaded with the value H'FF". Yoo Yoo Interrupt Logic seer. tere The interrupt logic block is programmed by output instruc- tions to the interrupt control port (port H'06", H'0A’, H'22", or 1°26, as appropriate). Only the least significant two bits are used: their interpretation is as follows. i i + + + Contents of ICP Interpretation stanoano ew pra pmecr onve oureur "sure Sore B'XXXXXX00" Disable all interrupts B'XXXXXKOT! Enable external interrupt, disable timer interrupt Each W/O port pin is a wire-AND structure between an inter- nal output data latch and the external signal. The latch is BIXXXXXX10" Disable all interrupts loaded from the data bus. The output latches are not B'XXXXXX11" Disable external interrupt, enable initialized by the system reset sequence. timer interrupt Note: The X designation represents “don't care” binary digits. evn 358

Interrupt Sequence In figure 5, the dashed lines on the EXT INT (El) timing il- lustrate the last opportunity for the EXT INT signal to cause Figure 5 details the interrupt sequence that occurs, whether _the last cycle of a nonprotected instruction to become a the interrupt request is from an external source through the freeze cycle. The freeze cycle is a short cycle (four © clock EXT INT pin or from the PIO device internal timer. Events periods) in all cases except where B is the decrement are labeled A through G. scratchpad instruction, in which case the freeze cycle is a long cycle (six @ clock periods). Event A An interrupt request must satisfy a set-up time requirement. The INT REG signal goes low on the next negative edge of If not satisfied, the INT REQ signal delays going low until the WRITE signal if both the PRI iN signal is low and the the next negative edge of the WRITE clock. appropriate interrupt enable bit of the ICP is set. Event B Event C Event B represents the instruction being executed when the This is a no-operation (NO-OP) long cycle, allowing time for interrupt occurs. The last cycle of B is normally the instruc: the PRI IN/PRI OUT chain to settle. At a 2-Mhz © clock rate, tion fetch for the next cycle. However, if B is not a privileg- a total of seven PIO, PSU, or MI devices can be daisy- ed instruction and the CPU interrupt control bit is set, the chained without the need for look-ahead logic. last cycle becomes a freeze cycle raher than a fetch. At the end of the freeze cycle the interrupt request latches are in- Event D hibited from altering the interrupt daisy chain so that In PSU circuits, the program counter (PO) is pushed to the sufficient time is allowed for the daisy chain to settle. stack register (P) to save the return address. The interrup- ting PIO places the lower eight bits of the interrupt vector If B is a privileged instruction, the instruction fetch is not address onto the data bus. This is always a long cycle. replaced by a freeze cycle; instead, the fetch is performed and the next instruction is executed. Although unlikely to Event E be encountered, a series of privileged instructions would be In this long cycle, the PIO places the upper eight bits of the executed sequentially. One more instruction (a protected in- interrupt vector address onto the data bus. struction) is executed after the last privileged instruction. The last cycle of the protected instruction then performs the freeze. ee Figure § Interrupt Sequence rneeze YCLE fe fe a ft rf ware J] im Liu uf Tle 8 Sal all mal | EXT INT OR 1 Pet anuer as ----h iNT REG i J or ee | ~ tf | | lt | PRTOUT OF Next P10 | | a }3 | | | | | | | ES 361

Event F Table 4 PIO Functions Versus ROMC States In this short cycle, the PIO interrupting interrupt request latch is cleared, Also, the CPU interrupt control bit is ROMC State cleared, thus disabling interrupts until an El instruction is Binary PIO Functions performed. Additionally, during Event F, the PRI TN/PRT OUT daisy-chain freeze is removed, since the interrupt vector ont OF | If this circuit is interrupting and is. address has been passed to the CPU. Another action is the highest in the priority chain, move fetch of the instruction from the interrupt address. lower half of interrupt vector into the data bus. Event G , This event starts executing the first instruction of the 10000 10 | Place interrupt circuitry In an in- interrupt service routine. hibit state that prevents altering the interrupt priority chain. Summary of interrupt Sequence For the PIO, the interrupt response time is defined as the 10011 13 | If the contents of the data bus in time elapsed between the occurrence of the EXT INT signal the prior cycle was an address of going active (or the timer transition to H'N’) and the begin- VO ports on this device, move the ning of execution of the first instruction of the interrupt current contents of the data bus service routine, The interrupt response time is a variable into the appropriate port (VO A, VO dependent on what the microprocessor is doing when the B, timer or controh. interrupt rt . Pt request occurs. 11011 1B | If the contents of the data bus in ‘As shown in figure 5, the minimum interrupt response time the prior cycle was an address of is three long cycles plus two short cycles plus one write VO ports on this device, move the clock pulse width plus a set-up time of an EXT INT signal contents of the appropriate /0 prior to the leading edge of the write pulse, a total of 27 ¢ port onto the data bus (VO A clock periods plus the set-up time. At 2 MHz, this is 14.25 or 10 8). us. Although the maximum could theoretically be infinite, a practical maximum is 35 us (based on the interrupt request $e occurring near the beginning of a Pl and LR K, P sequence). Timing Characteristics ROMC States Timing signals are illustrated in figures 3, 6, and 7; the Table 4 shows the function performed by the PIO device for signal timing characteristics are presented in table 5. each ROMC command, Each function is performed entirely within one machine cycle (one cycle of the WRITE clock). All other ROMC states are decoded as NO-OP. Figure 6 F3861 Input/Output Timing ware / \\ / \\ —e be tye Iwpur it DATA MAY CHANGE DATA MAY CHANGE sp oureur i (STANDARD \\ a 29v STABLE PutLuP) ee | 3462

a Figure 7 F3861 Interrupt Logic Timing Pe “| VFA NAA te ae 7 (ss yon ware / \\ =e " int REG | av b+— toos—m ‘ts PROT Pin ia in eG ~ ial .| | toda ko exrint TTT SQ Note: Timing measurements are made at valid logic level to valid logic level of the signals references, unless otherwise noted. ES 3-63

Table 5 F3861 Timing Characteristics The ac characteristics are Vgg = OV, Voc = + 5V(+5%), Ta=0C to + 70°C. ss ec (8%), Conditions: Po © Period 05 10 Sus Pw, Pulse Width 180 Po- 180 ns tot; = ns typ. td, @ to WRITE + Delay 60 250 ns C, = 100 pF td, to WRITE — Delay 60 225 ns © = 100 pF td, WRITE to DB Input Delay 2P0+10 us PW, WRITE Pulse Width Po-100 Po ns tat; = 50 ns typ. PWs WRITE Period; Short 4Po PW, WRITE Period; Long 6Po tds WRITE to ROMC Delay 550 ns WRITE to DB Output Delay td, WRITE to OBDA- Delay |2P®+100-td, | 2P®+200] 2Po+850-td,| ns C,= 100 pF tdy WRITE to DBDR + Delay 200 ns Open Drain try WRITE to INT REQ - Delay 430 ns ©, = 100 pF(1) tr WRITE to INT REQ + Delay 430 ns C= 100 pF (3) tor, PRI IN to INT REQ — Delay 240 ns C, = 100 pF (2) tor, PRI IN to INT REQ + Delay 240 ns C, = 100 pF ted, PRI IN to PRI OUT — Delay tpd, PRI IN to PRI OUT + Delay 365 ns C, =50 pF tpdg WRITE to PRI OUT + Delay 700 ns C, = 50 pF tpdy, WRITE to PRI OUT — Delay 640 ns C, =50 pF “top WRITE to Output Stable 25 us C, =50 pF Standard Pull-up “ty VO Setup Time 13 “s th VO Hold Time 0 ns *tex EXT iNT Setup Time 400 ns Notes: 1. Assume Priority In was enabled (PRI iN = 0) in the previous F8 cycle before the interrupt is detected in the PIO. 2. The PSU has an interrupt pending before priority in is enabled. 5. Assume the pin i od to the IVY RED Input ol the F9850 CPU. 44, The starred parameters in the table represent those most frequently ‘of importance when interfacing to an F8 system. Other parameters are typically those that are relevant between FB chips and are not normally ‘of concer to the user. 5. Input and output capacitance is 3 o 5 pF typical on all pins except Vop: Veo: and Veg. ES 364

———— eee F3861 DC Characteristics The de characteristics of the F3861 PIO are supplied in table 6. Table 6 F3861 PIO DC Characteristics Symbol [Parameter | Signal Min. | Max | units | Test Conditions Vin Input High Voltage Data Bus (DBO-DB7) 35 Yoo v Vie Input Low Voltage Vsg 08 v Vou Output High Voltage 39 Yoo v lon = — 100 pA Vou Output Low Voltage Vsg 04 v lo. = 1.6 mA Ine Input High Current 1 uA | Viy = BV, 3State mode lou Input Low Current -1 uA | Vin = Vggd-State mode Vi Input High Voltage Clock Lines 40 Vpo Vv Vie Input Low Voltage (®WRITE) Vsg 08 v I Leakage Current 1 uA | Vy = 6V Vi Input High Voltage Priority In and Control 35 Vo v Viv Input Low Voltage Lines (PRI IN, ROMCO- Vss 08 v I Leakage Current ROMC4) 1 wa _| Vy = ev Vou Output High Voltage Priority Out (PRI OUT) 39 Voo v lon = — 100 pA Vou Output Low Voltage Vss 04 v lo, = 100 pA Vou Output High Voltage interupt Request V__| Open Drain Output (1) Vou Output Low Voltage (INT REQ) Vsg 04 v jo, = 1mA \\ Leakage Current 1 uA | Vy = 6V Vou Output High Voltage | Data Bus Drive External Pull-up Vou Output Low Voltage | (OBDR) Vsg v lo, = 2mA { Leakage Current uA | Vy = 6V Vin Input High Voltage External Interrupt v Vit Input Low Voltage (©XT INT) 12 v Vic Input Clamp Voltage 15 v yy = 185 yA ta Input High Current 10 “ Vin = Yoo I Input Low Voltage -225) uA | Vy = 2v in Input Low Current -500| uA | Vi = Vos Vou Output High Voltage | 1/0 Port 39 Voo v lon = — 30 uA Vou Output High Voltage | (Standard Pull-Up) 29 Yoo v lon = ~ 100 yA Vou Output Low Voltage Vss 04 v lo. = 2mA Vin Input High Voltage 29 Vpo v Internal Pull-up to Vpp (3) Vit Input Low Voltage Vsg 08 Vv I Leakage Current, 16 | mA | Vy =04V ocIPC I Leakage Current, -20] mA | Vy=04V DC/PLIDM in Input Low Current -16 | mA _| Vw Ves) Notes: 1. Pulhup resistor to Vp. on CPU. 2. Positive current is defined as conventional current flowing into the pin referenced. 3. Hysteresis input circuit provides additional 0:3 V noise Immunity while internal/external pull-up provides TTL compatibility 4. Measured an K a high-evel 10 port OUT port. 5. Vsg = ‘V. Vop = £5V # 5%, Vag = +12 25%, Ta = 0°C t0 70°C 6. Output device oft 7, ~2.0 mA for extended temperature range. SS 365

——— F3861 The supply currents are given in table 7. Table 7 Supply Currents Symbol | Parameter | Min | Typ | Max | Units | Test Conditions loo | Vop Current 30 | 70 | ma | F = 2MHz, Outputs Unloaded log__| Veo Current 10 | 18 | mA | f= 2MHzZ, Outputs Unloaded Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those in- dicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device teliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Veo +15, -03V Vo +17V, -03V External Interrupt Input = 600 uA, + 225 yA All Other Inputs and Outputs +7 V, -03V Noe Storage Temperature = 85°C, + 150° C Al wotages are with respect t0 Vg. Operating Temperature 0*C, +70°C Recommended Operating Ranges ne Supply Voltage (Vpp) Vea Part Number Min Typ Max Min Typ Max Ves F3861 +475 V +45V 0 +525V0 +114V 0120 + 126V ov a

Ordering Information

Part Number Package Temperature Range C = Commericial Temperature Range 0° to + 70°C. F861 Ceramic c L = Limited Temperature Range - 40°C to +85°C F3861 DM Ceramic M M = Military Temperature Range — 55°C to +125°C *F3861 PC Plastic c * Version A, B, C, D, and E are stocked items. El 3-66